研究者詳細 - 渡邊　実

論文 - 渡邊　実

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A high-density optically reconfigurable gate array VLSI using variable holographic memory patterns 査読

K. Akagi, M. Watanabe

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems 2014年3月

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

Emerging Liquid Crystal Technologies IX 9004 90040M-1 2014年2月

Mono-instruction set computer architecture on a 3D optically reconfigurable gate array 査読

Hiroyuki Ito, Minoru Watanabe

2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) 173 - 176 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecondorder. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.

DOI： 10.1109/EDAPS.2013.6724417

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Many-module redundancy implementation of mono instruction set computers for 3D optical FPGAs 査読

Yuya Shirahashi, Minoru Watanabe

2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) 169 - 172 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for programmable devices for space applications is increasing day-by-day to support hardware repair functions, hardware update functions, and hardware acceleration for space systems. An optically reconfigurable gate array (ORGA) has been developed as a robust multi-context field programmable gate array that is quite suitable for such space applications. The ORGA can be reconfigured using corrupt configuration data with nanosecond-order reconfiguration speed. Currently, we also propose a mono-instruction set computer architecture exploiting the high-speed dynamic reconfiguration. Using the mono-instruction set computer architecture, many-module redundancy over triple module redundancy (TMR) can be realized. This paper presents one demonstration result of a mono-instruction set computer and its robust capabilities.

DOI： 10.1109/EDAPS.2013.6724416

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Color configuration method for an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT) 406 - 409 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a proposal of a color configuration method for an optically reconfigurable gate array (ORGA). A conventional ORGA consists of a single-wavelength laser array to address configuration contexts. However, the new ORGA has lasers of some other wavelength inside a laser array. Consequently, the addressable number of configuration contexts can be increased.

DOI： 10.1109/FPT.2013.6718400

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FPGA Blokus Duo Solver using a massively parallel architecture 査読

Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe

PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT) 494 - 497 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

DOI： 10.1109/FPT.2013.6718426

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A dynamic optically reconfigurable gate array using a blue laser 査読

Takayuki Kubota, Minoru Watanabe

4th International Conference on Photonics, ICP 2013 - Conference Proceeding 129 - 131 2013年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, optically reconfigurable gate arrays (ORGAs), which can support a high-speed dynamic reconfiguration with numerous reconfiguration contexts, have been developed. Although an ORGA is a three-dimensional VLSI, no through-silicon via (TSV) technology or any micro-bump technology is never necessary to produce an ORGA. A three-dimensional ORGA uses only free-optical connections and a volume-type holographic memory technology. Therefore, the yield ratio of ORGAs is so high that ORGAs can easily be produced with no concern related to production variation. In this study, to increase the gate density, a short wavelength laser of 404 nm is applied to ORGA architecture. This paper presents the reconfiguration capabilities of the reconfiguration period and retention time of the photodiode memory architecture of a newly fabricated ORGA-VLSI. © 2013 IEEE.

DOI： 10.1109/ICP.2013.6687090

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Angle-multiplexing recording of multi-context for optically reconfigurable gate array in holographic memory using liquid crystal composites 査読

Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

2013 18TH MICROOPTICS CONFERENCE (MOC) 2013年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using successive laser exposures in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The configuration contexts corresponding to the various logical circuits are reconstructed by the laser illumination at different incident angle in the HPDLC memory.

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Temperature dependence of anisotropic diffraction in holographic polymer-dispersed liquid crystal memory 査読

Akifumi Ogiwara, Minoru Watanabe, Retsu Moriwaki

APPLIED OPTICS 52 ( 26 ) 6529 - 6536 2013年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Grating devices using photosensitive organic materials play an important role in the development of optical and optoelectronic systems. High diffraction efficiency and polarization dependence achieved in a holographic polymer-dispersed liquid crystal (HPDLC) grating are expected to provide polarization-controllable optical devices, such as a holographic memory for optically reconfigurable gate arrays (ORGAs). However, the optical property is affected by the thermal modulation around the transition temperature (T-ni) where the liquid crystal (LC) changes from nematic to isotropic phases. The temperature dependence of the diffraction efficiency in HPDLC grating is investigated using four types of LC composites comprised of LCs and monomers having different physical properties such as T-ni and anisotropic refractive indices. The holographic memory formed by the LC with low anisotropic refractive index and LC diacrylate monomer implements optical reconfiguration for ORGAs at a high temperature beyond T-ni of LC. (c) 2013 Optical Society of America

DOI： 10.1364/AO.52.006529

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IMAGE RECOGNITION OPERATION ON A DYNAMICALLY RECONFIGURABLE VISION ARCHITECTURE 査読

Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito

2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS 1 - 4 2013年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

DOI： 10.1109/FPL.2013.6645603

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A fine-grained dependable optically reconfigurable gate array as a multi-soft-core processor platform 査読

Retsu Moriwaki, Minoru Watanabe

Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 7 - 12 2013年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Optically reconfigurable gate arrays (ORGAs) have been developed as high-speed reconfigurable fine grained gate arrays that can accommodate implementation of a multi-soft-core processor. An ORGA's programmable gate array can be reconfigured in nanosecond-order with one of more than 256 reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the functions of a multi-core processor. In addition to that beneficial feature, ORGAs have high dependability against space radiation since the ORGA can be reconfigured with an error-included configuration context. In this paper, while maintaining its highly dependable capability, a more advanced dependability-increasing technique using a negative logic implementation is proposed. The dependability of data on a holographic memory depends on the number of bright bits or the binary state H included in a configuration context. If the number of bright bits in a configuration context can be decreased, then the configuration dependability can also be increased. The proposed optical configuration dependability-increasing technique of a negative logic implementation can decrease the number of bright bits in a configuration context. This technique can raise the ORGA's configuration dependability level even further. This paper describes an experimental demonstration of the usefulness of the proposed technique. © 2013 IEEE.

DOI： 10.1109/MCSoC.2013.33

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Fourier transformation on an optically reconfigurable gate array 査読

Hiroyuki Ito, Minoru Watanabe

2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) 193 - 196 2013年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, optically reconfigurable gate arrays (OR-GAs) consisting of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI have been developed to realize fast reconfiguration and numerous reconfiguration contexts. Numerous configuration contexts can be stored on a holographic memory and can be programmed dynamically onto a gate array in a nanosecond-order period. Such highspeed dynamic reconfiguration enables a large virtual gate over a physical gate, for example a 1 Tera-gate VLSI. However, in addition to the advantages, the ORGA architecture allows high-speed optical Fourier transformation by addition of a programmable Fresnel lens. This paper presents a proposal of a new ORGA architecture to support Fourier transformation and results of its demonstration.

DOI： 10.1109/MWSCAS.2013.6674618

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Configuration on an optically reconfigurable gate array under the maximum 120°C temperature condition 査読

R. Moriwaki, M. Watanabe, A. Ogiwara

OptoElectronics and Communications Conference 1 - 2 2013年7月

A 7-depth search FPGA Connect6 Solver 査読

R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, A. Tanigawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 95 - 98 2013年6月

Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method 査読

Yuichiro Yamaji, Minoru Watanabe

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013 172 - 177 2013年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We have been developing Optically Reconfigurable Gate Arrays (ORGAs) with higher radiation tolerance than that of a Field Programmable Gate Array (FPGA). The ORGA configuration is extremely robust against radiation. Moreover, that radiation tolerance of ORGA's programmable gate array can be increased by exploiting the advantageous high-speed dynamic reconfiguration of an ORGA. Although an ORGA has such a radiation-tolerance benefit, a lot of lasers that are necessary for addressing a holographic memory present concerns related to cost. Therefore, MEMS technology was introduced to reduce the number of lasers. Using a novel interleaving method, the reconfiguration speed is maintained as 10 ns: 1000 lasers and 1,000,000 MEMS mirrors can address one million configuration contexts. This paper presents a proposal of more advanced technique by which one mirror can address four configuration contexts by controlling the mirror angle. Although MEMS mirrors are not expensive, the proposed method contributes to the miniaturization of an ORGA package and to weight reduction. © 2013 IEEE.

DOI： 10.1109/AHS.2013.6604242

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A dependability-increasing demonstration for a 16-configuration context optically reconfigurable gate array 査読

A. Tanigawa, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 129 - 132 2013年6月

Formation of holographic memory by recording of multi-context in liquid crystal composites

Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

2013 Conference on Lasers and Electro-Optics Pacific Rim (CLEOPR) 1 - 2 2013年6月

Dependability-increasing technique for a multi-context optically reconfigurable gate array 査読

Akira Tanigawa, Minoru Watanabe

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1568 - 1571 2013年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array with more than 100 reconfiguration contexts can be reconfigured in nanosecondorder. In addition to that beneficial feature, ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment. Even if 35 % or 5,915 pixels of holographic memory data are damaged by high-energy charged particles, the ORGA can execute configuration operations correctly. Therefore, ORGAs are sufficiently robust devices for use in spaceradiation environments. This paper presents a proposal of a more advanced dependability-increasing technique on a multicontext ORGA. This technique can raise the ORGA's level of configuration dependability even further by exploiting multicontext implementation.

DOI： 10.1109/ISCAS.2013.6572159

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0.18 μm CMOS process photodiode memory 査読

T. Kubota, M. Watanabe

IEEE International Symposium on Circuits and Systems 1464 - 1467 2013年5月

MEMS interleaving method for optically reconfigurable gate arrays 査読

Y. Yamaji, M. Watanabe

IEEE International Conference on Electro/Information Technology 172 - 177 2013年5月

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