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A 16-laser array for an optically reconfigurable gate array 査読

Takahiro Watanabe, Minoru Watanabe

2011 International Conference on Space Optical Systems and Applications, ICSOS'11 255 - 260 2011年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a robust VLSI chip that is useful for operating under a radiation-rich space environment, such as spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. This paper presents a robust 16-laser array for an optically reconfigurable gate array and its demonstration results. © 2011 IEEE.

DOI： 10.1109/ICSOS.2011.5783679

A configuration-speed acceleration method for a sequential circuit using a negative logic implementation 査読

Retsu Moriwaki, Minoru Watanabe

2011 International Conference on Space Optical Systems and Applications, ICSOS'11 213 - 217 2011年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

An optically reconfigurable gate array (ORGA) was developed recently as one multi-context device to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers, but such lasers increase the ORGA power consumption and package size. In some cases, they might even require a cooling system. For that reason, this paper presents a configuration speed acceleration method for a sequential circuit using a negative logic implementation without ORGA architecture modification and without any increase of laser power. Based on experimentally obtained results, this paper clarifies the acceleration method's effectiveness. © 2011 IEEE.

DOI： 10.1109/ICSOS.2011.5783670

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control 査読

Mao Nakajima, Minoru Watanabe

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 4 ( 2 ) 2011年5月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ASSOC COMPUTING MACHINERY

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

DOI： 10.1145/1968502.1968506

Reduction method of refresh cycles for a dynamic optically reconfigurable gate array 査読

Y. Aoyama, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 2011年4月

Programming Options for an Optical FPGA with Clockwise Dynamic Reconfigurability 査読

F. Matsusaki, F. Kobayashi, A. Nagino, M. Watanabe

International Conference on Innovative Computing and Communication and Asia-Pacific Conference on Information Technology and Ocean Engineering 2011年3月

MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays 査読

Hironobu Morita, Minoru Watanabe

RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS 6578 242 - 252 2011年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Optically reconfigurable gate array (ORGAs) were developed to realize next-generation large-virtual gate count programmable VLSIs. An ORGA consists of an ORGA-VLSI, a holographic memory, and a laser array, which is used for addressing the holographic memory. Since many configuration contexts can be stored on a volume-type holographic memory, the corresponding number of lasers must he implemented on an ORGA. However, a laser array with numerous lasers is always expensive. Therefore, to accommodate numerous configuration contexts with fewer lasers, this paper presents a novel method using an interleaving read operation of a holographic memory for ORGAs. This method can provide an addressing capability of a billion configuration contexts along with a nanosecond-order high-speed configuration capability.

DOI： 10.1007/978-3-642-19475-7_25

A 144-configuration context MEMS optically reconfigurable gate array 査読

Yuichiro Yamaji, Minoru Watanabe

2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) 237 - 241 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for space uses of FPGAs is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. However, under a space radiation environment, the incidence of high-energy charged particles causes single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 144-configuration context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment.

DOI： 10.1109/SOCC.2011.6085083

A 64-context MEMS optically reconfigurable gate array 査読

Yuichiro Yamaji, Minoru Watanabe

2010 International Conference on Field-Programmable Technology 499 - 502 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for use of FPGAs in space is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. Under a space radiation environment, embedded devices must allow for incidence of high-energy charged particles. Such incidence can cause single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 64-context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment. © 2010 IEEE.

DOI： 10.1109/FPT.2010.5681467

Fiber remote configuration for an optically reconfigurable gate array with four configuration contexts 査読

Yumiko Ueno, Minoru Watanabe

OPTICS COMMUNICATIONS 283 ( 23 ) 4614 - 4618 2010年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ELSEVIER SCIENCE BV

A function enabling remote programming is necessary for systems used with nuclear power plants, high-energy physics experiments, and other plants with no personnel Recently, optically reconfigurable gate array (ORGA) architecture has been developed to achieve a huge virtual gate count that is much greater than those of currently available VLSIs However, ORGA architectures have never supported a remote programming capability since a complicated holographic writer system is required along with an ORGA for that purpose. This paper therefore presents a proposal of a new remotely reconfigurable gate array architecture with four configuration contexts that enable remote reconfiguration using optical fiber networks Furthermore, this paper presents discussion of the availability of this architecture and plans based on the experimental results (C) 2010 Elsevier B V All rights reserved

DOI： 10.1016/j.optcom.2010.06.090

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capabilit 査読

D. Seto, M. Nakajima, M. Watanabe

Applied Optics 49 ( 36 ) 6986 - 6994 2010年12月

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability 査読

Daisaku Seto, Mao Nakajima, Minoru Watanabe

APPLIED OPTICS 49 ( 36 ) 6986 - 6994 2010年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 mu m three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 mu s partial reconfiguration. (C) 2010 Optical Society of America

Multi-context programmable optically reconfigurable gate array using a silver-halide holographic memory 査読

Shinya Kubota, Minoru Watanabe

2010 IEEE/SICE International Symposium on System Integration: SI International 2010 - The 3rd Symposium on System Integration, SII 2010, Proceedings 431 - 435 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, as one dynamic reconfigurable device, optically reconfigurable gate arrays (ORGAs) that consist of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve greater than 1 Teragate virtual integration, which is much greater than the integration that is possible using currently available VLSIs. If the ORGA can be used, a large software system can be implemented directly as hardware so that a large real-time system can be realized. Currently, a programmable ORGA architecture has been proposed to support user programmability. This paper presents the demonstration result of a multi-context programmable ORGA using a silver-halide non-volatile holographic memory and a corresponding writer system. ©2010 IEEE.

DOI： 10.1109/SII.2010.5708364

Othello solver based on a soft-core MIMD processor array 査読

Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe

2010 International Conference on Field-Programmable Technology 511 - 514 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchronous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results. © 2010 IEEE.

DOI： 10.1109/FPT.2010.5681470

Background light effect of a dynamically reconfigurable vision-chip architecture 査読

Retsu Moriwaki, Minoru Watanabe

2010 IEEE/SICE International Symposium on System Integration: SI International 2010 - The 3rd Symposium on System Integration, SII 2010, Proceedings 426 - 430 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, demands for implementation of a high-speed image recognition function onto autonomous vehicles and robots, that is superior to that of the human eye, have been increasing. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, realizing such high-speed real-time image recognition operation is extremely difficult because the template information transfer rate and template matching operation cycle reach the order of Petapixel/s. Therefore, to accommodate template matching operations that can be executed at rates greater than Petapixel/s, a dynamically reconfigurable vision-chip architecture has been developed in which a holographic memory technique is introduced to current VLSI technology. However, the dynamically reconfigurable vision-chip architecture must receive image information in addition to configuration context information. At such a time, a salient concern is that image information light might reduce the retention time of photodiode memories on a dynamically reconfigurable vision-chip. This paper therefore clarifies that the background light does not affect the photodiode memories on a dynamically reconfigurable vision-chip architecture. ©2010 IEEE.

DOI： 10.1109/SII.2010.5708363

A retention time improvement method for a MEMS dynamic optically reconfigurable gate array 査読

Hironobu Morita, Minoru Watanabe

2010 International Symposium on Micro-NanoMechatronics and Human Science: From Micro and Nano Scale Systems to Robotics and Mechatronics Systems, MHS 2010, Micro-Nano GCOE 2010, Bio-Manipulation 2010 257 - 261 2010年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, optically reconfigurable gate arrays (ORGAs) have been developed to address high-speed operations. During that development, a MEMS dynamic optically reconfigurable gate array architecture was proposed: it perfectly removes the static configuration memory to store a context and uses junction capacitances of photodiodes as dynamic configuration memory to realize high-gate count ORGA-VLSI. However, this architecture presents the issue that retention time of programmed circuits on a gate array is, just like DRAMs, not infinite. Since the circuit reconfiguration frequency is always superior to the refresh cycle frequency, the refresh cycle problem need not be considered. However, circuits with a long lifetime exist among the many implementation circuits. For these circuits, many refresh cycles must be required continuously. Therefore, This paper presents a proposal of a retention time improvement method by adjusting the threshold level in the holographic memory calculation. ©2010 IEEE.

DOI： 10.1109/MHS.2010.5669547

High-speed fiber-linked remote reconfiguration 査読

Yumiko Ueno, Minoru Watanabe

TENCON 2010 - 2010 IEEE Region 10 Conference 1203 - 1206 2010年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, fiber networks and undersea fiber optic cables have become widely used throughout the world. Because of its much lower attenuation and interference, optical fiber is superior to copper wires for long-distance applications. Such fibers' transfer rates and distances reach GHz-order and over 100 km. Up to now, a remote configurable FPGA system using current fiber networks was reported. However, since its configuration speed was very low, dynamic highspeed reconfiguration was impossible. This paper therefore presents a high-speed remote reconfiguration experiment using a bundle of fiber networks and an optically reconfigurable gate array. Such architecture presents the possibility of a remote high-speed dynamic reconfigurable hardware system.

DOI： 10.1109/TENCON.2010.5686374

Template matching operations on a dynamically reconfigurable vision-chip architecture 査読

Hironari Nakada, Minoru Watanabe

2010 10th International Symposium on Communications and Information Technologies 1091 - 1096 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper experimentally presents a template matching operations on a dynamically reconfigurable vision-chip architecture. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665152

Formation of holographic memory using subwavelength grating mask for optically reconfigurable gate array 査読

A. Ogiwara, M. Watanabe, T. Mabuchi, F. Kobayashi

MICROOPTICS CONFERENCE 108 - 109 2010年10月

Development of optically reconfigurable gate arrays

Minoru Watanabe

International Symposium on Optical Memory 188 - 189 2010年10月

Fault tolerance of a holographic storage system 査読

Takahiro Watanabe, Minoru Watanabe

2010 10th International Symposium on Communications and Information Technologies 1126 - 1130 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand is increasing daily for large storage systems that are useful for devices operating under a radiation-rich space environment, such as spacecraft, space satellites, and space robots. A holographic storage system, which can easily provide large storage capacity, is a candidate for space embedded systems. The holographic storage system, which requires no rotation mechanism, usually consists of a holographic memory material, a laser array, and a photodiode array. Although a holographic memory itself is an extremely robust device for use in a space radiation environment, its associated components are vulnerable to radiation. Such vulnerable devices can cause severe problems by preventing the reading of all holographic memory contents. This is a turn-off failure mode of a laser array. This paper therefore presents a recovery method for a turn-off failure mode of a laser array on a holographic storage system and presents results of its demonstration. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665158

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