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論文 - 渡邊　実

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Multi-speed configuration for ORGAs 査読

M. Nakajima, M. Watanabe

International Topical Meeting on Information Photonics 166 - 167 2008年11月

Liquid crystal holographic configurations for ORGAs 査読

YAMAGUCHI Naoki, WATANABE Minoru

APPLIED OPTICS 47 ( 26 ) 4692 - 4700 2008年10月

Liquid crystal holographic configurations for optically reconfigurable gate arrays 査読

Naoki Yamaguchi, Minoru Watanabe

APPLIED OPTICS 47 ( 26 ) 4692 - 4700 2008年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

An optically reconfigurable gate array (ORGA) system, which consists of an ORGA very large scale integration (VLSI), an easily rewritable liquid crystal holographic memory recording four configuration contexts, and a laser array, is proposed. Circuits on a gate array of the ORGA-VLSI can be programmed rapidly by exploiting large parallel connections between a holographic memory and a gate array VLSI; that programming can be executed even as it is being programmed. Consequently, the gate array can be switched from a certain circuit to another circuit instantaneously. We present a demonstration of the ORGA system and experimental results. (C) 2008 Optical Society of America

Optical configuration using a silver-halide holographic memory including four configuration contexts 査読

D. Seto, M. Watanabe

International Conference on Solid State Devices and Materials 116 - 117 2008年9月

A 770ns holographic reconfiguration of a four-context DORGA 査読

M. Nakajima, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 289 - 292 2008年7月

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration ? a 6502 Perspective- 査読

F. Kobayashi, Y. Morikawa, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 222 - 228 2008年7月

A dynamic optically reconfigurable gate array - Perfect emulation 査読

Daisaku Seto, Minoru Watanabe

IEEE JOURNAL OF QUANTUM ELECTRONICS 44 ( 5-6 ) 493 - 500 2008年5月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.

DOI： 10.1109/JQE.2008.916705

Multi-optical configuration using spreading beams 査読

Naoki Yamaguchi, Minoru Watanabe

2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 386 - 389 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. For the laser diode array, a conventional ORGA always required collimated beams, necessitating the use of some lenses and its accurate alignment. Therefore, this paper presents the very compact and simple architecture of a multi-context ORGA that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results of implementation of two configuration contexts and their reconfigurations, in addition to plans for future work.

DOI： 10.1109/MWSCAS.2008.4616817

A 937.5 ns multi-context holographic configuration with a 30-75 mu s retention time 査読

Mao Nakajima, Daisaku Seto, Minoru Watanabe

2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8 3502 - 3507 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However in ORGAs, although a large virtual gate count can be realized by exploiting the large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is still important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However to date, although only a 1.83-1.89 ms single-context holographic configuration and a retention time of 3.495.61 s of DORGA architecture have been confirmed, the performance at nanosecond-scale reconfiguration with a multi-context DORGA architecture has never been analyzed. Therefore, this paper presents the experimental result of a 937.5 ns multi-context holographic configuration and a 30.75 mu s retention time of DORGA architecture. The advantages of this architecture are discussed in relation to the results of this study.

DOI： 10.1109/IPDPS.2008.4536539

Dynamic holographic reconfiguration on a four-context ODRGA 査読

Mao Nakajima, Minoru Watanabe

2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS 173 - 178 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Reconfiguration applications based on reconfigurable devices present new computational paradigms because, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory have been developed to realize rapid reconfigurations and numerous reconfiguration contexts. In addition, optically differential reconfigurable gate arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results that elucidate aspects of fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

DOI： 10.1109/ASAP.2008.4580174

Inversion/non-inversion dynamic optically reconfigurable gate array 査読

Minoru Watanabe, Mao Nakajima

PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS 249 - + 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：WORLD SCIENTIFIC AND ENGINEERING ACAD AND SOC

Up to now, an optically differential reconfigurable gate array taking a differential reconfiguration strategy and a dynamic optically reconfigurable gate array taking a photodiode memory architecture have been proposed. The differential reconfiguration strategy can increase the reconfiguration frequency, with no increase in laser power, compared to other optically reconfigurable gate arrays, but the differential reconfiguration strategy can not achieve a high gate count VLSI because of the area occupied by static configuration memory. On the other hand, the dynamic optically reconfigurable gate array can achieve a high-gate count VLSI, but its configuration speed is slower than that of the optically differential reconfigurable gate array using equivalent laser power. Therefore, to realize both advantages of rapid configuration and a high gate count, this paper presents a novel inversion/non-inversion dynamic optically reconfigurable gate array that combines both architectures. In this study, the effectiveness of the inversion/non-inversion optical configuration method is clarified through some experiments.

Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI 査読

Shinichi Kato, Minoru Watanabe

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY 377 - 380 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a novel inversion / non-inversion zero-overhead dynamic optically reconfigurable gate array that can extract good factors from architectures of both optically differential reconfigurable gate arrays and dynamic optically reconfigurable gate arrays. A full VLSI design using a 0.35 mu m CMOS process technology is presented. Based on that presentation, three factors are discussed: gate density; reconfiguration frequency per unit of laser power, optical power consumption.

DOI： 10.1109/FPT.2008.4762422

An 11,424-gate dynamic optically reconfigurable gate array VLSI 査読

Mao Nakajima, Minoru Watanabe

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY 293 - 296 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A DORGA architecture has been proposed to increase gate density It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the world's largest 11,424 gate-count dynamic optically reconfigurable gale array (DORGA) VLSI fabricated on a 96.04 mm(2) chip using a 0.35 mu m three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture arc, discussed in relation to the results described herein.

An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays 査読

Takayuki Mabuchi, Minoru Watanabe

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY 289 - 292 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

In previously proposed ORGAs, the optical reconfiguration period was designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory differs depending on the number of bright bits included in a configuration context. Therefore, previous ORGAs can not fully exploit reconfiguration performance. For that reason, this paper presents a proposal for an analog reconfiguration-period adjustment technique for ORGAs to reduce each reconfiguration period. The advantages are then discussed herein based on experimental results obtained using an ORGA system on which the technique is adopted.

DOI： 10.1109/FPT.2008.4762400

An acceleration and optimization method for optical reconfiguration 査読

Minoru Watanabe, Naoki Yamaguchi

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS 607 - 612 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.

DOI： 10.1109/VLSI.2008.26

A dynamic optically reconfigurable gate array with a silver-halide holographic memory 査読

Daisaku Seto, Minoru Watanabe

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008 511 - 514 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To increase gate density, a dynamic optically reconfig-urable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted, thereby demonstrating its availability. However, because the resolution of the liquid crystal holographic memory is very low and because the storable configuration contexts are numerically limited to four, that estimation cannot be considered a practical experiment. Therefore, this paper presents a practical demonstration of the DORGA architecture using a silver-halide holographic memory that can store over 3,000 configuration contexts. The DORGA architecture performance, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study. ©2008 IEEE.

DOI： 10.1109/ISVLSI.2008.94

Defect tolerance of holographic configurations in ORGAs 査読

Kouji Shinohara, Minoru Watanabe

2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8 3488 - 3495 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the perfectly parallel programmable capability of ORGAs enables perfect avoidance of those defective areas through alternative use of other non-defective areas. Moreover holographic memories to store contexts are known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Moreover the damage of some fraction rarely affects its diffraction pattern or a reconfiguration context. Therefore, ORGAs are very robust against component defects in devices such as laser arrays, gate arrays, and holographic memory, and are particularly useful for space applications, which require high reliability. However, to date, the degree to which defects in a holographic memory affects holographic configurations has never been analyzed. Therefore, this paper describes analysis results of defect limitations of holographic configurations.

DOI： 10.1109/IPDPS.2008.4536537

An optical reconfiguration system with four contexts 査読

Naoki Yamaguchi, Minoru Watanabe

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS 601 - 606 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. It is noteworthy that ORGA-VLSIs which can be reconfigured in nanoseconds without any overhead have already been fabricated. However to date, no multiholographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has ever been developed. As the first step toward realizing such a device, a four-context optical system is demonstrated experimentally using a liquid crystal spatial light modulator and a He-Ne laser This paper describes those experimental results and plans for future work.

DOI： 10.1109/VLSI.2008.27

Programmable Optically Reconfigurable Gate Array Architecture using a PAL-SLM 査読

Shinya Kubota, Minoru Watanabe

2008 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION 100 - 104 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve huge virtual gate counts that is much larger than those of currently available VLSIs. Using ORGA architecture, greater than 1 tera gate count VLSIs are possible by exploiting the storage capacity of a holographic memory. Conventional ORGAs have only one shortcoming compared with current field programmable gate arrays (FPGAs) : they are not reprogrammable after their fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and implemented into the ORGA package with high precision beyond that available by manual assembly. To improve that shortcoming, this paper presents the world's first programmable ORGA architecture and experimental results. Furthermore, in light of those experimental results, this paper presents discussion of the availability of this architecture and future plans.

DOI： 10.1109/SI.2008.4770434

Optical configuration of an 11,424 gate-count dynamic optically reconfigurable gate array using a VCSEL 査読

Daisaku Seto, Minoru Watanabe

2008 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION 95 - 99 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, to realize large real-time systems, demands for fast computation on large VLSI have continued to increase. An optically reconfigurable gate array has been developed to realize large virtual gates. As part of that research effort, the world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on a concept using junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm(2) and a 0.35 mu m-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper presents an experimental result of along retention time of its photodiode memory architecture.

DOI： 10.1109/SI.2008.4770433

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