研究者詳細 - 渡邊　実

Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation 査読

Power consumption of mono-instruction set computers (MISCs) 査読

H. Ito, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 2013年4月

Retsu Moriwaki, Minoru Watanabe

Applied Optics 52 ( 9 ) 1939 - 1946 2013年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OSA - The Optical Society

This paper presents a proposal of an optical configuration acceleration method applied to optically reconfigurable gate arrays (ORGAs) using a negative logic implementation. The gate array of an ORGA is reconfigured using a holographic memory. The reading time of a holographic memory depends on the number of bright bits included in a configuration context. The proposed optical configuration acceleration method can decrease the number of bright bits. As a result, the proposed optical configuration acceleration method can increase the reconfiguration frequency. In this paper, a fabricated ORGA very large scale integration that can support the optical configuration acceleration method is estimated. Consequently, this paper shows that the reconfiguration frequency of the proposed method is 1.97 times higher than those of conventional ORGA architectures with no increase of laser power. © 2013 Optical Society of America.

DOI： 10.1364/AO.52.001939

Dependability-increasing method of processors under a space radiation environment 査読

Yuya Shirahashi, Minoru Watanabe

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7806 218 2013年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) can be reconfigured using error-inclusive configuration contexts under a radiation-rich space environment. Therefore, the ORGA presents an important benefit: the allowable amount of configuration data damage is greater than that by field programmable gate arrays (FPGAs) with error-checking and correction. However, the ORGA's programmable gate array itself is never as robust against space radiation as that of an application-specific integrated circuit (ASIC) because the programmable architecture of its gate array is the same as that of FPGAs. Therefore, to achieve a drastic increase in the robust capability of a fine-grained programmable gate array on an ORGA-VLSI, this paper presents a proposal of a novel dynamic module multiple redundancy scheme based on a mono-instruction set computer architecture exploiting high-speed dynamic reconfiguration. © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-36812-7_21

A 9-configuration-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory

Temperature Dependable Holographic Memory Using Holographic Polymer-dispersed Liquid Crystal 査読

A. Ogiwara, M. Watanabe, R. Moriwaki

Progress In Electromagnetics Research Symposium 322 - 325 2013年3月

R. Moriwaki, M. Watanabe, A. Ogiwara

Takayanagi Kenjiro Memorial Symposium 112 ( 325 ) S3_10_1 - S3_10_4 2012年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：一般社団法人電子情報通信学会

我々は現在,レーザアレイ,ホログラムメモリ,ゲートアレイVLSIから構成され,光による高速動的再構成が可能な光再構成型ゲートアレイを研究開発している.光再構成型ゲートアレイの特徴として,高速動的再構成と大規模なコンテキスト情報数の記憶が挙げられる.しかし,これまで光再構成型ゲートアレイは構造上,コンテキスト情報数に応じてレーザが必要なので,既存のプログラマブルデバイスと比較して価格が高くなるという問題点があった.そこで我々は,偏光依存性ホログラムメモリを用いることにより,レーザ数を削減できる光再構成型ゲートアレイのアーキテクチャを考案した.本稿では,偏光依存性ホログラムメモリを用いた9コンテキスト光再構成型ゲートアレイの試作結果について報告する.

CiNii Article

CiNii Books

A uniform partitioning method for mono-instruction set computer (MISC) 査読

Hiroyuki Ito, Minoru Watanabe

Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012 832 - 837 2012年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As gates in field programmable gate arrays (FPGAs) become usable in ever-increasing numbers, FPGAs are becoming more widely applied in various embedded systems. FPGAs have been demonstrated as useful renewable devices. Recently however, a hard-core processor inside an FPGA is frequently used for high-performance systems so that the implementation of the hard-core processor decreases the possibility of a specification change and reuse of its FPGA. Therefore, demand for implementing a soft-core processor onto an FPGA is gaining. In response to that demand, FPGA vendors have provided soft-core processors for FPGAs, but those processors invariably provide lower performance than hard-core processors do. Therefore, this paper presents high-performance mono-instruction set computer (MISC) architecture that fully exploits the programmability of a dynamically reconfigurable fine-grained gate array. In addition, this paper presents a proposal of a uniform partitioning method for the MISC architecture. © 2012 IEEE.

DOI： 10.1109/NBiS.2012.107

A 256-configuration-context MEMS optically reconfigurable gate array 査読

Y. Yamaji, M. Watanabe

International Conference on Solid State Devices and Materials 232 - 233 2012年9月

Inversion/non-inversion reconfiguration scheme for a 0.18 μm CMOS process optically reconfigurable gate array VLSI 査読

Takahiro Watanabe, Minoru Watanabe

2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) 117 - 120 2012年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present advantageous capabilities compared with other ORGAs: they have increased the reconfiguration frequency per unit of laser power and have reduced optical configuration power consumption. On the other hand, dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density, but an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical configuration power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array has been developed, adopting only the best attributes from both architectures. This paper presents an inversion/non-inversion implementation for a newly fabricated 0.18 mu m CMOS process optically reconfigurable gate array VLSI.

DOI： 10.1109/MWSCAS.2012.6291971

0.18 μm CMOS Process highly sensitive differential optically reconfigurable gate array VLSI 査読

Takahiro Watanabe, Minoru Watanabe

2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) 308 - 313 2012年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, demand is increasing for high-speed dynamic reconfiguration on programmable devices to improve their performance. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been undergoing rapid development. Moreover, to more increase the reconfiguration speed, optically differential reconfigurable gate arrays (ODRGAs) incorporating a differential reconfiguration method between configuration contexts have been developed. An ODRGA comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Its large-bandwidth optical connection enables high-speed reconfiguration. However, photodiode sensitivities of conventional ODRGAs are not good. This paper therefore presents a newly fabricated 0.18 mu m CMOS process optically differential reconfigurable gate array VLSI chip with highly sensitive photo-circuits.

DOI： 10.1109/ISVLSI.2012.71

A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function 査読

Takashi Yoza, Minoru Watanabe

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 361 - 366 2012年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a robust VLSI chip that is useful in a radiation-rich environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a radiation-tolerant Field Programmable Gate Array (FPGA). The ORGA architecture is extremely robust against multi-event upsets. Moreover, it can recover from permanent errors resulting from a heavy total radiation dose. This paper presents demonstration results of a 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed-adjustment function. © 2012 IEEE.

DOI： 10.1109/FPL.2012.6339205

Optical reconfiguration by anisotropic diffraction in holographic polymer-dispersed liquid crystal memory 査読

Akifumi Ogiwara, Minoru Watanabe

APPLIED OPTICS 51 ( 21 ) 5168 - 5177 2012年7月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Holographic polymer dispersed liquid crystal (HPDLC) memory is fabricated by a photoinduced phase separation comprised of polymer and liquid crystal (LC) phases using laser light interference exposures. The anisotropic diffraction induced by the alignment of LC in the periodic structure of the HPDLC memory is applied to reconstruct the configuration contexts for the optically reconfigurable gate arrays. Optical reconfiguration for various circuits under parallel programmability is implemented by switching the polarization state of incident light on the HPDLC memory using a spatial light modulator. (C) 2012 Optical Society of America

DOI： 10.1364/AO.51.005168

Methods for detection and compensation of alignment errors occurring between a programmable optically reconfigurable gate array and its writer system 査読

Shinya Kubota, Minoru Watanabe

PROCEEDINGS OF THE 2012 IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON) 182 - 185 2012年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSls. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, in contrast to current field-programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: alignment errors arise when a programmable ORGA is recorded with a writer system. When programming a programmable ORGA along with alignment errors between the programmable ORGA and its writer system, the reconfiguration speed of the programmable ORGA is decreased. This paper therefore presents a detection and compensation method of alignment errors between a programmable ORGA and a writer system to alleviate that shortcoming.

DOI： 10.1109/NAECON.2012.6531052

Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation 査読

R. Moriwaki, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 127 - 132 2012年7月

A 4-configuration context fiber-linked optically reconfigurable gate array 査読

Yumiko Ueno, Minoru Watanabe

Technical Digest - 2012 17th Opto-Electronics and Communications Conference, OECC 2012 592 - 593 2012年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, fiber networks and undersea fiber optic cables have become widely used throughout the world. Because of its much lower attenuation and interference, optical fiber is superior to copper wire for long-distance applications. Optical fiber data transfer rates and distances reach GHz-order and over 100 km. Previously, a remote configurable field programmable gate array (FPGA) system using current fiber networks was reported. However, since its configuration speed was very low, dynamic high-speed reconfiguration was impossible. Therefore, this paper presents a 4-configuration context fiber-linked optically reconfigurable gate array using a bundle of fiber networks and an optically reconfigurable gate array. © 2012 IEEE.

DOI： 10.1109/OECC.2012.6276587

A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array 査読

Takashi Yoza, Minoru Watanabe

2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) 92 - 98 2012年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a large-gate-count robust VLSI chip that is useful in a radiation-rich space environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. © 2012 IEEE.

DOI： 10.1109/AHS.2012.6268635

0.18 μm CMOS process high-sensitivity optically reconfigurable gate array VLSI 査読

T. Watanabe, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 147 - 151 2012年5月

FPGA Connect6 Solver with Hardware Sort Units 査読

R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, T. Watanabe, Y. Aoyama, M. Seo, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 163 - 166 2012年5月

High speed - low power optical configuration on an ORGA with a phase-modulation type holographic memory 査読

Takahiro Watanabe, Minoru Watanabe

2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW) 256 - 260 2012年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) with an amplitude-modulation type holographic memory have been developed as a type of multi-context field programmable gate array. The ORGA's programmable gate array can be reconfigured in nanosecond-order, with more than 100 reconfiguration contexts. However, the diffraction efficiency of the amplitude-modulation type holographic memory is not good because the holographic memory decreases its transmission light intensity depending on the modulation level. About half of the power of the laser is consumed by the holographic memory. Therefore, this paper presents a high-speed - low-power optical configuration capability of an ORGA with a phase-modulation type holographic memory.

DOI： 10.1109/IPDPSW.2012.28