研究者詳細 - 渡邊　実

論文 - 渡邊　実

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FPGA hardware accelerator for holographic memory calculations for optically reconfigurable gate arrays 査読

Yoshizumi Ito, Minora Watanabe

2017 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2017 146 - 149 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Radiation-hardened optically reconfigurable gate arrays have been developed for use in space embedded systems. An optically reconfigurable gate array consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI, which is one type of radiation-hardened SRAM-based field programmable gate array (FPGA). However, optically reconfigurable gate arrays have the important feature of faster scrubbing operations than that of radiation-hardened SRAM-based FPGAs. Therefore, the soft-error-tol er anees of the configuration memories of optically reconfigurable gate arrays become much higher than those of FPGAs. However, the calculation load of a lot of holographic memory patterns on a personal computer is extremely heavy. This paper therefore presents a hardware accelerator using an FPGA. The Vivado-high-level synthesis tool (Xilinx Inc.) has been used for development. Its operation speed was improved drastically from 1,590 ms to 3.12 ms while its power consumption for calculations has been decreased drastically from 55 W to 4.4 W.

DOI： 10.1109/ICSOS.2017.8357225

Optically reconfigurable gate array driven by a lithium-ion battery 査読

S. Fujisaki, M. Watanabe

IEEE CPMT Symposium Japan 227 - 230 2017年11月

Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

International System on Chip Conference 2017- 91 - 95 2017年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as the Fukushima Daiichi nuclear power plant. According to recent news, regions with 650 Sv/h radiation have been found at the Fukushima Daiichi nuclear power plant. Under such extremely high radiation environments, high-speed scrubbing operations must be used to maintain correct circuit information on the configuration memory of programmable gate arrays. Up to now, optical high-speed scrubbing based on an optically reconfigurable gate array has been proposed. This paper presents a demonstration of the radiation tolerance of the optical high-speed scrubbing based on an optically reconfigurable gate array VLSI by using lasers that emulate strong radiation environments. It has been confirmed that 70-ns period high-speed scrubbing operations on the optically reconfigurable gate array are never disturbed by the emulated radiation.

DOI： 10.1109/SOCC.2017.8226014

Asynchronous optical bus for optical VLSIs 査読

Takumi Fujimori, Minoru Watanabe

7th International Conference on Innovative Computing Technology, INTECH 2017 162 - 166 2017年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, optically reconfigurable gate arrays consisting of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI have been under development as high-speed dynamic reconfigurable devices. High-speed dynamic reconfiguration of optically reconfigurable gate arrays can be achieved using a two-dimensional optical bus. If such high-speed reconfiguration were feasible, then its programmable gate array performance could be increased dramatically. This paper presents a demonstration of high-speed asynchronous optical dynamic reconfiguration based on an optically reconfigurable gate array VLSI. The reconfiguration speed of the optically reconfigurable gate array can reach 206.44 Gbit/s.

DOI： 10.1109/INTECH.2017.8102440

Multi-context scrubbing method 査読

Takumi Fujimori, Minora Watanabe

Midwest Symposium on Circuits and Systems 2017- 1548 - 1551 2017年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Two salient concerns of current field programmable gate arrays (FPGAs) used for space applications are how to block soft errors that arise on their configuration memories and how to treat permanent failures attributable to total dose effects. To date, those two main concerns have been treated separately, but we present a proposal for multi-context scrubbing to 'kill two birds with one stone' and resolve both issues simultaneously. To decrease the frequency of soft errors arising on the configuration memories of FPGAs, applying scrubbing operations for configuration memories is extremely useful. Since faster scrubbing can increase the radiation tolerances of the configuration memories on FPGAs, optical high-speed scrubbing using optically reconfigurable gate array (ORGA) architecture is introduced. Up to now, major scrubbing operations have invariably used a single configuration context, but since the storage capacities of holographic memories on ORGAs are high, many configuration contexts can be stored on a holographic memory. Thereby, various configuration contexts that avoid permanent failures can be used cyclically for scrubbing operations. Even if a permanent failure occurs on the programmable gate array during scrubbing operations, which exploit numerous configuration contexts, correct operations can be executed.

DOI： 10.1109/MWSCAS.2017.8053231

Development of a radiation-hardened embedded system used for robots decommissioning nuclear reactors 査読

M. Watanabe

ACTINIDES2017 2017年7月

500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA 査読

Yoshizumi Ito, Minora Watanabe, Akifumi Ogiwara

2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017 167 - 171 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Currently, radiation-hardened static random access memory (SRAM) based field programmable gate arrays (FPGAS) are used frequently for space applications. Invariably, such SRAM-based FPGAS are used along with an electrically erasable programmable read-only memory (EEPROM). Although the radiation tolerance of data stored on EEPROMs is much higher than that stored on SRAMs, the radiation tolerance of the data on an EEPROM is not perfectly safe because electrons on the floating gates of transistors are also disturbed by strong radiation. If high-energy charged particles are incident to the EEPROM, then the EEPROM data might be destroyed by the radiation. In stark contrast, the radiation tolerances of holographic memories are perfect Recording and reading of holographic memory can be executed optically. They never depend on electrons or holes. Moreover, data stored on holographic memory are read by summations of numerous light waves. The operation can be regarded as a majority voting operation. Therefore, even if half of a holographic memory is removed, the remaining half of the holographic memory can generate recorded data correctly. This paper describes a holographic memory based FPGA or an optically reconfigurable gate array (ORGA). Furthermore, this paper explains that a holographic memory can function correctly up to a 500 Mrad total-ionizing-dose, exhibiting 1,667 times higher radiation tolerance than current radiation-hardened VLSIs and FPGAS.

DOI： 10.1109/AHS.2017.8046374

High-speed scrubbing based on asynchronous optical configuration 査読

Takumi Fujimori, Minoru Watanabe

2017 2nd International Conference on Opto-Electronic Information Processing, ICOIP 2017 74 - 78 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as that of the Fukushima Daiichi nuclear power plant. According to recently reported news, an area with 650 Sv/h radiation intensity has been confirmed outside of a containment vessel at the Fukushima Daiichi nuclear power plant. For uses under such extremely high radiation environments, high-speed scrubbing operations must be applied for FPGAs. A high-speed optical scrubbing method that can be used on optically reconfigurable gate arrays has been proposed in recent reports of the literature. Such optically reconfigurable gate arrays using optical high-speed scrubbing can be used in environments with intense radiation. In addition, to increase the optical scrubbing operation speed, this paper demonstrates a high-speed optical scrubbing method with a simpler sequence for use on an optically reconfigurable gate array. The 50 ns period high-speed scrubbing operation could be confirmed on the fabricated optically reconfigurable gate array VLSI.

DOI： 10.1109/OPTIP.2017.8030702

Gate density advantage of parallel-operation-oriented FPGA architecture 査読

Takumi Fujimori, Minora Watanabe

Proceedings of the IEEE National Aerospace Electronics Conference, NAECON 2017 155 - 158 2017年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.

DOI： 10.1109/NAECON.2017.8268761

Tolerance of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation 査読

Akifumi Ogiwara, Minoru Watanabe, Yoshizumi Ito

APPLIED OPTICS 56 ( 16 ) 4854 - 4860 2017年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are discussed in the application for an optically reconfigurable gate array. The radiation experiments are conducted using a cobalt 60 gamma radiation source to examine the tolerance of a 100 Mrad total ionizing dose for the HPDLC memory. The optical properties are compared in the conditions before and after gamma-ray irradiation for the fabricated HPDLC gratings. The effects of gamma-ray irradiation on the internal grating structure are also investigated by polarization optical microscopy and scanning electron microscopy observations. The HPDLC memory irradiated by a 100 Mrad total ionizing dose demonstrates the implementation of the optical reconfiguration in a gate-array VLSI. (C) 2017 Optical Society of America

DOI： 10.1364/AO.56.004854

Error injection analysis for triple modular and penta-modular redundancies 査読

Ryo Terada, Minoru Watanabe

2017 6th International Symposium on Next Generation Electronics, ISNE 2017 1 - 4 2017年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, radiation-hardened embedded systems are demanded for robots that must function in high-radiation environments such as those prevailing at the Fukushima Daiichi and Chernobyl nuclear power plants. Recent news reports have described the discovery of a 650 Sv/h radiation region near the containment vessels of the Fukushima Daiichi nuclear power plant. Even under such a dauntingly intense radiation environment, workable robots are required. This paper therefore present a high-soft-error-tolerant 16-bit adder unit based on penta-modular redundancy (SMR) in addition to triple modular redundancy (TMR). The soft-error tolerances of the TMR and SMR were analyzed theoretically. Such TMR and SMR circuits were implemented onto a field programmable gate array (FPGA). Then error-injection experiments for the TMR and SMR were done on the FPGA. Analytical results have revealed that SMR 16-bit adder circuit is useful for heavy radiation environments.

DOI： 10.1109/ISNE.2017.7968746

Motor controller radiation tolerance experiments 査読

Takumi Hatamochi, Minoru Watanabe

2017 6th International Symposium on Next Generation Electronics, ISNE 2017 1 - 2 2017年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, radiation-hardened embedded systems are sought for robots working under high-radiation environments such as the Fukushima Daiichi and Chernobyl nuclear power plants. Recent news reports have described a region with 650 Sv/h radiation outside of containment vessels at the Fukushima Daiichi nuclear power plant. Even in such heavy radiation environments, functioning robots are required. This paper therefore presents radiation-hardened motor controllers used for robots. The radiation tolerances of motor controllers were evaluated using irradiation by a 60Co gamma source.

DOI： 10.1109/ISNE.2017.7968747

300 Mrad total-ionizing-dose tolerance of a holographic memory on an optically reconfigurable gate array 査読

Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

2017 6th International Symposium on Next Generation Electronics, ISNE 2017 1 - 3 2017年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Currently, radiation-hardened field programmable gate arrays (FPGAs) are sought for embedded systems designed for use in space. However, in terms of soft-error and permanent failure, the radiation tolerances of configuration memories on current FPGAS are not high. Therefore, to remove the soft-error on configuration memories of FPGAS, optically reconfigurable gate arrays with a parallel configuration capability have been proposed. The optically reconfigurable gate array consists of an optically reconfigurable gate array VLSI, a holographic memory, and a laser array. Since the optically reconfigurable gate array allows high-speed scrubbing of its configuration memory, the soft-error factor on configuration memory can be removed from consideration. Moreover, the parallel configuration allows uses of radiation-damaged gate arrays so that the optically reconfig-urable gate array can increase the radiation tolerance. However to support such high-speed scrubbing, its optical part must work correctly even if it receives a large amount of radiation. This paper therefore presents a system in which the holographic memory can function correctly despite exposure up to 300 Mrad total-ionizing-dose, which is 300-times-higher radiation tolerance than those of current VLSIs and FPGAS.

DOI： 10.1109/ISNE.2017.7968743

High-speed scrubbing demonstration using an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

OPTICS EXPRESS 25 ( 7 ) 7807 - 7817 2017年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs. (C) 2017 Optical Society of America

DOI： 10.1364/OE.25.007807

FPGAハードウエア・アクセラレーション向け日の丸高位合成ツール招待査読

渡邊実, 佐野健太郎, 高前田伸也, 三好健文, 中條拓伯

電子情報通信学会論文誌 J100-B ( 1 ) 1 - 10 2017年1月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：電子情報通信学会

近年，FPGAは家電製品，自動車，そして宇宙システムと幅広い用途に使用されている．しかし，2000年代前半まで，FPGAはASICと比較して性能が低く，試作，テスト，研究用途に用いられただけで，量産品に対してはコストあたりの性能に秀でたASICが多用されてきた．これが変わるのが2000年代後半であり，FPGAは最先端のプロセスが利用できる数少ない集積回路の一つとなり，高性能な製品を生み出す主役の座に躍り出た．その代表的なものの一つにFPGAを利用したハードウェア・アクセラレータがあり，その有効性については，MicrosoftがBing検索に用いるデータセンターに対してFPGAを用いたサーバーを開発したり，Intel社がXeonプロセッサにFPGAを実装する等，もはや疑う余地がなくなったと言える．そして今日，FPGAベンダーは開発に多大な工数を要したハードウェア記述言語(HDL)の代わりに，C++からFPGAへの回路実装が可能な汎用的な高位合成ツールの提供を開始している．このような皆高位合成ツール時代のFPGA開発において，各企業が他社との優位性を確保するためには，これら万人向けに作られた汎用高位合成ツールやベンダーから提供されるHDL開発環境等を活用するだけでなく，汎用ツールの弱点を補完でき，より高性能な製品をより少ない工数で開発できる特定用途向けのツール群が必要になる．本論文では既に広く有効性が認知された汎用的な高位合成ツールではなく，まだ認知度が低いが日本で独自に開発が進められる「日の丸」ツール群を紹介する．

DOI： 10.14923/transcomj.2016jbi0002

Optically reconfigurable gate array platform for Mono-instruction set computer architecture 査読

Hiroki Shimba, Minoru Watanabe

2017 IEEE 7th Annual Computing and Communication Workshop and Conference 1 - 4 2017年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a highspeed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.

DOI： 10.1109/CCWC.2017.7868473

A 200 Mrad radiation tolerance of a polymer-dispersed liquid crystal holographic memory 査読

Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

PROCEEDINGS OF 2016 IEEE 18TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS; IEEE 14TH INTERNATIONAL CONFERENCE ON SMART CITY; IEEE 2ND INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (HPCC/SMARTCITY/DSS) 1534 - 1535 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Today, although Blu-ray, DVD, CD, hard disk drive, solid state drive, electrically erasable programmable read-only memory (EEPROM) are available, the lifetime of stored data is short. To store large amounts of data longer than 100 years, long-term data storage media are necessary. Moreover, systems designed for use in space require highly radiation-tolerant memory. As long-term data storage media this study demonstrates that a polymer-dispersed liquid crystal holographic memory has a high radiation tolerance by using a cobalt 60 gamma radiation source. Results show that the holographic memory radiation tolerance is more than 667 times higher than EEPROM radiation tolerance.

DOI： 10.1109/HPCC-SmartCity-DSS.2016.29

Compilation time advantage of parallel-operation-oriented optically reconfigurable gate arrays 査読

Takumi Fujimori, Minoru Watanabe

2016 INTERNATIONAL CONFERENCE ON ADVANCED MECHATRONIC SYSTEMS (ICAMECHS) 306 - 311 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, studies have matured of field programmable gate arrays (FPGAs) that realize hardware acceleration. For such hardware acceleration on FPGAs, hugely parallel computation is frequently used. Consequently, numerous identical circuits are implemented onto an FPGA. However, identical configuration contexts of numerous identical circuits are stored on different regions of the configuration memory when a using currently available FPGA, which is exceedingly wasteful. Therefore, we propose a parallel-operation-oriented ORGA with many gate array layers sharing a common configuration context. In programmable devices, the configuration memory and configuration circuit occupy a large implementation area: 70 % - 80 % of the entire VLSI chip area. For that reason, the gate density of the programmable device could be increased if the amount of configuration memory were decreased. Therefore, a parallel-operation-oriented ORGA presents advantages in terms of gate density. Furthermore, the parallel-operation-oriented ORGA architecture presents the important advantage of shorter compilation time. This study clarifies the benefits of the parallel-operation-oriented ORGA in comparison to those of an FPGA having equivalent gate array structure based on the same process technology.

DOI： 10.1109/ICAMechS.2016.7813465

A 300 Mrad total-ionizing dose experiment of lasers used for holographic memories 査読

T. Akabe, M. Watanabe

International Conference On Advances in Computing, Electronics and Electrical Technology 17 - 20 2016年11月

Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays 査読

Bharat Ramanathan, Minoru Watanabe

2016 11TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION (ICCSE) 454 - 457 2016年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An optically reconfigurable gate array (ORGA), an alternative technology to commercially available field programmable gate arrays (FPGAs), is much faster. Moreover, it can operate in radiation-rich environments. An ORGA uses a laser array, a holographic memory, and an ORGA-VLSI chip including a fine-grained programmable gate array. Many configuration contexts can be stored on the holographic memory and can be addressed by the laser array. The ORGA-VLSI can be programmed optically through numerous photodiodes. To realize faster configuration, measuring the variation of photodiode characteristics is extremely important. Nevertheless, photodiode characteristics have not been estimated to date because measurements must be done using its programmable gate array such that the measurement results include a photodiode response time and propagation delay on the programmable gate array. They cannot be classified clearly. Therefore, this paper proposes a photodiode sensitivity measurement method using low light intensity. Results show that the measurement methodology can remove the propagation delay factor and can extract photodiode sensitivity.

DOI： 10.1109/ICCSE.2016.7581623

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