研究者詳細 - 渡邊　実

論文 - 渡邊　実

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井上,小林, 渡邊実

計測自動制御学会論文集 42 ( 10 ) 1175 - 1180 2006年10月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：The Society of Instrument and Control Engineers

Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propose a new PLL using phase interpolation based on a counter with a high-frequency internal clock. The PLL can compare phases more than once a cycle of reference and input, thus reducing jitter and improving responsiveness. Also we optimize implementation of phase interpolation, to improve circuit size and maximum operating frequency, even if the circuit compares phases many time a cycle.

DOI： 10.9746/sicetr1965.42.1175

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A logic synthesis and place and route environment for ORGAs 査読

M. Watanabe, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 237 - 238 2006年7月

高密度ダイナミック光再構成型ゲートアレーVLSI 査読

渡邊実, 小林

電子情報通信学会論文誌 J89-D ( 6 ) 1082 - 1090 2006年6月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：社団法人電子情報通信学会

近年,光による広いバンド幅を利用することで電気配線では実現できない高速な書込みと,光メモリにより大容量のコンテクストが実現可能なプログラマブル・ゲートアレー,光再構成型ゲートアレーの研究が進められている.しかし,これまでの光再構成型ゲートアレーでは,回路情報が静的なメモリ上に記憶されており,このメモリの実装部がゲートアレー部を圧迫し,光再構成型ゲートアレーの高密度化を妨げていた.そこで,回路情報を保持する静的なメモリを全廃し,受光に用いるフォトダイオードの接合容量をメモリとしても使用する新しいダイナミック光再構成型ゲートアレーが提案された.本論文では,まず,0.35μm-3層メタルのプロセスを使用したダイナミック光再構成型ゲートアレー試作チップの評価結果を示す.そして,同じプロセスを使用することで,14.2mm角チップに26,350ゲート規模の光再構成型ゲートアレーが実現可能であることを示すと同時に,この基本デザインを用いて従来の静的メモリ機能をもつ光再構成型ゲートアレーと比較した実装密度の改善率を明らかにする.

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その他リンク： http://hdl.handle.net/10228/4570

Shield effect analysis for a gate array on an Optically Reconfigurable Gate Array 査読

M. Watanabe, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 239 - 240 2006年6月

Differential Reconfiguration Architecture suitable for a Holographic Memory 査読

M. Watanabe, M. Miyano, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 198 - 203 2006年6月

Dynamic optically reconfigurable gate array 査読

M Watanabe, F Kobayashi

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 ( 4B ) 3510 - 3515 2006年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：INST PURE APPLIED PHYSICS

Optically reconfigurable gate arrays (ORGAs) can readily enable both fast reconfiguration and numerous reconfiguration contexts using an optical holographic memory and optical wide-band reconfiguration connections. Such devices present the possibility of large virtual gate-count very large scale integrations (VLSIs). However, the real gate-count of the VLSI part of the devices is too small-only 80. Moreover, the reconfiguration speed is not sufficiently fast: 16 to 20 mu s. For those reasons, this paper clarifies the architecture issues and presents a new architecture of a dynamic optically reconfigurable gate array (DORGA) to improve them. In addition, a comparison is made of results obtained using the previously proposed devices and DORGAs under the same environment. Finally, this paper presents a new design of a 51,272-gate-count DORGA with the new architecture.

DOI： 10.1143/JJAP.45.3510

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A 1,632 gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI 査読

Minoru Watanabe, Fuminori Kobayashi

RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS 3985 268 - 273 2006年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SPRINGER-VERLAG BERLIN

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize a single instruction set computer that requires zero-overhead fast reconfiguration. To date, although the concept and architecture have been proposed and some simulation results of designs have been presented, a ZO-ORGA VLSI chip has never been fabricated. In this paper, the first 1,632 gate-count zero-overhead VLSI chip fabricated using 0.35 um CMOS process technology is presented. The 1,632 ZO-DORGA-VLSI is not only the first prototype VLSI chip; it is also the largest gate-count ORGA. Such a large gate count ORGA had never been fabricated until this study. The performance of ZO-DORGA-VLSI is clarified and discussed using experimental results.

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Hybrid sample rate converter with 110dB SNR and 1/10 less logic gates 査読

Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe

2006 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY 432 - 436 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An SRC, sampling rate converter, consisting of conventional filter-type SRC and time-domain SRC using Fourier interpolation algorithm is proposed. Filter portion realizes over-sampling, and its output is interpolated by the Fourier portion. The SRC achieves noise level of as low as -110dB for all frequencies, and its gate count is about 1000000 FPGA logic cells.

DOI： 10.1109/EIT.2006.252121

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Reconfiguration speed adjustment technique for ORGAs with a holographic memory 査読

Minoru Watanabe, Fuminori Kobayashi

2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS 917 - 922 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array. The gate array of ORGAs is optically reconfigured using diffraction patterns from a holographic memory that is addressed by a laser diode array. In previously proposed ORGAs, the optical reconfiguration speed has been designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory varies depending on the pattern of reconfiguration contexts that is recorded in it. Therefore, this paper proposes a reconfiguration speed adjustment technique for ORGAs to accelerate the reconfiguration speed. In addition, the advantages are discussed from some simulation results of a holographic memory and the experimental results of a fabricated gate array VLSI.

DOI： 10.1109/FPL.2006.311344

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An optically differential reconfigurable gate array with a holographic memory 査読

Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi

20th International Parallel and Distributed Processing Symposium, IPDPS 2006 2006 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Optically Reconfigurable Gate Arrays (ORGAs) offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSIs by exploiting the large storage capacity of holographic memory. We developed an Optically Differential Reconfigurable Gate Array (ODRGA-VLSI) with no overhead and fast reconfiguration capability. This paper presents the results of development of a perfect optical reconfigurable system with the ODRGA-VLSI chip and holographic memory. Experimental results of the reconfiguration procedure and circuit performance on a gate array are also presented. © 2006 IEEE.

DOI： 10.1109/IPDPS.2006.1639478

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Power consumption advantage of a dynamic optically reconfigurable gate array 査読

Minoru Watanabe, Fuminori Kobayashi

20th International Parallel and Distributed Processing Symposium, IPDPS 2006 2006 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Optically reconfigurable gate arrays (ORGAs) are a type of field programmable gate array (FPGA). However, unlike FPGAs, an ORGA can quickly be reconfigured optically using external optical memories and optical connections. Recently, various types of ORGAs have been developed. However, their gate counts were not satisfactory compared with those of FPGAs. Therefore, to improve the gate density of conventional ORGAs, a dynamic ORGA (DORGA) architecture that can remove static memory functions to store a configuration context has been proposed. The DORGA architecture offers not only the advantages of a high gate count, but also the advantage of low reconfiguration power consumption. To date, its power consumption has never been clarified. For that reason, this paper presents measurement results of the optical reconfiguration power consumption of a DORGA-VLSI chip. In addition, the power consumption advantages of the DORGA architecture are clarified through comparison with other ORGAs. © 2006 IEEE.

DOI： 10.1109/IPDPS.2006.1639490

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A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 mu m CMOS technology 査読

Minoru Watanabe, Fuminori Kobayashi

ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 108 - + 2006年

Optically Reconfigurable Gate Arrays vs. ASICs 査読

Minoru Watanabe, Fuminori Kobayashi

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 1164 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Reconfigurable Gate Array (ORGA) is a type of Field Programmable Gate Array (FPGA) that can be reconfigured optically in a very short time and with many reconfiguration contexts by combining a holographic memory and a laser array on a gate-array VLSI. An ORGA can be considered as a type of next-generation three-dimensional (31)) VLSI chip. The developments of high-gate count ORGA-VLSIs, optical reconfiguration systems with a holographic memory, and laser arrays have been advanced recently. However, ORGA performance has never been discussed in comparison with current Application Specific Integrated Circuits (ASICs) or full custom VLSIs. In this paper, the performance difference between ORGAs and ASICs is clarified; the future vision of the ORGA is also discussed.

DOI： 10.1109/APCCAS.2006.342348

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A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays 査読

Minoru Watanabe, Ryuji Fujime, Fuminori Kobayashi

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II 94 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Differential Reconfigurable Gate Array VLSI (ODRGA-VLSI) presents the advantage that it can be reconfigured more rapidly than other optically reconfigurable gate arrays (ORGAs). In an ORGA, reconfiguration contexts are stored in a holographic memory, which is addressed by a laser array, and read as light. The reconfiguration speed is proportional to the light intensity received in each photodiode on an ORGA-VLSI. In addition, the light intensity from a holographic memory is inversely proportional to the number of its lighting bits corresponding to bits of '1' from the diffraction characteristic of a holographic memory. Therefore, the bit-by-bit programmability of ODRGA-VLSI allows more rapid reconfiguration than for other ORGAs because the light power can be focused onto a reprogrammed area instead of a much larger area. However, the reconfiguration circuit to support bit-by-bit reconfiguration occupies a large implementation area of an ODRGA-VLSI chip. Therefore, a new dynamic reconfiguration circuit has been introduced into ODRGA-VLSIs to reduce the implementation area to realize a high gate-count ODRGA-VLSI. In this paper, the VLSI implementation of the dynamic reconfiguration circuit is shown using 0.35 mu m CMOS process technology; a comparison to results from other optical reconfiguration circuits is presented.

DOI： 10.1109/MWSCAS.2006.382216

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Over-sampling PLL for low-jitter and responsive clock synchronization 査読

Manabu Inoue, Furninori Kobayashi, Minoru Watanabe

2006 INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES,VOLS 1-3 809 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Phase Locked Loops (PLLs) are widely used in communication and required to provide low-jitter and fast frequency/phase locking capabilities. For improving these capabilities of PLL, an over-sampling phase detector (PD) using phase interpolation based on a counter with a high-frequency internal clock is proposed. PLL using normal PD compares phases of reference or input signal with its output at the time of their positive transition, but this PLL using over-sampling PD can compare phases more than once a cycle of reference. Thus, the PLL features less jitter than PLL using normal PD, and improved responsiveness. Also we optimized implementation of phase interpolation, to improve maximum operating frequency and circuit size. Experimental results including two jitter characteristics, vital in communication, are shown.

DOI： 10.1109/ISCIT.2006.339842

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A 51,272-gate-count Dynamic Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology 査読

M. Watanabe, F. Kobayashi

International Conference on Solid State Devices and Materials, 336 - 337 2005年9月

Fourier/Filter Hybrid Sampling Rate Converter 査読

M. Inoue, F. Kobayashi, M. Watanabe

SICE Annual Conference 176 - 179 2005年8月

A dynamic optically reconfigurable gate array using dynamic method 査読

M. Watanabe, F. Kobayashi

International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science 50 - 58 2005年2月

An Optically Differential Reconfigurable Gate Array VLSI chip with a dynamic reconfiguration circuit 査読

Minoru Watanabe, Fuminori Kobayashi

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 2005 145 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

An Optically Differential Reconfigurable Gate Array (ODRGA) is a type of Field Programmable Gate Array (FPGA), but its gate array can be reconfigured optically in less than 6 ns. We have fabricated a 68 gate-count ODRGA. However, optical differential reconfiguration circuits, which are capable of optical detection of configuration contexts and which can support reconfiguration of an arbitrary part of its gate array bit-by-bit, occupy up to 47% of the implementation area of ODRGA-VLSI chip and prevent realization of a high gate-count ODRGA. Therefore, a dynamic optical differential reconfiguration circuit was developed to reduce the implementation area of optical reconfiguration circuits. It has been evaluated separately. This paper presents the first 476 gate count ODRGA-VLSI chip with a standard 0.35 μm 3-metal CMOS process technology using an improved dynamic optical differential reconfiguration circuit. In addition, the dynamic reconfiguration frequency and performance of logic blocks are shown using HSPICE simulation results. Finally, this paper presents an estimation of the use of a standard 0.35 μm 3-metal 14.2 × 14.2 mm chip.

DOI： 10.1109/IPDPS.2005.105

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A 16,000-gate-count optically reconfigurable gate array in a standard 0.35 mu m CMOS technology 査読

M Watanabe, F Kobayashi

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 1214 - 1217 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Up to now, we have fabricated 68-gate-count Optically Reconfigurable Gate Arrays (ORGAs), the reconfiguration period of which has been confirmed as less than 10 us. As the next step, we have begun development of high-gate-count ORGAs. The new ORGA-VLSI chip can achieve a 16,000-gate-count through reduction of photodiode size, photodiode spacing, and through introduction of a small optical reconfiguration circuit, that do not exceed the resolution of available optical components. This paper presents the new design of a 16,000-gate-count ORGA using a standard 0.35 mu m 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip and an evaluation of optical reconfiguration circuits using HSPICE simulation.

DOI： 10.1109/ISCAS.2005.1464812

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