研究者詳細 - 渡邊　実

論文 - 渡邊　実

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Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI

Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe

2025 IEEE International Conference on Consumer Electronics (ICCE) 1 - 3 2025年1月

Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA

Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

2025 IEEE International Conference on Consumer Electronics (ICCE) 1 - 4 2025年1月

Fast-Neutron Soft-Error Tolerance of a Radiation-Hardened Repairable Field Programmable Gate Array 査読

Minoru Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shingo Tamaki, Isao Murata, Sachie Kusaka

IEEE International Conference on Consumer Electronics 2025年1月

Evaluation of a Wafer-Scale VLSI Using Programmable Architecture 査読

Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

IEEE International Conference on Consumer Electronics 2025年1月

Radiation-Hardened Triple Modular Redundant Serial Communication System Using Triple Communication Lines 査読

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

IEEE International Conference on Consumer Electronics 2025年1月

Development of a Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Arrays 査読

Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe

IEEE International Conference on Consumer Electronics 2025年1月

Triple Modular Redundancy Logic Design from High-Level Hardware Description 査読

Nobuya Watanabe, Minoru Watanabe

IEEE International Conference on Consumer Electronics 2025年1月

OPTICALLY RECONFIGURED GATE ARRAY VLSI WITH A TRIPLE-MODULAR REDUNDANT OPTICAL CONFIGURATION CIRCUIT 査読

Kiyoto Yonechi, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

REALIZATION OF A HUGE-SCALE RADIATION-HARDENED OPTICALLY RECONFIGURABLE GATE ARRAY VLSI 査読

Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

IMPLEMENTATION OF A MONO INSTRUCTION SET COMPUTER ON A RADIATION-HARDENED OPTICALLY RECONFIGURABLE GATE ARRAY 査読

Soma Imai, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

Formation of holographic memory using laser combiner consisting of three laser sources with different wavelength for optical reconfiguration 査読

Akifumi Ogiwara, Minoru Watanabe

International Symposium on Imaging, Sensing, and Optical Memory 2024 59 - 60 2024年10月

TRIPPLE MODULAR REDUNDANT RISC-V PROCESSOR ON A CYCLONE FPGA 査読

Masato Isobe, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

A 4-BIT COUNTER IMPLEMENTATION ON A REPAIRABLE FPGA 査読

Ryota Hosoya, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

A RING OSCILLATOR IMPLEMENTATION ONTO AN OPTICALLY RECONFIGURABLE GATE ARRAY VLSI 査読

Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

Clock distribution exploiting switching matrices on an optically reconfigurable gate array 査読

Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

Triple modular redundant serial communication circuit used in a severe radiation environment 査読

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024 1 - 4 2024年10月

Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI 査読

Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

IEEE International System-on-Chip Conference 1 - 6 2024年9月

Radiation-hardened programmable two-phase clock generator 査読

Minoru Watanabe

2024 International Electronics Symposium (IES) 140 - 144 2024年8月

Holographic memory optimization method for an Optically reconfigurable gate array

Takumi Fukumoto, Minoru Watanabe, Nobuya Watanabe

E08 - E08 2024年8月

A triple modular redundant RISC-V processor on a Cyclone V FPGA

Masato Isobe, Minoru Watanabe, Nobuya Watanabe

RISC-V Day Tokyo 2024 Summer English 1 - 1 2024年8月

Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI 査読

Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe

2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 239 - 240 2024年7月

Analysis of Clock Tree Buffer Degradation Caused by Radiation 査読

Minoru Watanabe

Lecture Notes in Computer Science 120 - 133 2024年3月

Wafer-scale VLSI realization using programmable architecture 査読

Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

2024 IEEE International Conference on Consumer Electronics (ICCE) 1 - 2 2024年1月

Fast-neutron soft-error tolerance experimentation with a radiation-hardened optically reconfigurable gate array 査読

Minoru Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shigeo Matsuyama, Misako Miwa

2024 IEEE International Conference on Consumer Electronics (ICCE) 1 - 2 2024年1月

Parallel Configuration Experiment for a Radiation-Hardened Optically Reconfigurable Gate Array with a Holographic Polymer-Dispersed Liquid Crystal Memory 査読

Sae Goto, Minoru Watanabe, Akifumi Ogiwara, Nobuya Watanabe

International Conference on Consumer Electronics 2024年1月

Holographic Memory Formed by Different Laser Wavelengths in Laser Combiner System for Optically Reconfigurable Gate Array 査読

Akifumi Ogiwara, Minoru Watanabe

IEEE International Conference on Consumer Electronics 2024年1月

Application Design System for High-Speed Dynamically Reconfigurable Gate Arrays 査読

Nobuya Watanabe, Ryoya Ishitani, Minoru Watanabe

IEEE International Conference on Consumer Electronics 2024年1月

Remote monitoring system for optically reconfigurable gate arrays in radiation environments. 査読

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

IEEE International Conference on Consumer Electronics 1 - 2 2024年

Radiation-hardened stabilized power supply unit based on bipolar transistors 査読

Takato Tanizawa, Minoru Watanabe

International Conference on Microelectronics 2023年12月

Optical multi-context scrubbing operation on a redundant system 査読国際誌

Kakeru Ando, Minoru Watanabe, Nobuya Watanabe

Optics Express 31 ( 23 ) 38529 - 38529 2023年10月

担当区分：責任著者掲載種別：研究論文（学術雑誌）出版者・発行元：Optica Publishing Group

This paper presents a proposal of the world-first optical multi-context scrubbing operation on a redundant system that can maintain the state of a sequential circuit and the operation continuously without any interruption on a radiation-hardened optically reconfigurable gate array even after a permanent failure suddenly happens on the sequential circuit or a flip-flop by radiation. Up to now, a high-speed optical scrubbing operation has been demonstrated on a radiation-hardened optically reconfigurable gate array. In addition, a multi-context scrubbing operation based on the high-speed optical scrubbing operation has already been demonstrated. Although the multi-context scrubbing operation presents the benefit that it can treat both soft-errors and permanent failures caused by radiation simultaneously, the conventional contributions have never presented how to maintain the state of a sequential circuit after a permanent failure occurs on flip-flops. Therefore, in the conventional multi-context scrubbing operation, all the operations must be restarted from the initial condition each time a permanent failure occurs on a programmable gate array. As a result, conventional multi-context scrubbing operations could not be applied for real-time systems. The proposed optical multi-context scrubbing method that can solve the issue has been experimentally evaluated on a radiation-hardened optically reconfigurable gate array.

DOI： 10.1364/oe.500666

An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit 査読

Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe

2023 IEEE 36th International System-on-Chip Conference (SOCC) 2023年9月

Construction of Laser Interferometer Consisting of Different Wavelengths Using Laser Combiner System for Fabrication of Holographic Memory for Optically Reconfigurable Gate Array 査読

Akifumi Ogiwara, Minoru Watanabe

Microoptics Conference (MOC) 2023年9月

Evaluation of low-voltage operations of an optically reconfigurable gate array VLSI

Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Design example of a triple modular redundancy ALU, a register file, and a program counter for a processor

Masato Isobe, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Photodiode current range measurement result of an optically reconfigurable gate array VLSI

Sae Goto, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

An optically reconfigurable gate array driven by an unstabilized power supply unit

Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Total-ionizing-dose tolerance of an optically reconfigurable gate array VLSI

Kaho Yamada, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

A mono instruction set computer architecture on an optically reconfigurable gate array VLSI

Soma Imai, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Realization of a wafer-scale VLSI by using optically reconfigurable gate array architecture

Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Sequential circuit implementation onto optically reconfigurable gate array VLSI using a ring oscillator

Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Remote monitoring system used in a severe radiation environment

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant 2023年8月

Multi-context-scrubbing operation for a 1-bit counter circuit 査読

Kakeru Ando, Minoru Watanabe, Nobuya Watanabe

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS) 1 - 6 2023年6月

Design example of a triple modular redundancy ALU and register-file for RISC-V processors

Masato Isobe, Minoru Watanabe, Nobuya Watanabe

RISC-V Days Tokyo 2023 Summer conference 2023年6月

Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock 査読

Minoru Watanabe

2023 IEEE International Symposium on Circuits and Systems (ISCAS) 1 - 6 2023年5月

Multi-context optically reconfigurable gate array system used for fast-neutron experiments 査読

Sae Goto, Kakeru Ando, Kaho Yamada, Minoru Watanabe, Nobuya Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shingo Tamaki, Isao Murata, Sachie Kusaka

16TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE - ( - ) 1 - 1 2023年4月

Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor 査読

Daisuke Bamba, Minoru Watanabe, Nobuya Watanabe

2023 IEEE International Conference on Consumer Electronics (ICCE) - ( - ) 1 - 2 2023年1月

Optically reconfigurable gate array VLSI that can support a perfect parallel configuration 査読

Sae Goto, Minoru Watanabe, Nobuya Watanabe

18th IEEE Asia Pacific Conference on Circuits and Systems 2022年11月

Cf252 neutron soft error tolerance of an optoelectronic field programmable gate array VLSI 査読

Minoru Watanabe

IEEE International Integrated Reliability Workshop 2022年10月

Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI 査読

Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe

IEEE International Conference on Electronics Circuits and Systems 2022年10月

Total-ionizing-dose tolerance of an optically reconfigurable gate array VLSI

Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe

The sixth International Forum on the Decommissioning of the Fukushima Daiichi Nuclear Power Station 2022年8月

Optically reconfigurable gate array VLSI without any common signal

Sae Goto, Minoru Watanabe, Nobuya Watanabe

The sixth International Forum on the Decommissioning of the Fukushima Daiichi Nuclear Power Station 2022年8月

Radiation-hardened optically reconfigurable gate array 招待

Minoru Watanabe

Global Summit and Expo on Nanotechnology and Nanomaterials (GSENN) 2022年6月

Convolutional neural network implementations using Vitis AI 査読

Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya

IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC) 365 - 371 2022年1月

Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation 査読

Hiroshi Ito, Minoru Watanabe

International Conference on Field-Programmable Technology 2021年12月

Analysis of optical properties and internal structures of γ-ray-irradiated holographic devices formed using liquid crystal composites 査読国際誌

Akifumi Ogiwara, Minoru Watanabe

Optical Materials 123 111932 - 111932 2021年12月

Radiation Hardened Optically Reconfigurable Gate Array 招待査読

Minoru Watanabe

OPTICSMEET2021 2021年11月

Optically reconfigurable gate array with a 1 Grad total-ionizing-dose tolerant holographic memory 査読

Junya Ishido, Minoru Watanabe, Akifumi Ogiwara

IEEE Photonics Conference (IPC) 2021年10月

Holographic gratings formed by wavelength multiplexing in liquid crystal composites 査読

Akifumi Ogiwara, Minoru Watanabe

26th Microoptics Conference (MOC) 2021年9月

Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs 査読

Kurea Murakami, Minoru Watanabe

IEEE International Symposium on Circuits and Systems (ISCAS) 2021年5月

Effects of a radiation dose in gamma-ray irradiation fields on holographic gratings formed by liquid crystal composites 査読国際誌

Akifumi Ogiwara, Makishi Toda, Junya Ishido, Minoru Watanabe, Hiroshi Kakiuchida

OSA Continuum 4 ( 2 ) 514 - 514 2021年2月

Optical Multi-Context Blind Scrubbing for Field Programmable Gate Arrays 査読国際誌

Yusuke Takaki, Minoru Watanabe

IEEE Photonics Journal 12 ( 6 ) 1 - 11 2020年12月

Radiation-hardened configuration-context realization for field programmable gate arrays 査読

H. Shinba, M. Watanabe

Applied Optics 59 ( 19 ) 5680 - 5686 2020年6月

Multi-context holographic memory exploiting a wavelength-dependent optimization technique 招待査読

Junya Ishido, Minoru Watanabe

IEEE International Conference on Photonics 2020年5月

Implementation of RISC-V Processor and MAX-10 FPGA

Md Roman Ahmed, Minoru Watanabe

The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University 2020年3月

Place and route tool for optically reconfigurable gate arrays with fault cells

Yuki Takena, Minoru Watanabe

The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University 2020年3月

Radiation tolerance of a crystal oscillator circuit

Yuichi Moriya, Minoru Watanabe

The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University 2020年3月

Radiation-hardened optically reconfigurable gate array using a multi-wavelength holographic memory 査読

Junya Ishido, Minoru Watanabe

IEEE Workshop on Silicon Errors in Logic – System Effects 2020年2月

Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation 査読

Masaki Watanabe, Minoru Watanabe

IEEE Asia Pacific Conference on Circuits and Systems 2019年11月

Effect of radiation dose of Gamma-Ray irradiation on volume gratings using liquid crystal composites 査読

Makishi Toda, Akifumi, Ogiwara, Minoru Watanabe

Microoptics Conference 238 - 239 2019年11月

Parallel-operation-oriented optically reconfigurable gate array VLSI with four gate array layers 査読

Hirotoshi Ito, Minoru Watanabe

IEEE International Conference on Space Optical Systems and Applications 2019年10月

FPGA implementation of a robot control algorithm 査読

Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano

International Conference on Emerging Technologies and Factory Automation 2019年9月

Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array 査読

Hirotoshi Ito, Minoru Watanabe

IEEE International System-on-Chip Conference 2019年9月

Optically Reconfigurable Gate Array with a triple modular redundancy 査読

Toru Yoshinaga, Minoru Watanabe

International Conference on Space Science and Communication 2019年7月

A 1.15 Grad total-ionizing-dose tolerance parallel-operation-oriented optically reconfigurable gate array VLSI 査読

Takumi Fujimori, Minoru Watanabe

IEEE International Workshop on Metrology for AeroSpace 2019年6月

An optically reconfigurable gate array workable under a strong gamma radiation environment 査読

Shinya Fujisaki, Takumi Fujimori, Minoru Watanabe

IEEE- Workshop on Microelectronics and Electron Devices 2019年4月

1 Grad radiation-hardened optoelectronic embedded system

M. Watanabe

IEEE Workshop on Silicon Errors in Logic – System Effects 2019年3月

FPGAによる自動車の自動走行コンテスト招待

渡邊実

情報・システムソサイエティ誌 24 ( 3 ) 2019年

Soft-error tolerance of an optically reconfigurable gate array VLSI 査読

T. Fujimori, M. Watanabe

INTERNATIONAL CONFERENCE ON SYSTEMS ENGINEERING 1 - 6 2018年12月

Radiation-hardened motor controller

T. Hatamochi, M. Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Many modular redundancy implementation on CPLD

Masaki Watanabe, Minoru Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Full-hardware robot controller

Y. Takaki, M. Watanabe, K. Sano

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Radiation-hardened power supply unit

Shinya Fujisaki, Minoru Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Radiation-hardened optically reconfigurable gate array 査読

M. Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

An optically reconfigurable gate array using four liquid crystal spatial light modulators 査読

Y. Takaki, M. Watanabe

IEEE CPMT Symposium Japan 185 - 188 2018年11月

Triple modular redundancy optically reconfigurable gate array

T. Yoshinaga, M. Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Optically reconfigurable gate array using a colored configuration, 査読

T. Fujimori, M. Watanabe

Applied Optics 57 ( 29 ) 8625 - 8631 2018年10月

Effects of radiation exposure on volume gratings formed in liquid crystal composites 査読

A Ogiwara, M. Toda, M. Watanabe, H. Kakiuchida

2018 KJF International Conference on Organic Materials for Electronics and Photonics 2018年9月

Total-Ionizing-Dose Tolerance of the configuration function of MAX3000A CPLDs 査読

T. Fujimori, M. Watanabe

Data Workshop 2018年9月

Radiation-hardened and stabilized power supply unit based on a lithiumion battery 査読

S. Fujisaki, M. Watanabe

Radiation and its Effects on Components and Systems conference 2018年9月

Ultrasonic sensor system with a 94 Mrad total-ionizing-dose tolerance 査読

S. Fujisaki, M. Watanabe

IEEE International Conference on Semiconductor Electronics 263 - 266 2018年8月

A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory 査読

T. Fujimori, M. Watanabe

NASA/ESA Conference on Adaptive Hardware and Systems 2018年8月

Tolerance of radiation exposure on volume gratings using liquid crystal composites

M.Toda, A.Ogiwara, M.Watanabe

27th International Liquid Crystal Conference (ILCC2018) P4-C2-47 2018年7月

A 603 Mrad total-ionizing-dose tolerance optically reconfigurable gate array VLSI 査読

T. Fujimori, M. Watanabe

International Conference on Signals and Systems 249 - 254 2018年5月

High total-ionizing-dose tolerance field programmable gate array 査読

T. Fujimori, M. Watanabe

IEEE International Symposium on Circuits and Systems 1 - 4 2018年5月

An 807 Mrad total dose tolerance of an optically reconfigurable gate array VLSI

IEEE Workshop on Silicon Errors in Logic – System Effects 2018年4月

FFT implementation using mono-instruction set computer (MISC) architecture 査読

H. Shinba, M. Watanabe

Second Workshop on Pioneering Processor Paradigms 2018年2月

Holographic memory calculation FPGA accelerator for optically reconfigurable gate arrays 査読

Takumi Fujimori, Minoru Watanabe

Proceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017 2018- 620 - 625 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V
Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770
Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770
Intel Corp.).

DOI： 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.109

Resistance evaluation of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation 査読

Akifumi Ogiwara, Minoru Watanabe, Yoshizumi Ito

22nd Microoptics Conference, MOC 2017 2017- 200 - 201 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are investigated for the applications requiring high reliability using an optically reconfigurable gate array. The optical properties and internal grating structures are investigated by using a cobalt 60 gamma radiation source to examine the resistance of 100 Mrad total-ionizing-dose.

DOI： 10.23919/MOC.2017.8244556

Parallel light configuration that increases the radiation tolerance of integrated circuits 査読

Takumi Fujimori, Minoru Watanabe

OPTICS EXPRESS 25 ( 23 ) 28136 - 28145 2017年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Total ionizing dose tolerances of current integrated circuits are limited to 3-10 kGy because semiconductor devices are fundamentally vulnerable to radiation. However, using programmable architecture, the total ionizing dose tolerances of integrated circuits can be increased if the integrated circuits can be repaired each time a permanent failure occurs. Nevertheless, current programmable devices cannot allow such repairable use because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged. To increase the radiation tolerance of integrated circuits, this paper presents a proposal of a new optoelectronic programmable device with a parallel light configuration architecture instead of current field programmable gate arrays which have a serial configuration architecture. This demonstration confirms 1.9 MGy radiation tolerance on an optoelectronic programmable device using a non-radiation-hardened standard complementary metal oxide semiconductor process. (C) 2017 Optical Society of America

DOI： 10.1364/OE.25.028136

Small Area Implementation for Optically Reconfigurable Gate Array VLSI: FFT Case 査読

Ili Shairah Abdul Halim, Fuminori Kobayashi, Minoru Watanabe, Koichiro Mashiko, Ooi Chia Yee

JOURNAL OF SCIENTIFIC & INDUSTRIAL RESEARCH 76 ( 11 ) 697 - 700 2017年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：NATL INST SCIENCE COMMUNICATION-NISCAIR

Optically reconfigurable gate array (ORGA) is a type of multi-context field programmable gate array (FPGA) that has achieved a nanosecond-order reconfiguration capability as well as attaining numerous reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the function of multi-core processor. ORGA system has high dependability in a radiation rich environment and the development is progressing towards better radiation tolerance. In this paper, size minimization of the ORGA-VLSI is the main concern to maintain its high dependability; hence wire complexity needs special consideration during floor planning. A case of Fast Fourier Transform (FFT) is shown to demonstrate the effectiveness of circuit modification by implementing dynamic reconfiguration for area optimization. Results show that, compared with a normal FFT configuration, the minimum wirelength is reduced 5.5% for a 32-point FFT implementation.

FPGA hardware accelerator for holographic memory calculations for optically reconfigurable gate arrays 査読

Yoshizumi Ito, Minora Watanabe

2017 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2017 146 - 149 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Radiation-hardened optically reconfigurable gate arrays have been developed for use in space embedded systems. An optically reconfigurable gate array consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI, which is one type of radiation-hardened SRAM-based field programmable gate array (FPGA). However, optically reconfigurable gate arrays have the important feature of faster scrubbing operations than that of radiation-hardened SRAM-based FPGAs. Therefore, the soft-error-tol er anees of the configuration memories of optically reconfigurable gate arrays become much higher than those of FPGAs. However, the calculation load of a lot of holographic memory patterns on a personal computer is extremely heavy. This paper therefore presents a hardware accelerator using an FPGA. The Vivado-high-level synthesis tool (Xilinx Inc.) has been used for development. Its operation speed was improved drastically from 1,590 ms to 3.12 ms while its power consumption for calculations has been decreased drastically from 55 W to 4.4 W.

DOI： 10.1109/ICSOS.2017.8357225

Optically reconfigurable gate array driven by a lithium-ion battery 査読

S. Fujisaki, M. Watanabe

IEEE CPMT Symposium Japan 227 - 230 2017年11月

Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

International System on Chip Conference 2017- 91 - 95 2017年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as the Fukushima Daiichi nuclear power plant. According to recent news, regions with 650 Sv/h radiation have been found at the Fukushima Daiichi nuclear power plant. Under such extremely high radiation environments, high-speed scrubbing operations must be used to maintain correct circuit information on the configuration memory of programmable gate arrays. Up to now, optical high-speed scrubbing based on an optically reconfigurable gate array has been proposed. This paper presents a demonstration of the radiation tolerance of the optical high-speed scrubbing based on an optically reconfigurable gate array VLSI by using lasers that emulate strong radiation environments. It has been confirmed that 70-ns period high-speed scrubbing operations on the optically reconfigurable gate array are never disturbed by the emulated radiation.

DOI： 10.1109/SOCC.2017.8226014

Asynchronous optical bus for optical VLSIs 査読

Takumi Fujimori, Minoru Watanabe

7th International Conference on Innovative Computing Technology, INTECH 2017 162 - 166 2017年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, optically reconfigurable gate arrays consisting of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI have been under development as high-speed dynamic reconfigurable devices. High-speed dynamic reconfiguration of optically reconfigurable gate arrays can be achieved using a two-dimensional optical bus. If such high-speed reconfiguration were feasible, then its programmable gate array performance could be increased dramatically. This paper presents a demonstration of high-speed asynchronous optical dynamic reconfiguration based on an optically reconfigurable gate array VLSI. The reconfiguration speed of the optically reconfigurable gate array can reach 206.44 Gbit/s.

DOI： 10.1109/INTECH.2017.8102440

Multi-context scrubbing method 査読

Takumi Fujimori, Minora Watanabe

Midwest Symposium on Circuits and Systems 2017- 1548 - 1551 2017年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Two salient concerns of current field programmable gate arrays (FPGAs) used for space applications are how to block soft errors that arise on their configuration memories and how to treat permanent failures attributable to total dose effects. To date, those two main concerns have been treated separately, but we present a proposal for multi-context scrubbing to 'kill two birds with one stone' and resolve both issues simultaneously. To decrease the frequency of soft errors arising on the configuration memories of FPGAs, applying scrubbing operations for configuration memories is extremely useful. Since faster scrubbing can increase the radiation tolerances of the configuration memories on FPGAs, optical high-speed scrubbing using optically reconfigurable gate array (ORGA) architecture is introduced. Up to now, major scrubbing operations have invariably used a single configuration context, but since the storage capacities of holographic memories on ORGAs are high, many configuration contexts can be stored on a holographic memory. Thereby, various configuration contexts that avoid permanent failures can be used cyclically for scrubbing operations. Even if a permanent failure occurs on the programmable gate array during scrubbing operations, which exploit numerous configuration contexts, correct operations can be executed.

DOI： 10.1109/MWSCAS.2017.8053231

Development of a radiation-hardened embedded system used for robots decommissioning nuclear reactors 査読

M. Watanabe

ACTINIDES2017 2017年7月

500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA 査読

Yoshizumi Ito, Minora Watanabe, Akifumi Ogiwara

2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017 167 - 171 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Currently, radiation-hardened static random access memory (SRAM) based field programmable gate arrays (FPGAS) are used frequently for space applications. Invariably, such SRAM-based FPGAS are used along with an electrically erasable programmable read-only memory (EEPROM). Although the radiation tolerance of data stored on EEPROMs is much higher than that stored on SRAMs, the radiation tolerance of the data on an EEPROM is not perfectly safe because electrons on the floating gates of transistors are also disturbed by strong radiation. If high-energy charged particles are incident to the EEPROM, then the EEPROM data might be destroyed by the radiation. In stark contrast, the radiation tolerances of holographic memories are perfect Recording and reading of holographic memory can be executed optically. They never depend on electrons or holes. Moreover, data stored on holographic memory are read by summations of numerous light waves. The operation can be regarded as a majority voting operation. Therefore, even if half of a holographic memory is removed, the remaining half of the holographic memory can generate recorded data correctly. This paper describes a holographic memory based FPGA or an optically reconfigurable gate array (ORGA). Furthermore, this paper explains that a holographic memory can function correctly up to a 500 Mrad total-ionizing-dose, exhibiting 1,667 times higher radiation tolerance than current radiation-hardened VLSIs and FPGAS.

DOI： 10.1109/AHS.2017.8046374

High-speed scrubbing based on asynchronous optical configuration 査読

Takumi Fujimori, Minoru Watanabe

2017 2nd International Conference on Opto-Electronic Information Processing, ICOIP 2017 74 - 78 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as that of the Fukushima Daiichi nuclear power plant. According to recently reported news, an area with 650 Sv/h radiation intensity has been confirmed outside of a containment vessel at the Fukushima Daiichi nuclear power plant. For uses under such extremely high radiation environments, high-speed scrubbing operations must be applied for FPGAs. A high-speed optical scrubbing method that can be used on optically reconfigurable gate arrays has been proposed in recent reports of the literature. Such optically reconfigurable gate arrays using optical high-speed scrubbing can be used in environments with intense radiation. In addition, to increase the optical scrubbing operation speed, this paper demonstrates a high-speed optical scrubbing method with a simpler sequence for use on an optically reconfigurable gate array. The 50 ns period high-speed scrubbing operation could be confirmed on the fabricated optically reconfigurable gate array VLSI.

DOI： 10.1109/OPTIP.2017.8030702

Gate density advantage of parallel-operation-oriented FPGA architecture 査読

Takumi Fujimori, Minora Watanabe

Proceedings of the IEEE National Aerospace Electronics Conference, NAECON 2017 155 - 158 2017年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.

DOI： 10.1109/NAECON.2017.8268761

Tolerance of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation 査読

Akifumi Ogiwara, Minoru Watanabe, Yoshizumi Ito

APPLIED OPTICS 56 ( 16 ) 4854 - 4860 2017年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are discussed in the application for an optically reconfigurable gate array. The radiation experiments are conducted using a cobalt 60 gamma radiation source to examine the tolerance of a 100 Mrad total ionizing dose for the HPDLC memory. The optical properties are compared in the conditions before and after gamma-ray irradiation for the fabricated HPDLC gratings. The effects of gamma-ray irradiation on the internal grating structure are also investigated by polarization optical microscopy and scanning electron microscopy observations. The HPDLC memory irradiated by a 100 Mrad total ionizing dose demonstrates the implementation of the optical reconfiguration in a gate-array VLSI. (C) 2017 Optical Society of America

DOI： 10.1364/AO.56.004854

Error injection analysis for triple modular and penta-modular redundancies 査読

Ryo Terada, Minoru Watanabe

2017 6th International Symposium on Next Generation Electronics, ISNE 2017 1 - 4 2017年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, radiation-hardened embedded systems are demanded for robots that must function in high-radiation environments such as those prevailing at the Fukushima Daiichi and Chernobyl nuclear power plants. Recent news reports have described the discovery of a 650 Sv/h radiation region near the containment vessels of the Fukushima Daiichi nuclear power plant. Even under such a dauntingly intense radiation environment, workable robots are required. This paper therefore present a high-soft-error-tolerant 16-bit adder unit based on penta-modular redundancy (SMR) in addition to triple modular redundancy (TMR). The soft-error tolerances of the TMR and SMR were analyzed theoretically. Such TMR and SMR circuits were implemented onto a field programmable gate array (FPGA). Then error-injection experiments for the TMR and SMR were done on the FPGA. Analytical results have revealed that SMR 16-bit adder circuit is useful for heavy radiation environments.

DOI： 10.1109/ISNE.2017.7968746

Motor controller radiation tolerance experiments 査読

Takumi Hatamochi, Minoru Watanabe

2017 6th International Symposium on Next Generation Electronics, ISNE 2017 1 - 2 2017年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, radiation-hardened embedded systems are sought for robots working under high-radiation environments such as the Fukushima Daiichi and Chernobyl nuclear power plants. Recent news reports have described a region with 650 Sv/h radiation outside of containment vessels at the Fukushima Daiichi nuclear power plant. Even in such heavy radiation environments, functioning robots are required. This paper therefore presents radiation-hardened motor controllers used for robots. The radiation tolerances of motor controllers were evaluated using irradiation by a 60Co gamma source.

DOI： 10.1109/ISNE.2017.7968747

300 Mrad total-ionizing-dose tolerance of a holographic memory on an optically reconfigurable gate array 査読

Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

2017 6th International Symposium on Next Generation Electronics, ISNE 2017 1 - 3 2017年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Currently, radiation-hardened field programmable gate arrays (FPGAs) are sought for embedded systems designed for use in space. However, in terms of soft-error and permanent failure, the radiation tolerances of configuration memories on current FPGAS are not high. Therefore, to remove the soft-error on configuration memories of FPGAS, optically reconfigurable gate arrays with a parallel configuration capability have been proposed. The optically reconfigurable gate array consists of an optically reconfigurable gate array VLSI, a holographic memory, and a laser array. Since the optically reconfigurable gate array allows high-speed scrubbing of its configuration memory, the soft-error factor on configuration memory can be removed from consideration. Moreover, the parallel configuration allows uses of radiation-damaged gate arrays so that the optically reconfig-urable gate array can increase the radiation tolerance. However to support such high-speed scrubbing, its optical part must work correctly even if it receives a large amount of radiation. This paper therefore presents a system in which the holographic memory can function correctly despite exposure up to 300 Mrad total-ionizing-dose, which is 300-times-higher radiation tolerance than those of current VLSIs and FPGAS.

DOI： 10.1109/ISNE.2017.7968743

High-speed scrubbing demonstration using an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

OPTICS EXPRESS 25 ( 7 ) 7807 - 7817 2017年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs. (C) 2017 Optical Society of America

DOI： 10.1364/OE.25.007807

FPGAハードウエア・アクセラレーション向け日の丸高位合成ツール招待査読

渡邊実, 佐野健太郎, 高前田伸也, 三好健文, 中條拓伯

電子情報通信学会論文誌 J100-B ( 1 ) 1 - 10 2017年1月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：電子情報通信学会

近年，FPGAは家電製品，自動車，そして宇宙システムと幅広い用途に使用されている．しかし，2000年代前半まで，FPGAはASICと比較して性能が低く，試作，テスト，研究用途に用いられただけで，量産品に対してはコストあたりの性能に秀でたASICが多用されてきた．これが変わるのが2000年代後半であり，FPGAは最先端のプロセスが利用できる数少ない集積回路の一つとなり，高性能な製品を生み出す主役の座に躍り出た．その代表的なものの一つにFPGAを利用したハードウェア・アクセラレータがあり，その有効性については，MicrosoftがBing検索に用いるデータセンターに対してFPGAを用いたサーバーを開発したり，Intel社がXeonプロセッサにFPGAを実装する等，もはや疑う余地がなくなったと言える．そして今日，FPGAベンダーは開発に多大な工数を要したハードウェア記述言語(HDL)の代わりに，C++からFPGAへの回路実装が可能な汎用的な高位合成ツールの提供を開始している．このような皆高位合成ツール時代のFPGA開発において，各企業が他社との優位性を確保するためには，これら万人向けに作られた汎用高位合成ツールやベンダーから提供されるHDL開発環境等を活用するだけでなく，汎用ツールの弱点を補完でき，より高性能な製品をより少ない工数で開発できる特定用途向けのツール群が必要になる．本論文では既に広く有効性が認知された汎用的な高位合成ツールではなく，まだ認知度が低いが日本で独自に開発が進められる「日の丸」ツール群を紹介する．

DOI： 10.14923/transcomj.2016jbi0002

Optically reconfigurable gate array platform for Mono-instruction set computer architecture 査読

Hiroki Shimba, Minoru Watanabe

2017 IEEE 7th Annual Computing and Communication Workshop and Conference 1 - 4 2017年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a highspeed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.

DOI： 10.1109/CCWC.2017.7868473

A 200 Mrad radiation tolerance of a polymer-dispersed liquid crystal holographic memory 査読

Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

PROCEEDINGS OF 2016 IEEE 18TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS; IEEE 14TH INTERNATIONAL CONFERENCE ON SMART CITY; IEEE 2ND INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (HPCC/SMARTCITY/DSS) 1534 - 1535 2016年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Today, although Blu-ray, DVD, CD, hard disk drive, solid state drive, electrically erasable programmable read-only memory (EEPROM) are available, the lifetime of stored data is short. To store large amounts of data longer than 100 years, long-term data storage media are necessary. Moreover, systems designed for use in space require highly radiation-tolerant memory. As long-term data storage media this study demonstrates that a polymer-dispersed liquid crystal holographic memory has a high radiation tolerance by using a cobalt 60 gamma radiation source. Results show that the holographic memory radiation tolerance is more than 667 times higher than EEPROM radiation tolerance.

DOI： 10.1109/HPCC-SmartCity-DSS.2016.29

Compilation time advantage of parallel-operation-oriented optically reconfigurable gate arrays 査読

Takumi Fujimori, Minoru Watanabe

2016 INTERNATIONAL CONFERENCE ON ADVANCED MECHATRONIC SYSTEMS (ICAMECHS) 306 - 311 2016年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, studies have matured of field programmable gate arrays (FPGAs) that realize hardware acceleration. For such hardware acceleration on FPGAs, hugely parallel computation is frequently used. Consequently, numerous identical circuits are implemented onto an FPGA. However, identical configuration contexts of numerous identical circuits are stored on different regions of the configuration memory when a using currently available FPGA, which is exceedingly wasteful. Therefore, we propose a parallel-operation-oriented ORGA with many gate array layers sharing a common configuration context. In programmable devices, the configuration memory and configuration circuit occupy a large implementation area: 70 % - 80 % of the entire VLSI chip area. For that reason, the gate density of the programmable device could be increased if the amount of configuration memory were decreased. Therefore, a parallel-operation-oriented ORGA presents advantages in terms of gate density. Furthermore, the parallel-operation-oriented ORGA architecture presents the important advantage of shorter compilation time. This study clarifies the benefits of the parallel-operation-oriented ORGA in comparison to those of an FPGA having equivalent gate array structure based on the same process technology.

DOI： 10.1109/ICAMechS.2016.7813465

A 300 Mrad total-ionizing dose experiment of lasers used for holographic memories 査読

T. Akabe, M. Watanabe

International Conference On Advances in Computing, Electronics and Electrical Technology 17 - 20 2016年11月

Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays 査読

Bharat Ramanathan, Minoru Watanabe

2016 11TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION (ICCSE) 454 - 457 2016年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An optically reconfigurable gate array (ORGA), an alternative technology to commercially available field programmable gate arrays (FPGAs), is much faster. Moreover, it can operate in radiation-rich environments. An ORGA uses a laser array, a holographic memory, and an ORGA-VLSI chip including a fine-grained programmable gate array. Many configuration contexts can be stored on the holographic memory and can be addressed by the laser array. The ORGA-VLSI can be programmed optically through numerous photodiodes. To realize faster configuration, measuring the variation of photodiode characteristics is extremely important. Nevertheless, photodiode characteristics have not been estimated to date because measurements must be done using its programmable gate array such that the measurement results include a photodiode response time and propagation delay on the programmable gate array. They cannot be classified clearly. Therefore, this paper proposes a photodiode sensitivity measurement method using low light intensity. Results show that the measurement methodology can remove the propagation delay factor and can extract photodiode sensitivity.

DOI： 10.1109/ICCSE.2016.7581623

Effects of multi-context information recorded at different regions in holographic polymer-dispersed liquid crystal on optical reconfiguration 査読

Akifumi Ogiwara, Minoru Watanabe

JAPANESE JOURNAL OF APPLIED PHYSICS 55 ( 8 ) 08RG04-1 - 08RG04-6 2016年8月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IOP PUBLISHING LTD

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by constructing a laser illumination system to implement successive laser exposures at different small regions in a glass cell filled with LC composites. The context pattern arrangements for circuit information are designed in a 3 x 3 in. 2 photomask by electron beam lithography, and they are recorded as laser interference patterns at nine regions separated in an HPDLC sample by a laser interferometer composed of movable pinhole and photomask plates placed on motorized stages. The multi-context information reconstructed from the different regions in the HPDLC is written to a photodiode array in a gate-array VLSI by switching only the position of laser irradiation using the displacement of the pinhole plate under the control of a personal computer ( PC). The effects of multi-context information recorded at different regions in the HPDLC on optical reconfiguration are discussed in terms of the optical system composed of ORGA VLSI and HPDLC memory. The internal structures in the HPDLC memory formed by multi-context recording are investigated by scanning electron microscopy ( SEM) observation, and the configurations composed of LC and polymer phases are revealed at various regions in the HPDLC memory. (C) 2016 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.55.08RG04

Direct optical communication on an optically reconfigurable gate array 査読

Shinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi

2016 FIFTH INTERNATIONAL CONFERENCE ON FUTURE COMMUNICATION TECHNOLOGIES (FGCT) 17 - 20 2016年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

As one type of field programmable gate array (FPGA), optically reconfigurable gate arrays (ORGAs) have been undergoing continual development. ORGAs are optoelectronic devices consisting of a holographic memory, a laser array, a programmable gate array. Since the storage capacity of such holographic memory is greater than that of two-dimensional semiconductor memory, an ORGA can accommodate more huge gates and provide higher performance than FPGAs. A programmable gate array of an ORGA has numerous photodiodes that can be reconfigured optically using configuration contexts on a holographic memory. Although the photodiodes are normally used only for a configuration procedure, the photodiodes are useful for direct input of optical communication signals. This paper therefore presents a demonstration of optical communication on ORGA's programmable gate array.

DOI： 10.1109/FGCT.2016.7605065

Demonstrating a Holographic Memory Having 100 Mrad Total-Ionizing-Dose Tolerance 査読

Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

PROCEEDINGS OF 2016 7TH INTERNATIONAL CONFERENCE ON MECHANICAL AND AEROSPACE ENGINEERING, (ICMAE) 377 - 380 2016年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, space systems require highly radiation tolerant memory. If memory with high radiation tolerance were available, then shielding of embedded systems for use in space could be reduced or removed, thereby greatly decreasing the weight of such space embedded systems. This study examines the radiation-hardened characteristics of a holographic memory. Using a cobalt 60 gamma radiation source, radiation experiments were conducted for a photopolymer holographic memory. Results show that the holographic memory can function correctly at a 100 Mrad total-ionizing dose. The radiation tolerance of the holographic memory is over 300 times higher than that of an electrically erasable programmable read-only memory (EEPROM). Moreover, this paper shows a demonstration applied for an optically reconfigurable gate array. The configuration procedure could be executed by using the radiation-damaged holographic memory.

DOI： 10.1109/ICMAE.2016.7549569

Radiation tolerance of a MEMS mirror device 査読

Takumi Fujimori, Minoru Watanabe

2016 INTERNATIONAL CONFERENCE ON OPTICAL MEMS AND NANOPHOTONICS (OMN) 1 - 2 2016年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents experimentally obtained results demonstrating the radiation tolerance of a MEMS mirror device. The radiation tolerance was confirmed as 170 Mrad or higher total-ionizing dose tolerance.

DOI： 10.1109/OMN.2016.7565925

Architecture-Independent Negative Logic Implementation for Optically Reconfigurable Gate Arrays 査読

Takumi Fujimori, Minoru Watanabe

PROCEEDINGS OF 2016 7TH INTERNATIONAL CONFERENCE ON MECHANICAL AND AEROSPACE ENGINEERING, (ICMAE) 381 - 385 2016年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) comprise a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. According to holographic memory properties, the reconfiguration speed and radiation tolerance of ORGAs depend on the number of bright bits included in a configuration context. This paper therefore proposes a method of reducing the number of bright bits included in a configuration context using negative logic implementation. Since the method is architecture-independent, the method offers the important benefit that it is never necessary to modify the architecture of optically reconfigurable gate array VLSIs. This paper describes experimental demonstrations of the reconfiguration speed and radiation-tolerance advantages of the method.

DOI： 10.1109/ICMAE.2016.7549570

A 180 Mrad Total-Ionizing Dose Experiment for Laser Arrays on Optically Reconfigurable Gate Arrays 査読

K. Akagi, M. Watanabe

25th Annual Single Event Effects (SEE) Symposium 2016年5月

Quality Recovery Method of Interference Patterns Generated From Faulty MEMS Spatial Light Modulators 査読

Minoru Watanabe

JOURNAL OF LIGHTWAVE TECHNOLOGY 34 ( 3 ) 910 - 917 2016年2月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Currently, microelectromechanical system (MEMS) spatial light modulators (SLMs) with numerous tiny mirrors that are controllable as a binary state are available. Such MEMS spatial light modulators are useful as holographic displays, optical tweezers, optical memories, reconfigurable lenses, etc. Although nonfault devices are always used for such applications, this paper clarifies that even if a part of a MEMS-SLM is faulty, the MEMS-SLM is useful for almost all commercial products related to the applications described above. Moreover, it is useful even as research equipment with a high degree of precision. This paper therefore presents the fault-tolerance analysis results of light intensity, contrast ratio, and spot size of interference pattern generated from a MEMS-SLM to clarify the allowable deteriorations of faulty MEMS-SLMs. Moreover, we propose a recovery method that a faulty MEMS-SLM can be used as a nonfaulty MEMS-SLM by exploiting excess laser power.

DOI： 10.1109/JLT.2015.2483622

Full FPGA Game Machine 査読

Takumi Fujimori, Minoru Watanabe

2016 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE) 431 - 432 2016年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, many consumer game machines are based on the operations of processors. However, in the field programmable gate array (FPGA) research field, various FPGA game solvers have been developed recently. The processing speeds of such FPGA game solvers can reach about 1000 times faster than processor-based operations. This paper explains the development of one such FPGA game solvers, the Blokus Duo FPGA solver, and presents discussion of how processors on game machines can be replaced with FPGAs in future consumer game machines.

DOI： 10.1109/ICCE.2016.7430678

Reconfiguration performance recovery on optically reconfigurable gate arrays 査読

Tomoya Akabe, Minoru Watanabe

2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID) 603 - 604 2016年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, radiation-hardened optoelectronic field programmable gate arrays (FPGAs) or optically reconfigurable gate arrays (ORGAs) have been under development. We propose a method of reconfiguration performance recovery for maintaining the gate array performance of ORGAs. We have experimentally demonstrated the recovery of the ORGA configuration speed merely by exploiting excess laser power.

DOI： 10.1109/VLSID.2016.67

Angle-multiplexing recording of circuit information in volume hologram using liquid crystal composites

Akifumi Ogiwara, Yuta Maeda, Minoru Watanabe

Optics InfoBase Conference Papers 2016年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：OSA - The Optical Society

Formation of holographic memory using liquid crystal composites is reported for optically reconfigurable gate arrays. The different circuit information is recorded at four angles by switching the reference beam under the control of motorized stages.

DOI： 10.1364/iprsn.2016.jtu4a.38

Sustainable advantage of a parallel configuration in an optical FPGA 査読

Minoru Watanabe

2015 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION (SII) 807 - 810 2015年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, static random access memory (SRAM)based field programmable gate arrays (FPGAs) are used for various systems. Since such SRAM-based FPGAs are programmable, their use over a long period must accommodate the use of a partly damaged programmable gate array. However, since current FPGAs use a serial configuration line for their configuration and the serial configuration circuit is invariably first broken circuit. Therefore, currently available FPGAs cannot accommodate the use of a partly damaged programmable gate array. However, if a partly damaged programmable gate array could be used, then the lifetime of VLSIs would be increased drastically. To extend the lifetime of programmable devices, FPGA should use a parallel configuration architecture instead of the serial configuration architecture of currently available FPGAs. This paper therefore clarifies the benefits of the parallel configuration architecture on an optically reconfigurable gate array (ORGA) VLSI using the designs of an ORGA-VLSI and a currently available serial-configuration FPGA.

DOI： 10.1109/SII.2015.7405083

Triple modular redundancy on parallel-operation-oriented optically reconfigurable gate arrays 査読

Yoshizumi Ito, Minoru Watanabe

2015 IEEE INTERNATIONAL CONFERENCE ON AEROSPACE ELECTRONICS AND REMOTE SENSING TECHNOLOGY (ICARES) 2015年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, to realize autonomous functions resembling those of humans on space systems, higher-performance embedded systems than those of current space systems are necessary for use in long-distance space missions. Currently, a parallel-operation-oriented optically reconfigurable gate array (ORGA) has been under development. The ORGA can support a nanosecond-order high-speed reconfiguration and high-density implementation of parallel operations. The parallel-operation-oriented ORGA has many programmable gate array layers, which share a common configuration context and increase the number of implementable parallel operations. Therefore, a parallel-operation-oriented ORGA is suitable for hardware acceleration of a software operation on a processor. However, in a space environment, triple modular redundancy (TMR) must be used. Single common configuration memory becomes a weak point for radiation in terms of redundancy. Therefore, we propose a TMR implementation method that is suitable for the parallel-operation-oriented ORGA.

DOI： 10.1109/ICARES.2015.7429829

Total-ionizing-dose tolerance analysis of an optically reconfigurable gate array VLSI

Minoru Watanabe

2015 IEEE International Conference on Aerospace Electronics and Remote Sensing Technology (ICARES) 2015年12月

FPGA Trax Solver based on a Neural Network Design 査読

Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe

2015 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (FPT) 260 - 263 2015年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

For research related to field programmable gate arrays (FPGAs), various FPGA game solvers have been developed recently. The FPGA game solver can achieve up to 1,000 times faster processing speeds than processor-based operations. This paper presents one development of such FPGA game solvers: an FPGA Trax Solver based on a neural network design. The speed of the FPGA Trax Solver operations implemented on an FPGA (Arria II GX; Altera Corp.) is over 60 times greater than operation of C++ based software on a personal computer (Vostro 460; Dell Inc.).

DOI： 10.1109/FPT.2015.7393119

Formation of holographic polymer dispersed liquid crystal memory by angle-multiplexing recording for optically reconfigurable gate arrays 査読

Akifumi Ogiwara, Minoru Watanabe

APPLIED OPTICS 54 ( 36 ) 10623 - 10629 2015年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array is discussed for angle-multiplexing recording by controlling the laser interference exposure in LC composites. The successive laser illumination system to record the various configuration contexts at the specified region and angle in HPDLC memory is constructed by using the combination of a half-mirror and a photomask placed on the motorized stages under the control of a personal computer. The effect of laser exposure energy on the formation of holographic memory is investigated by measuring diffraction intensity as a function of exposure energy during the grating formation process and observing the internal grating structure by scanning electron microscopy. The optical reconfiguration in the gate-array VLSI is executed for configuration contexts of OR and NOR operations shown as logical operators that are reconstructed by laser irradiation at different incident angles for a specified region in the HPDLC memory. (C) 2015 Optical Society of America

DOI： 10.1364/AO.54.010623

Triple modular redundancy on parallel-operation-oriented FPGA architectures for optical communications 査読

Minoru Watanabe

2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015 1 - 4 2015年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, high-speed space optical communication requires real-time hardware operation instead of slow software operation on a processor. For such purposes, field programmable gate arrays (FPGAS) are extremely useful. In such hardware accelerations, a software algorithm is frequently implemented onto an FPGA as a parallel operation. However, in such implementations, many regions of the configuration memory on an FPGA must have common circuit information, but the overlap on the configuration memory can be regarded as wasteful implementation. Therefore, a parallel-operation-oriented FPGA has been proposed to implement parallel operations onto an FPGA efficiently. Such a parallel-operation-oriented FPGA has numerous programmable gate array layers sharing a common configuration context so that the overlap data on the configuration memory of an FPGA can be removed perfectly. However, in space environments, triple modular redundancy must always be used to remove soft errors and the single shared configuration architecture of the parallel-operation-oriented FPGA is the opposite way of such redundancy. To meet those demands, we propose a suitable implementation method of triple modular redundancy (TMR) onto the parallel-operation-oriented FPGA architecture.

DOI： 10.1109/ICSOS.2015.7425070

100 mrad total-ionizing dose tolerance experiment of a laser array 査読

Kouta Akagi, Minoru Watanabe

2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015 1 - 3 2015年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, lasers are being used for space optical communications. However, in a space environment, space radiation is constantly incident to lasers. Therefore, the radiation tolerance analysis of lasers is an important characteristic that must be evaluated. As described in this report, we present radiation experiment results of a semiconductor laser array. This experiment measured the radiation tolerance of the laser array using a Cobalt 60 gamma radiation source. Results show that the laser array stands up to at least 100 Mrad total ionizing dose.

DOI： 10.1109/ICSOS.2015.7425076

Fresnel lens radiation shield for photodiodes 査読

Minoru Watanabe

2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015 1 - 2 2015年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, since space satellites use image sensors and photodiode sensors, their radiation tolerance has become an important concern. In addition, some available space communication systems use a photodiode sensor for communications. However, since such sensors have an aperture without shielding, the total ionizing dose tolerance of the sensors becomes so weak that the radiation tolerance becomes lower than that of other embedded components. This paper therefore presents a proposal of a Fresnel lens radiation shield for use with photodiodes. A Fresnel lens can increase the light sensitivity and radiation tolerance of a photodiode.

DOI： 10.1109/ICSOS.2015.7425088

Effect of Laser Exposure Condition on Formation of Holographic Memory by Angle-multiplexing Recording using Liquid Crystal composites 査読

Akifumi Ogiwara, Minoru Watanabe

2015 20TH MICROOPTICS CONFERENCE (MOC) 1 - 2 2015年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

The effect of laser exposure condition on the formation of holographic polymer-dispersed liquid crystal (HPDLC) memory by the angle-multiplexing recording is discussed. The successive laser illumination system to record the various configuration contexts at the different region and angle in HPDLC memory is constructed by controlling the laser interference exposure in liquid crystal (LC) composites and the optical equipment using the motorized stages.

DOI： 10.1109/MOC.2015.7416433

Investigating the radiation tolerance of a laser array for an optically reconfigurable gate array 査読

Kouta Akagi, Minoru Watanabe

2015 20TH MICROOPTICS CONFERENCE (MOC) 1 - 2 2015年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize radiation-hardened field programmable gate arrays (FPGAs). An ORGA consists of a laser array, a holographic memory, and a programmable gate array VLSI. Since the configuration of an ORGA is a parallel configuration, damage to a configuration circuit or a component does not affect configuration procedures on other configuration circuits. Therefore, even if almost all look-up tables (LUTs) malfunction because of radiation, the remaining functional LUTs can be programmed and used, whereas the serial configuration of FPGAs does not allow the use of a partly failed gate array. However, to achieve higher radiation tolerance of a programmable gate array than that of an FPGA in ORGA architecture, the radiation tolerances of a laser array and a holographic memory must be sufficiently higher than that of the part of a programmable gate array VLSI. Since the radiation tolerance of a holographic memory has already been confirmed as sufficiently higher than that of a programmable gate array VLSI, this paper presents a radiation tolerance investigation of a laser array on an optically reconfigurable gate array. Experiments using Co60 gamma radiation have demonstrated that a laser array has a greater than 20 Mrad total ionizing dose tolerance.

DOI： 10.1109/MOC.2015.7416484

Total ionizing dose tolerance of the serial configuration on cyclone II FPGA 査読

Hiroyuki Ito, Minoru Watanabe

2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015 1 - 4 2015年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, existing radiation-hardened static random access memory (SRAM)-based field programmable gate arrays (FPGAS) are anticipated for use in space radiation environments. Although such radiation-hardened SRAM-based FPGAS are programmable, the use of a radiation-damaged gate array has never been assessed for use with application-specific integrated circuits (ASICs) because its serial configuration is invariably damaged first by radiation so that the configuration itself becomes impossible. Therefore, currently available FPGA cannot be used in such faulty gate arrays used in space environments. However, if faulty programmable gate arrays are used, then the total ionizing dose tolerance of the programmable gate array would be increased even if its process technology were the same as that of conventional FPGAS. In this paper, in order to explore the possibility, we experimentally assessed the configuration circuit robust capabilities of a normal Cyclone II FPGA. Also, we examined the failure probability when using 1-bit, 2-bit, 4-bit, and 8-bit buses for the FPGA configuration using the designs of serially configured FPGAS.

DOI： 10.1109/ICSOS.2015.7425067

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics 査読

Daisaku Seto, Minoru Watanabe

JAPANESE JOURNAL OF APPLIED PHYSICS 54 ( 9 ) 09MA06-1 - 09MA06-5 2015年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IOP PUBLISHING LTD

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 x 10(4) times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and highspeed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.09MA06

Formation of holographic memory by angle-multiplexing recording in liquid crystal composites 査読

Akifumi Ogiwara, Minoru Watanabe

2015 11th Conference on Lasers and Electro-Optics Pacific Rim, CLEO-PR 2015 3 1 - 2 2015年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array based on the angle-multiplexing recording is discussed by controlling the laser interference exposure in liquid crystal (LC) composites. The successive laser illumination system to record the various configuration contexts at the different region and angle in HPDLC memory is constructed by using the half mirror and photomask placed on the motorized stages under the control of a personal computer (PC). The effect of laser exposure energy on the formation of holographic memory is investigated by the measurement of diffraction intensity during the grating formation process. The reconstruction of configuration contexts for the various logical circuits is demonstrated by the laser illumination at different incident angle in the HPDLC memory.

DOI： 10.1109/CLEOPR.2015.7376567

Holographic scrubbing technique for a programmable gate array 査読

Minoru Watanabe, Takumi Fujimori

2015 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS) 1 - 5 2015年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, field programmable gate arrays (FPGAs), which have become widely used for embedded systems, have also become anticipated for use in high-radiation environments such as space environments and nuclear power plants. Currently available radiation-hardened FPGAs can support scrubbing techniques, but such techniques entail the difficulty that radiation tolerance is insufficient for high-radiation environments. This paper therefore presents a holographic scrubbing technique for a programmable gate array. The scrubbing period can be less than 10 ns, so the robust ability of programmable gate arrays can be increased drastically. This paper presents theoretical analysis results and a demonstration of high-speed scrubbing on an optically reconfigurable gate array.

DOI： 10.1109/AHS.2015.7231161

Radiation-hardened Optically Reconfigurable Gate Array Using a Negative Logic Configuration without a Dedicated VLSI 査読

T. Fujimori, M. Watanabe

24th Annual Single Event Effects (SEE) Symposium 2015年5月

High-resolution configuration of optically reconfigurable gate arrays 査読

Kouta Akagi, Minoru Watanabe

2015 International Symposium on Next-Generation Electronics (ISNE) 1 - 4 2015年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs) have been developed to offer numerous reconfiguration contexts with high-speed dynamic reconfiguration. Such ORGAs consist of a holographic memory, a laser array, and optically reconfigurable gate array VLSI. The storage capacity of a three-dimensional holographic memory is much higher than that of current two-dimensional memory technologies. Therefore, even Tera-gate-count circuit information can be stored on such a holographic memory. Moreover, high-speed reconfiguration can be realized by exploiting two-dimensional free optical connections between a holographic memory and a photodiode array on an optically reconfigurable gate array VLSI. Such high-speed dynamic reconfiguration can increase the gate array performance. Currently, we are trying to develop a high-density optically reconfigurable gate array VLSI. An important bottleneck is the limitation of light diffraction. This report presents a method of increasing the resolution of diffraction light for realizing a high-density optically reconfigurable gate array

DOI： 10.1109/ISNE.2015.7131967

Design of a parallel-operation-oriented FPGA 査読

Minoru Watanabe

2015 International Symposium on Next-Generation Electronics (ISNE) 1 - 4 2015年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, studies of acceleration of software operations on a processor have been executed aggressively using Field Programmable Gate Arrays (FPGAs). However, currently available FPGA architecture presents waste under a parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous parts of configuration memory. This paper therefore presents a proposal for a parallel-operation-oriented FPGA architecture including a shared common configuration memory. In this research, a parallel-operation-oriented FPGA with four programmable gate arrays sharing a common configuration memory has been designed using a 0.18 mu m CMOS process technology. The advantage of the parallel-operation-oriented FPGA is clarified and a design technique to achieve a high-performance parallel-operation-oriented FPGA is discussed.

DOI： 10.1109/ISNE.2015.7132021

Radiation tolerance experiment for a dynamically reconfigurable vision architecture, 査読

M. Watanabe, S. Kawahito

International Journal of Image Processing Techniques 2 ( 1 ) 59 - 62 2015年4月

Total ionizing dose effects of optical components on an optically reconfigurable gate array 査読

Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 9040 393 - 400 2015年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Springer Verlag

Recently, optically reconfigurable gate arrays (ORGAs) have been developed as radiation-hardened field programmable gate arrays (FPGAs) to realize a 10 Mrad total ionizing dose-tolerance. Specifically, ORGAs offer important benefits of high-speed reconfiguration, numerous reconfiguration contexts, and robust configuration. These three factors are important to remove the soft-error of a configuration circuit on a programmable gate array and to increase the total ionizing dose tolerance. Although the robust configuration capability has been confirmed using radiation emulation, no actual radiation experiment has been reported to date in the relevant literature. This paper therefore presents experiments demonstrating the enhanced radiation tolerance of an optically reconfigurable gate array using a cobalt-60 gamma radiation source.

DOI： 10.1007/978-3-319-16214-0_35

Parallel-Operation-Oriented Optically Reconfigurable Gate Array 査読

Takumi Fujimori, Minoru Watanabe

ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2015 9017 3 - 14 2015年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Recently, studies exploring acceleration of software operations on a processor have been undertaken aggressively using field programmable gate arrays (FPGAs). However, currently available FPGA architectures present waste occurring with parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous configuration memory parts. Therefore, a parallel-operation-oriented FPGA with a single shared configuration memory for some programmable gate arrays has been proposed. Here, the architecture is applied for optically reconfigurable gate arrays (ORGA). To date, the ORGA architecture has demonstrated that a high-speed dynamic reconfiguration capability can increase the performance of its programmable gate array drastically. Software operations can be accelerated using an ORGA. This paper therefore presents a proposal for combinational architecture of the parallel-operation oriented FPGA architecture and a high-speed reconfiguration ORGA. The architecture is called a parallel-operation-oriented ORGA architecture. For this study, a parallel-operation-oriented ORGA with four programmable gate arrays sharing a common configuration photodiode-array has been designed using 0.18 mu m CMOS process technology. This study clarified the benefits of the parallel-operation-oriented ORGA in comparison with an FPGA having the same gate array structure, produced using the same process technology.

DOI： 10.1007/978-3-319-16086-3_1

Radiation tolerance of optically reconfigurable gate arrays

R. Moriwaki, H. Ito, M. Watanabe, A. Ogiwara, H. Maekawa

International Symposium Toward the Future of Advanced Researches in Shizuoka University 2015年1月

Optically Reconfigurable Gate Array Prototype System

M. Seo, M. Watanabe

The 1st RIS-MJIIT Workshop on Renewable and Sustainable Integrated Systems 2015年

Radiation tolerance experiment for a dynamically reconfigurable vision architecture 査読

M. Watanabe, S. Kawahito

International Conference on Advances in Computing, Electronics and Electrical Technology 1 - 4 2014年12月

Dependable Optically Reconfigurable Gate Array Architecture

Minoru Watanabe

International Symposium on Optical Memory 210 - 211 2014年10月

Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture 査読

Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1528 - 1531 2014年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, several varieties of image recognition systems using Fourier transform have been proposed. The salient benefit of using a Fourier transform is its position-independent image recognition capability. However, the operation of Fourier transform of high-resolution images is an extremely heavy operation. This paper therefore presents a proposal of image recognition systems using an optical Fourier transform on a dynamically reconfigurable vision architecture. This proposed system can recognize numerous images within an extremely short period using dynamic reconfiguration.

DOI： 10.1109/ISCAS.2014.6865438

A parallel-operation-oriented FPGA architecture 査読

M. Watanabe

International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 123 - 126 2014年6月

Dependable optically differential reconfigurable gate array 査読

M. Seo, M. Watanabe

International Conference on Space Optical Systems and Applications, CD-ROM (6 pages) 2014年5月

Optically Reconfigurable Gate Array with an Angle-Multiplexed Holographic Memory 査読

Retsu Moriwaki, Hikaru Maekawa, Akifumi Ogiwara, Minoru Watanabe

GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI 341 - 346 2014年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ASSOC COMPUTING MACHINERY

Optically reconfigurable gate arrays (ORGAs) have been developed to achieve a high-performance FPGA with numerous configuration contexts. In the architecture, an optical memory technology or a holographic memory technology has been introduced so that the architecture can have numerous configuration contexts and high-speed reconfiguration capability. Results show that the architecture can achieve a large virtual gate count that is much larger than those of currently available VLSIs. To date, ORGAs with a spatially multiplex holographic memory have been reported. However, the spatially multiplexed holographic memory can only have a small number of configuration contexts, which are limited to about 256 configuration contexts. To implement more than a million configuration contexts, an angle-multiplex holographic memory must be used. However, no ORGA with an angle multiplex holographic memory that can sufficiently exploit the huge storage capacity of a holographic memory has ever been reported. Therefore, this paper presents a proposal of a novel ORGA with an angle-multiplexed holographic memory. The architecture can open the possibility of providing a million configuration contexts for a multi-context FPGA.

DOI： 10.1145/2591513.2591597

Radiation tolerance of color configuration on an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

PROCEEDINGS OF 2014 IEEE INTERNATIONAL PARALLEL & DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW) 205 - 210 2014年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, research of optically reconfigurable gate arrays (ORGAs), a type of multi-context field programmable gate arrays (FPGAs), has progressed rapidly. ORGAs offer important benefits of high-speed reconfiguration, numerous reconfiguration contexts, and robust configuration. Such ORGAs always consist of a single-wavelength laser array to address configuration contexts. However, for this architecture, concerns related to its package size often arise. The laser array is large because of the large space between lasers. For that reason, the ORGA also tends to be large. Therefore, we have introduced some wavelength lasers inside a laser array of an ORGA to decrease the laser array size. Results show that the ORGA package can be smaller. However, the dependability of color configuration has never been discussed up to now. This paper therefore presents a demonstration of the radiation tolerance of color configuration on an optically reconfigurable gate array.

DOI： 10.1109/IPDPSW.2014.27

Enhanced radiation tolerance of an optically reconfigurable gate array by exploiting an inversion/non-inversion implementation 査読

Takashi Yoza, Minoru Watanabe

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 8405 156 - 166 2014年4月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Springer Verlag

To date, optically reconfigurable gate arrays (ORGAs) have been developed to realize highly dependable embedded systems. ORGAs present many beneficial capabilities beyond those of field programmable gate arrays (FPGAs): The most important is that an ORGA can be reconfigured using an error-included configuration context that has been damaged by high-energy charged particles. The radiation tolerance of an ORGA is extremely high. Moreover, if an inversion/ non-inversion implementation architecture is introduced to an ORGA, the configuration dependability of the ORGA for radiation can be increased drastically. This paper therefore presents a demonstration of the enhanced radiation tolerance of an optically reconfigurable gate array achieved by exploiting the inversion/ non-inversion implementation. © 2014 Springer International Publishing Switzerland.

DOI： 10.1007/978-3-319-05960-0_14

A high-density optically reconfigurable gate array VLSI using variable holographic memory patterns 査読

K. Akagi, M. Watanabe

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems 2014年3月

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

Emerging Liquid Crystal Technologies IX 9004 90040M-1 2014年2月

Mono-instruction set computer architecture on a 3D optically reconfigurable gate array 査読

Hiroyuki Ito, Minoru Watanabe

2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) 173 - 176 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecondorder. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.

DOI： 10.1109/EDAPS.2013.6724417

Many-module redundancy implementation of mono instruction set computers for 3D optical FPGAs 査読

Yuya Shirahashi, Minoru Watanabe

2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) 169 - 172 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for programmable devices for space applications is increasing day-by-day to support hardware repair functions, hardware update functions, and hardware acceleration for space systems. An optically reconfigurable gate array (ORGA) has been developed as a robust multi-context field programmable gate array that is quite suitable for such space applications. The ORGA can be reconfigured using corrupt configuration data with nanosecond-order reconfiguration speed. Currently, we also propose a mono-instruction set computer architecture exploiting the high-speed dynamic reconfiguration. Using the mono-instruction set computer architecture, many-module redundancy over triple module redundancy (TMR) can be realized. This paper presents one demonstration result of a mono-instruction set computer and its robust capabilities.

DOI： 10.1109/EDAPS.2013.6724416

Color configuration method for an optically reconfigurable gate array 査読

Takumi Fujimori, Minoru Watanabe

PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT) 406 - 409 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a proposal of a color configuration method for an optically reconfigurable gate array (ORGA). A conventional ORGA consists of a single-wavelength laser array to address configuration contexts. However, the new ORGA has lasers of some other wavelength inside a laser array. Consequently, the addressable number of configuration contexts can be increased.

DOI： 10.1109/FPT.2013.6718400

FPGA Blokus Duo Solver using a massively parallel architecture 査読

Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe

PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT) 494 - 497 2013年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

DOI： 10.1109/FPT.2013.6718426

A dynamic optically reconfigurable gate array using a blue laser 査読

Takayuki Kubota, Minoru Watanabe

4th International Conference on Photonics, ICP 2013 - Conference Proceeding 129 - 131 2013年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, optically reconfigurable gate arrays (ORGAs), which can support a high-speed dynamic reconfiguration with numerous reconfiguration contexts, have been developed. Although an ORGA is a three-dimensional VLSI, no through-silicon via (TSV) technology or any micro-bump technology is never necessary to produce an ORGA. A three-dimensional ORGA uses only free-optical connections and a volume-type holographic memory technology. Therefore, the yield ratio of ORGAs is so high that ORGAs can easily be produced with no concern related to production variation. In this study, to increase the gate density, a short wavelength laser of 404 nm is applied to ORGA architecture. This paper presents the reconfiguration capabilities of the reconfiguration period and retention time of the photodiode memory architecture of a newly fabricated ORGA-VLSI. © 2013 IEEE.

DOI： 10.1109/ICP.2013.6687090

Angle-multiplexing recording of multi-context for optically reconfigurable gate array in holographic memory using liquid crystal composites 査読

Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

2013 18TH MICROOPTICS CONFERENCE (MOC) 2013年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using successive laser exposures in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The configuration contexts corresponding to the various logical circuits are reconstructed by the laser illumination at different incident angle in the HPDLC memory.

Temperature dependence of anisotropic diffraction in holographic polymer-dispersed liquid crystal memory 査読

Akifumi Ogiwara, Minoru Watanabe, Retsu Moriwaki

APPLIED OPTICS 52 ( 26 ) 6529 - 6536 2013年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Grating devices using photosensitive organic materials play an important role in the development of optical and optoelectronic systems. High diffraction efficiency and polarization dependence achieved in a holographic polymer-dispersed liquid crystal (HPDLC) grating are expected to provide polarization-controllable optical devices, such as a holographic memory for optically reconfigurable gate arrays (ORGAs). However, the optical property is affected by the thermal modulation around the transition temperature (T-ni) where the liquid crystal (LC) changes from nematic to isotropic phases. The temperature dependence of the diffraction efficiency in HPDLC grating is investigated using four types of LC composites comprised of LCs and monomers having different physical properties such as T-ni and anisotropic refractive indices. The holographic memory formed by the LC with low anisotropic refractive index and LC diacrylate monomer implements optical reconfiguration for ORGAs at a high temperature beyond T-ni of LC. (c) 2013 Optical Society of America

DOI： 10.1364/AO.52.006529

IMAGE RECOGNITION OPERATION ON A DYNAMICALLY RECONFIGURABLE VISION ARCHITECTURE 査読

Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito

2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS 1 - 4 2013年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

DOI： 10.1109/FPL.2013.6645603

A fine-grained dependable optically reconfigurable gate array as a multi-soft-core processor platform 査読

Retsu Moriwaki, Minoru Watanabe

Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 7 - 12 2013年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Optically reconfigurable gate arrays (ORGAs) have been developed as high-speed reconfigurable fine grained gate arrays that can accommodate implementation of a multi-soft-core processor. An ORGA's programmable gate array can be reconfigured in nanosecond-order with one of more than 256 reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the functions of a multi-core processor. In addition to that beneficial feature, ORGAs have high dependability against space radiation since the ORGA can be reconfigured with an error-included configuration context. In this paper, while maintaining its highly dependable capability, a more advanced dependability-increasing technique using a negative logic implementation is proposed. The dependability of data on a holographic memory depends on the number of bright bits or the binary state H included in a configuration context. If the number of bright bits in a configuration context can be decreased, then the configuration dependability can also be increased. The proposed optical configuration dependability-increasing technique of a negative logic implementation can decrease the number of bright bits in a configuration context. This technique can raise the ORGA's configuration dependability level even further. This paper describes an experimental demonstration of the usefulness of the proposed technique. © 2013 IEEE.

DOI： 10.1109/MCSoC.2013.33

Fourier transformation on an optically reconfigurable gate array 査読

Hiroyuki Ito, Minoru Watanabe

2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) 193 - 196 2013年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, optically reconfigurable gate arrays (OR-GAs) consisting of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI have been developed to realize fast reconfiguration and numerous reconfiguration contexts. Numerous configuration contexts can be stored on a holographic memory and can be programmed dynamically onto a gate array in a nanosecond-order period. Such highspeed dynamic reconfiguration enables a large virtual gate over a physical gate, for example a 1 Tera-gate VLSI. However, in addition to the advantages, the ORGA architecture allows high-speed optical Fourier transformation by addition of a programmable Fresnel lens. This paper presents a proposal of a new ORGA architecture to support Fourier transformation and results of its demonstration.

DOI： 10.1109/MWSCAS.2013.6674618

Configuration on an optically reconfigurable gate array under the maximum 120°C temperature condition 査読

R. Moriwaki, M. Watanabe, A. Ogiwara

OptoElectronics and Communications Conference 1 - 2 2013年7月

A 7-depth search FPGA Connect6 Solver 査読

R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, A. Tanigawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 95 - 98 2013年6月

Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method 査読

Yuichiro Yamaji, Minoru Watanabe

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013 172 - 177 2013年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We have been developing Optically Reconfigurable Gate Arrays (ORGAs) with higher radiation tolerance than that of a Field Programmable Gate Array (FPGA). The ORGA configuration is extremely robust against radiation. Moreover, that radiation tolerance of ORGA's programmable gate array can be increased by exploiting the advantageous high-speed dynamic reconfiguration of an ORGA. Although an ORGA has such a radiation-tolerance benefit, a lot of lasers that are necessary for addressing a holographic memory present concerns related to cost. Therefore, MEMS technology was introduced to reduce the number of lasers. Using a novel interleaving method, the reconfiguration speed is maintained as 10 ns: 1000 lasers and 1,000,000 MEMS mirrors can address one million configuration contexts. This paper presents a proposal of more advanced technique by which one mirror can address four configuration contexts by controlling the mirror angle. Although MEMS mirrors are not expensive, the proposed method contributes to the miniaturization of an ORGA package and to weight reduction. © 2013 IEEE.

DOI： 10.1109/AHS.2013.6604242

A dependability-increasing demonstration for a 16-configuration context optically reconfigurable gate array 査読

A. Tanigawa, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 129 - 132 2013年6月

Formation of holographic memory by recording of multi-context in liquid crystal composites

Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

2013 Conference on Lasers and Electro-Optics Pacific Rim (CLEOPR) 1 - 2 2013年6月

Dependability-increasing technique for a multi-context optically reconfigurable gate array 査読

Akira Tanigawa, Minoru Watanabe

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1568 - 1571 2013年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array with more than 100 reconfiguration contexts can be reconfigured in nanosecondorder. In addition to that beneficial feature, ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment. Even if 35 % or 5,915 pixels of holographic memory data are damaged by high-energy charged particles, the ORGA can execute configuration operations correctly. Therefore, ORGAs are sufficiently robust devices for use in spaceradiation environments. This paper presents a proposal of a more advanced dependability-increasing technique on a multicontext ORGA. This technique can raise the ORGA's level of configuration dependability even further by exploiting multicontext implementation.

DOI： 10.1109/ISCAS.2013.6572159

0.18 μm CMOS process photodiode memory 査読

T. Kubota, M. Watanabe

IEEE International Symposium on Circuits and Systems 1464 - 1467 2013年5月

MEMS interleaving method for optically reconfigurable gate arrays 査読

Y. Yamaji, M. Watanabe

IEEE International Conference on Electro/Information Technology 172 - 177 2013年5月

Formation of temperature dependable holographic memory using holographic polymer-dispersed liquid crystal 査読

Akifumi Ogiwara, Minoru Watanabe, Retsu Moriwaki

Optics Letters 38 ( 7 ) 1158 - 1160 2013年4月

記述言語：英語掲載種別：研究論文（学術雑誌）

Grating devices using photosensitive organic materials play an important role in the development of optical and optoelectronic systems. High diffraction efficiency and polarization dependence achieved in a holographic polymerdispersed liquid crystal (HPDLC) grating are expected to provide polarization controllable optical devices, such as the holographic memory for optically reconfigurable gate arrays (ORGAs). However, the optical property is affected by the thermal modulation around the transition temperature (T ni) that the liquid crystal (LC) changes from nematic to isotropic phases. The temperature dependence of the diffraction efficiency in HPDLC grating is discussed with two types of LC composites comprised of isotropic and LC diacrylate monomers. The holographic memory formed by the LC and LC diacrylate monomer performs precise reconstruction of the context information for ORGAs at high temperatures more than 150°C. © 2013 Optical Society of America.

DOI： 10.1364/OL.38.001158

Power consumption of mono-instruction set computers (MISCs) 査読

H. Ito, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 2013年4月

Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation 査読

Retsu Moriwaki, Minoru Watanabe

Applied Optics 52 ( 9 ) 1939 - 1946 2013年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OSA - The Optical Society

This paper presents a proposal of an optical configuration acceleration method applied to optically reconfigurable gate arrays (ORGAs) using a negative logic implementation. The gate array of an ORGA is reconfigured using a holographic memory. The reading time of a holographic memory depends on the number of bright bits included in a configuration context. The proposed optical configuration acceleration method can decrease the number of bright bits. As a result, the proposed optical configuration acceleration method can increase the reconfiguration frequency. In this paper, a fabricated ORGA very large scale integration that can support the optical configuration acceleration method is estimated. Consequently, this paper shows that the reconfiguration frequency of the proposed method is 1.97 times higher than those of conventional ORGA architectures with no increase of laser power. © 2013 Optical Society of America.

DOI： 10.1364/AO.52.001939

Dependability-increasing method of processors under a space radiation environment 査読

Yuya Shirahashi, Minoru Watanabe

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7806 218 2013年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) can be reconfigured using error-inclusive configuration contexts under a radiation-rich space environment. Therefore, the ORGA presents an important benefit: the allowable amount of configuration data damage is greater than that by field programmable gate arrays (FPGAs) with error-checking and correction. However, the ORGA's programmable gate array itself is never as robust against space radiation as that of an application-specific integrated circuit (ASIC) because the programmable architecture of its gate array is the same as that of FPGAs. Therefore, to achieve a drastic increase in the robust capability of a fine-grained programmable gate array on an ORGA-VLSI, this paper presents a proposal of a novel dynamic module multiple redundancy scheme based on a mono-instruction set computer architecture exploiting high-speed dynamic reconfiguration. © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-36812-7_21

Temperature Dependable Holographic Memory Using Holographic Polymer-dispersed Liquid Crystal 査読

A. Ogiwara, M. Watanabe, R. Moriwaki

Progress In Electromagnetics Research Symposium 322 - 325 2013年3月

A 9-configuration-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory

R. Moriwaki, M. Watanabe, A. Ogiwara

Takayanagi Kenjiro Memorial Symposium 112 ( 325 ) S3_10_1 - S3_10_4 2012年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：一般社団法人電子情報通信学会

我々は現在,レーザアレイ,ホログラムメモリ,ゲートアレイVLSIから構成され,光による高速動的再構成が可能な光再構成型ゲートアレイを研究開発している.光再構成型ゲートアレイの特徴として,高速動的再構成と大規模なコンテキスト情報数の記憶が挙げられる.しかし,これまで光再構成型ゲートアレイは構造上,コンテキスト情報数に応じてレーザが必要なので,既存のプログラマブルデバイスと比較して価格が高くなるという問題点があった.そこで我々は,偏光依存性ホログラムメモリを用いることにより,レーザ数を削減できる光再構成型ゲートアレイのアーキテクチャを考案した.本稿では,偏光依存性ホログラムメモリを用いた9コンテキスト光再構成型ゲートアレイの試作結果について報告する.

A uniform partitioning method for mono-instruction set computer (MISC) 査読

Hiroyuki Ito, Minoru Watanabe

Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012 832 - 837 2012年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

As gates in field programmable gate arrays (FPGAs) become usable in ever-increasing numbers, FPGAs are becoming more widely applied in various embedded systems. FPGAs have been demonstrated as useful renewable devices. Recently however, a hard-core processor inside an FPGA is frequently used for high-performance systems so that the implementation of the hard-core processor decreases the possibility of a specification change and reuse of its FPGA. Therefore, demand for implementing a soft-core processor onto an FPGA is gaining. In response to that demand, FPGA vendors have provided soft-core processors for FPGAs, but those processors invariably provide lower performance than hard-core processors do. Therefore, this paper presents high-performance mono-instruction set computer (MISC) architecture that fully exploits the programmability of a dynamically reconfigurable fine-grained gate array. In addition, this paper presents a proposal of a uniform partitioning method for the MISC architecture. © 2012 IEEE.

DOI： 10.1109/NBiS.2012.107

A 256-configuration-context MEMS optically reconfigurable gate array 査読

Y. Yamaji, M. Watanabe

International Conference on Solid State Devices and Materials 232 - 233 2012年9月

Inversion/non-inversion reconfiguration scheme for a 0.18 μm CMOS process optically reconfigurable gate array VLSI 査読

Takahiro Watanabe, Minoru Watanabe

2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) 117 - 120 2012年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present advantageous capabilities compared with other ORGAs: they have increased the reconfiguration frequency per unit of laser power and have reduced optical configuration power consumption. On the other hand, dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density, but an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical configuration power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array has been developed, adopting only the best attributes from both architectures. This paper presents an inversion/non-inversion implementation for a newly fabricated 0.18 mu m CMOS process optically reconfigurable gate array VLSI.

DOI： 10.1109/MWSCAS.2012.6291971

0.18 μm CMOS Process highly sensitive differential optically reconfigurable gate array VLSI 査読

Takahiro Watanabe, Minoru Watanabe

2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) 308 - 313 2012年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Currently, demand is increasing for high-speed dynamic reconfiguration on programmable devices to improve their performance. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been undergoing rapid development. Moreover, to more increase the reconfiguration speed, optically differential reconfigurable gate arrays (ODRGAs) incorporating a differential reconfiguration method between configuration contexts have been developed. An ODRGA comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Its large-bandwidth optical connection enables high-speed reconfiguration. However, photodiode sensitivities of conventional ODRGAs are not good. This paper therefore presents a newly fabricated 0.18 mu m CMOS process optically differential reconfigurable gate array VLSI chip with highly sensitive photo-circuits.

DOI： 10.1109/ISVLSI.2012.71

A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function 査読

Takashi Yoza, Minoru Watanabe

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 361 - 366 2012年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a robust VLSI chip that is useful in a radiation-rich environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a radiation-tolerant Field Programmable Gate Array (FPGA). The ORGA architecture is extremely robust against multi-event upsets. Moreover, it can recover from permanent errors resulting from a heavy total radiation dose. This paper presents demonstration results of a 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed-adjustment function. © 2012 IEEE.

DOI： 10.1109/FPL.2012.6339205

Optical reconfiguration by anisotropic diffraction in holographic polymer-dispersed liquid crystal memory 査読

Akifumi Ogiwara, Minoru Watanabe

APPLIED OPTICS 51 ( 21 ) 5168 - 5177 2012年7月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Holographic polymer dispersed liquid crystal (HPDLC) memory is fabricated by a photoinduced phase separation comprised of polymer and liquid crystal (LC) phases using laser light interference exposures. The anisotropic diffraction induced by the alignment of LC in the periodic structure of the HPDLC memory is applied to reconstruct the configuration contexts for the optically reconfigurable gate arrays. Optical reconfiguration for various circuits under parallel programmability is implemented by switching the polarization state of incident light on the HPDLC memory using a spatial light modulator. (C) 2012 Optical Society of America

DOI： 10.1364/AO.51.005168

Methods for detection and compensation of alignment errors occurring between a programmable optically reconfigurable gate array and its writer system 査読

Shinya Kubota, Minoru Watanabe

PROCEEDINGS OF THE 2012 IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON) 182 - 185 2012年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSls. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, in contrast to current field-programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: alignment errors arise when a programmable ORGA is recorded with a writer system. When programming a programmable ORGA along with alignment errors between the programmable ORGA and its writer system, the reconfiguration speed of the programmable ORGA is decreased. This paper therefore presents a detection and compensation method of alignment errors between a programmable ORGA and a writer system to alleviate that shortcoming.

DOI： 10.1109/NAECON.2012.6531052

Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation 査読

R. Moriwaki, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 127 - 132 2012年7月

A 4-configuration context fiber-linked optically reconfigurable gate array 査読

Yumiko Ueno, Minoru Watanabe

Technical Digest - 2012 17th Opto-Electronics and Communications Conference, OECC 2012 592 - 593 2012年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, fiber networks and undersea fiber optic cables have become widely used throughout the world. Because of its much lower attenuation and interference, optical fiber is superior to copper wire for long-distance applications. Optical fiber data transfer rates and distances reach GHz-order and over 100 km. Previously, a remote configurable field programmable gate array (FPGA) system using current fiber networks was reported. However, since its configuration speed was very low, dynamic high-speed reconfiguration was impossible. Therefore, this paper presents a 4-configuration context fiber-linked optically reconfigurable gate array using a bundle of fiber networks and an optically reconfigurable gate array. © 2012 IEEE.

DOI： 10.1109/OECC.2012.6276587

A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array 査読

Takashi Yoza, Minoru Watanabe

2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) 92 - 98 2012年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a large-gate-count robust VLSI chip that is useful in a radiation-rich space environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. © 2012 IEEE.

DOI： 10.1109/AHS.2012.6268635

0.18 μm CMOS process high-sensitivity optically reconfigurable gate array VLSI 査読

T. Watanabe, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 147 - 151 2012年5月

FPGA Connect6 Solver with Hardware Sort Units 査読

R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, T. Watanabe, Y. Aoyama, M. Seo, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 163 - 166 2012年5月

High speed - low power optical configuration on an ORGA with a phase-modulation type holographic memory 査読

Takahiro Watanabe, Minoru Watanabe

2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW) 256 - 260 2012年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) with an amplitude-modulation type holographic memory have been developed as a type of multi-context field programmable gate array. The ORGA's programmable gate array can be reconfigured in nanosecond-order, with more than 100 reconfiguration contexts. However, the diffraction efficiency of the amplitude-modulation type holographic memory is not good because the holographic memory decreases its transmission light intensity depending on the modulation level. About half of the power of the laser is consumed by the holographic memory. Therefore, this paper presents a high-speed - low-power optical configuration capability of an ORGA with a phase-modulation type holographic memory.

DOI： 10.1109/IPDPSW.2012.28

Mono-instruction computer on a dynamically reconfigurable gate array 査読

Y. Nihira, M, Watanabe

Workshop on Synthesis And System Integration of Mixed Information technologies 66 - 70 2012年3月

Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arrays 査読

Takahiro Watanabe, Minoru Watanabe

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7199 163 - 173 2012年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a robust field programmable gate array that is useful for operations performed in a radiation-rich space environment, such as those of spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) are under development as robust field programmable gate arrays. Their holographic memories can generate correct configuration contexts at any time, even if up to 20 % of the holographic memory data are damaged. However, up to now, a soft error effect for a laser array on ORGA devices has never been discussed. Therefore, this paper first presents a proposal of a method to find an unexpected configuration procedure caused by a laser array driver circuit facing a soft error on conventional ORGA architectures and to recover from such a procedure. Then this paper presents a proposal of a new robust laser array driver circuit that is applicable for any ORGA architecture, which can perfectly remove the unexpected configuration procedure itself. © 2012 Springer-Verlag.

DOI： 10.1007/978-3-642-28365-9_14

A full dynamically reconfigurable vision-chip system including a lens-array 査読

Y. Kamikubo, M. Watanabe, S. Kawahito

Workshop on Synthesis And System Integration of Mixed Information technologies 272 - 277 2012年3月

Dependable Optically Reconfigurable Gate Array

Minoru Watanabe

2012 International Workshop on Advanced Nanovision Science 47 - 50 2012年1月

Binary MEMS optically reconfigurable gate array for an artificial brain system 査読

Yuichiro Yamaji, Minoru Watanabe

PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON ARTIFICIAL LIFE AND ROBOTICS (AROB 17TH '12) 614 - 617 2012年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ALIFE ROBOTICS CO, LTD

Optically reconfigurable gate arrays (ORGAs) consisting of a holographic memory, a laser diode array, and a programmable gate array were developed to realize an artificial brain system for robots. In the ORGA, much information or many reconfiguration contexts can be stored in a volume-type holographic memory and can be programmed dynamically onto a programmable gate array at nanosecond-order perfectly in parallel. Therefore, by exploiting the huge storage capacity of the holographic memory and large parallel operations on a programmable gate array, huge parallel brain operations can be executed quickly on an ORGA. This paper presents a proposal of a binary MEMS-interleaving reconfiguration operation on an optically reconfigurable gate array for an artificial brain system.

Gray-level image recmgnitimrmn a dynamically recmnfigurablevisimnarchitecture 査読

Yuki Kamikubo, Minonu Witanabe, Shoji Kawahito

International System on Chip Conference 61 - 65 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, for fse in aftonomofs vehicles and robots, demand has been increasing for high-speed image recognition that is sfperior to that of the hfman eye. However, to recognize nfmerofs images qfickly, sfch system reqfires many template images to be read oft dynamically from memory. They mfst then be sent to a processor qfickly. Realizing sfch high-speed real-time image recognition operation is difficflt becafse of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigfrable vision architectfre that can recognize binarized images has been presented. However, to date, no dynamically reconfigfrable vision architectfre that can recognize gray-level images has ever been presented. Therefore, this paper presents experimentation related to a more advanced dynamically reconfigfrable vision architectfre that can recognize gray-level images. © 2012 IEEE.

DOI： 10.1109/SOCC.2012.6398381

Holographic polymer-dispersed liquid crystal memory for optically reconfigurable gate array using subwavelength grating mask 査読

Akifumi Ogiwara, Minoru Watanabe, Takayuki Mabuchi, Fuminori Kobayashi

APPLIED OPTICS 50 ( 34 ) 6369 - 6376 2011年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Holographic polymer-dispersed liquid crystal (HPDLC) memory formed by a subwavelength grating (SWG) mask is presented for new optical information processing. The SWG structure in a photomask is formed on the SiO2 plate using the anisotropic reactive ion etching technique. The configuration contexts for optically reconfigurable gate arrays (ORGAs) are stored in the HPDLC memory by polarization modulation property based on the form birefringence of the SWGplate. The configuration context pattern in the HPDLC memory is reconstructed to write it for the ORGAs under parallel programmability. (C) 2011 Optical Society of America

DOI： 10.1364/AO.50.006369

An FPGA Connect6 Solver with a Two-Stage Pipelined Evaluation 査読

Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe

2011 International Conference on Field-Programmable Technology, FPT 2011 2011年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, immediately following invention of a Connect6 game, many game programs were developed aggressively. However, because the solution space of the Connect6 game is extremely large, the computation powers of current computers are quite insufficient to search all possible solutions. This paper therefore presents a proposal of a field programmable gate array (FPGA) Connect6 Solver with a two-stage pipelined evaluation exploiting numerous zero-evaluation functions to evaluate only a zero value and a small number of detailed evaluation functions which can evaluate all range. The FPGA Connect6 Solver implemented onto a Cyclone IV FPGA is able to defeat target software provided by the 2011 International Conference on Field-Programmable Technology (ICFPT) within the time limit of 1 s for each turn. In addition, the FPGA Connect6 Solver can defeat another JAVA-based software program with a similar algorithm. At that time, the operation speed of the FPGA Connect6 Solver is 764.2 times higher than that of the software operating on a personal computer (Vostro 220S
Dell Inc.) with a 3.16 GHz, Core 2 Duo processor (Intel Corp.). © 2011 IEEE.

DOI： 10.1109/FPT.2011.6133249

Full liquid crystal spatial light modulator writer system for a programmable optically reconfigurable gate array 査読

S. Kubota, M. Watanabe

MICROOPTICS CONFERENCE H-47 2011年11月

Holographic polymer-dispersed liquid crystal memory for optically reconfigurable gate array using subwavelength grating mask 査読

OGIWARA Akifumi, WATANABE Minoru, MABUCHI Takayuki, KOBAYASHI Fuminori

APPLIED OPTICS 50 ( 34 ) 6369 - 6376 2011年11月

Robust holographic storage system design 査読

Takahiro Watanabe, Minoru Watanabe

OPTICS EXPRESS 19 ( 24 ) 24147 - 24158 2011年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Demand is increasing daily for large data storage systems that are useful for applications in spacecraft, space satellites, and space robots, which are all exposed to radiation-rich space environment. As candidates for use in space embedded systems, holographic storage systems are promising because they can easily provided the demanded large-storage capability. Particularly, holographic storage systems, which have no rotation mechanism, are demanded because they are virtually maintenance-free. Although a holographic memory itself is an extremely robust device even in a space radiation environment, its associated lasers and drive circuit devices are vulnerable. Such vulnerabilities sometimes engendered severe problems that prevent reading of all contents of the holographic memory, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal for a recovery method for the turn-off failure mode of a laser array on a holographic storage system, and describes results of an experimental demonstration. (C) 2011 Optical Society of America

DOI： 10.1364/OE.19.024147

Triple module redundancy scheme on an optically reconfigurable gate array 査読

Y. Torigai, M. Watanabe

International SoC Design Conference 250 - 253 2011年11月

Multi-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory 査読

R. Moriwaki, M. Watanabe, A. Ogiwara, F. Kobayashi

MICROOPTICS CONFERENCE 1 - 2 2011年11月

Holographic memory formed by multi-context recording for optically reconfigurable gate array 査読

A. Ogiwara, M. Watanabe, F. Kobayashi

17th Microopics Conference (MOC) 1 - 2 2011年11月

Dependable optically reconfigurable gate array with a phase-modulation type holographic memory 査読

Takahiro Watanabe, Minoru Watanabe

2011 21st International Conference on Field Programmable Logic and Applications 34 - 37 2011年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array can be reconfigured at nanosecond-order, with more than 100 reconfiguration contexts. In addition to that beneficial feature, since ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment, ORGAs are suitable for space applications. The robust capability of ORGAs with an amplitude modulation type holographic memory has already been demonstrated, but an ORGA with a phase-modulation type holographic memory that can achieve more robust capability has never been reported. Therefore, this paper presents a proposal of a new dependable ORGA architecture based on a phase-modulation type of holographic memory. In addition, this paper describes experimental clarification through a demonstration that the dependable ORGA is more robust than conventional ORGAs with an amplitude modulation type holographic memory. © 2011 IEEE .

DOI： 10.1109/FPL.2011.17

A Four-Context Programmable Optically Reconfigurable Gate Array With a Reflective Silver-Halide Holographic Memory 査読

Shinya Kubota, Minoru Watanabe

IEEE PHOTONICS JOURNAL 3 ( 4 ) 665 - 675 2011年8月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper presents a proposal for a four-context programmable optically reconfigurable gate array (PORGA) with a high-resolution reflective silver-halide holographic memory and a corresponding writer system. The PORGA demonstrates the capability of 4.6-11.5-mu s high-speed configuration context switching among four configuration contexts, which is 1000 times faster than that of conventional field programmable gate arrays (FPGAs).

DOI： 10.1109/JPHOT.2011.2160335

Novel dynamic module multiple redundancy for optically reconfigurable gate arrays

Minoru Watanabe

IEEE International Midwest Symposium on Circuits & Systems 2011年8月

Dynamic reconfiguration on a dynamically reconfigurable vision-chip architecture 査読

A. Gundjalam, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 2011年7月

A MEMS writer system embedded for a programmable optically reconfigurable gate array 査読

S. Kubota, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 130 - 135 2011年6月

Optically reconfigurable gate array with a polymer-dispersed liquid crystal holographic memory 査読

Takayuki Mahuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011 44 - 49 2011年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of high-fault-tolerance multi-context field programmable gate array for space applications under radiation-rich environments. However, although many configuration contexts can be stored on an ORGA device and can be implemented on its gate array dynamically in an extremely short time, several laser sources are necessary to address the configuration contexts. Since such lasers are always expensive and because such devices are easily damaged by surge current, reducing the number of lasers is an important factor. Therefore, this paper presents a proposal of a new optically reconfigurable gate array with a polymer-dispersed liquid crystal holographic memory. Under the ORGA, all configuration contexts can be addressed by half the number of lasers as there are reconfiguration contexts. This paper presents demonstration results of the optically re-configurable gate array obtained using a polymer-dispersed liquid crystal holographic memory. © 2011 IEEE.

DOI： 10.1109/AHS.2011.5963965

Parallel template matching operations on a dynamically reconfigurable vision-chip architecture 査読

Hironari Nakada, Minora Watanabe, Shoji Kawahito

2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 205 - 208 2011年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, high-speed image recognition functionality that is superior to the image recognition speed of the human eye is demanded for autonomous vehicles and robots. Currently, such embedded systems comprise a processor and memory. To recognize many images, many template images must be stored in memory and must be sent quickly from memory to the processor. For example, assuming that the system receives an external image with 1 million pixels at every 1 ms and assuming that the system must execute template-matching operations of 1 million template images with the same million pixels within 1 ms, then the transfer speed from the memory to the processor and the processor operation reaches 1 Petapixel/s. Therefore, to realize high-speed template-matching operation, a dynamically reconfigurable vision-chip architecture with a holographic memory and large-bandwidth optical connections has been proposed. Among such researches, this paper presents a proposal of novel parallel template-matching operations performed on the dynamically reconfigurable vision-chip architecture. Furthermore, the advantages of the new method are discussed based on some demonstration results. © 2011 IEEE.

DOI： 10.1109/NEWCAS.2011.5981291

A 16-laser array for an optically reconfigurable gate array 査読

Takahiro Watanabe, Minoru Watanabe

2011 International Conference on Space Optical Systems and Applications, ICSOS'11 255 - 260 2011年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand is increasing daily for a robust VLSI chip that is useful for operating under a radiation-rich space environment, such as spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. This paper presents a robust 16-laser array for an optically reconfigurable gate array and its demonstration results. © 2011 IEEE.

DOI： 10.1109/ICSOS.2011.5783679

A configuration-speed acceleration method for a sequential circuit using a negative logic implementation 査読

Retsu Moriwaki, Minoru Watanabe

2011 International Conference on Space Optical Systems and Applications, ICSOS'11 213 - 217 2011年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

An optically reconfigurable gate array (ORGA) was developed recently as one multi-context device to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers, but such lasers increase the ORGA power consumption and package size. In some cases, they might even require a cooling system. For that reason, this paper presents a configuration speed acceleration method for a sequential circuit using a negative logic implementation without ORGA architecture modification and without any increase of laser power. Based on experimentally obtained results, this paper clarifies the acceleration method's effectiveness. © 2011 IEEE.

DOI： 10.1109/ICSOS.2011.5783670

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control 査読

Mao Nakajima, Minoru Watanabe

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 4 ( 2 ) 2011年5月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ASSOC COMPUTING MACHINERY

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

DOI： 10.1145/1968502.1968506

Reduction method of refresh cycles for a dynamic optically reconfigurable gate array 査読

Y. Aoyama, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 2011年4月

Programming Options for an Optical FPGA with Clockwise Dynamic Reconfigurability 査読

F. Matsusaki, F. Kobayashi, A. Nagino, M. Watanabe

International Conference on Innovative Computing and Communication and Asia-Pacific Conference on Information Technology and Ocean Engineering 2011年3月

MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays 査読

Hironobu Morita, Minoru Watanabe

RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS 6578 242 - 252 2011年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Optically reconfigurable gate array (ORGAs) were developed to realize next-generation large-virtual gate count programmable VLSIs. An ORGA consists of an ORGA-VLSI, a holographic memory, and a laser array, which is used for addressing the holographic memory. Since many configuration contexts can be stored on a volume-type holographic memory, the corresponding number of lasers must he implemented on an ORGA. However, a laser array with numerous lasers is always expensive. Therefore, to accommodate numerous configuration contexts with fewer lasers, this paper presents a novel method using an interleaving read operation of a holographic memory for ORGAs. This method can provide an addressing capability of a billion configuration contexts along with a nanosecond-order high-speed configuration capability.

DOI： 10.1007/978-3-642-19475-7_25

A 144-configuration context MEMS optically reconfigurable gate array 査読

Yuichiro Yamaji, Minoru Watanabe

2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) 237 - 241 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for space uses of FPGAs is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. However, under a space radiation environment, the incidence of high-energy charged particles causes single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 144-configuration context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment.

DOI： 10.1109/SOCC.2011.6085083

A 64-context MEMS optically reconfigurable gate array 査読

Yuichiro Yamaji, Minoru Watanabe

2010 International Conference on Field-Programmable Technology 499 - 502 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for use of FPGAs in space is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. Under a space radiation environment, embedded devices must allow for incidence of high-energy charged particles. Such incidence can cause single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 64-context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment. © 2010 IEEE.

DOI： 10.1109/FPT.2010.5681467

Fiber remote configuration for an optically reconfigurable gate array with four configuration contexts 査読

Yumiko Ueno, Minoru Watanabe

OPTICS COMMUNICATIONS 283 ( 23 ) 4614 - 4618 2010年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ELSEVIER SCIENCE BV

A function enabling remote programming is necessary for systems used with nuclear power plants, high-energy physics experiments, and other plants with no personnel Recently, optically reconfigurable gate array (ORGA) architecture has been developed to achieve a huge virtual gate count that is much greater than those of currently available VLSIs However, ORGA architectures have never supported a remote programming capability since a complicated holographic writer system is required along with an ORGA for that purpose. This paper therefore presents a proposal of a new remotely reconfigurable gate array architecture with four configuration contexts that enable remote reconfiguration using optical fiber networks Furthermore, this paper presents discussion of the availability of this architecture and plans based on the experimental results (C) 2010 Elsevier B V All rights reserved

DOI： 10.1016/j.optcom.2010.06.090

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capabilit 査読

D. Seto, M. Nakajima, M. Watanabe

Applied Optics 49 ( 36 ) 6986 - 6994 2010年12月

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability 査読

Daisaku Seto, Mao Nakajima, Minoru Watanabe

APPLIED OPTICS 49 ( 36 ) 6986 - 6994 2010年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 mu m three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 mu s partial reconfiguration. (C) 2010 Optical Society of America

Multi-context programmable optically reconfigurable gate array using a silver-halide holographic memory 査読

Shinya Kubota, Minoru Watanabe

2010 IEEE/SICE International Symposium on System Integration: SI International 2010 - The 3rd Symposium on System Integration, SII 2010, Proceedings 431 - 435 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, as one dynamic reconfigurable device, optically reconfigurable gate arrays (ORGAs) that consist of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve greater than 1 Teragate virtual integration, which is much greater than the integration that is possible using currently available VLSIs. If the ORGA can be used, a large software system can be implemented directly as hardware so that a large real-time system can be realized. Currently, a programmable ORGA architecture has been proposed to support user programmability. This paper presents the demonstration result of a multi-context programmable ORGA using a silver-halide non-volatile holographic memory and a corresponding writer system. ©2010 IEEE.

DOI： 10.1109/SII.2010.5708364

Othello solver based on a soft-core MIMD processor array 査読

Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe

2010 International Conference on Field-Programmable Technology 511 - 514 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchronous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results. © 2010 IEEE.

DOI： 10.1109/FPT.2010.5681470

Background light effect of a dynamically reconfigurable vision-chip architecture 査読

Retsu Moriwaki, Minoru Watanabe

2010 IEEE/SICE International Symposium on System Integration: SI International 2010 - The 3rd Symposium on System Integration, SII 2010, Proceedings 426 - 430 2010年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, demands for implementation of a high-speed image recognition function onto autonomous vehicles and robots, that is superior to that of the human eye, have been increasing. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, realizing such high-speed real-time image recognition operation is extremely difficult because the template information transfer rate and template matching operation cycle reach the order of Petapixel/s. Therefore, to accommodate template matching operations that can be executed at rates greater than Petapixel/s, a dynamically reconfigurable vision-chip architecture has been developed in which a holographic memory technique is introduced to current VLSI technology. However, the dynamically reconfigurable vision-chip architecture must receive image information in addition to configuration context information. At such a time, a salient concern is that image information light might reduce the retention time of photodiode memories on a dynamically reconfigurable vision-chip. This paper therefore clarifies that the background light does not affect the photodiode memories on a dynamically reconfigurable vision-chip architecture. ©2010 IEEE.

DOI： 10.1109/SII.2010.5708363

A retention time improvement method for a MEMS dynamic optically reconfigurable gate array 査読

Hironobu Morita, Minoru Watanabe

2010 International Symposium on Micro-NanoMechatronics and Human Science: From Micro and Nano Scale Systems to Robotics and Mechatronics Systems, MHS 2010, Micro-Nano GCOE 2010, Bio-Manipulation 2010 257 - 261 2010年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, optically reconfigurable gate arrays (ORGAs) have been developed to address high-speed operations. During that development, a MEMS dynamic optically reconfigurable gate array architecture was proposed: it perfectly removes the static configuration memory to store a context and uses junction capacitances of photodiodes as dynamic configuration memory to realize high-gate count ORGA-VLSI. However, this architecture presents the issue that retention time of programmed circuits on a gate array is, just like DRAMs, not infinite. Since the circuit reconfiguration frequency is always superior to the refresh cycle frequency, the refresh cycle problem need not be considered. However, circuits with a long lifetime exist among the many implementation circuits. For these circuits, many refresh cycles must be required continuously. Therefore, This paper presents a proposal of a retention time improvement method by adjusting the threshold level in the holographic memory calculation. ©2010 IEEE.

DOI： 10.1109/MHS.2010.5669547

High-speed fiber-linked remote reconfiguration 査読

Yumiko Ueno, Minoru Watanabe

TENCON 2010 - 2010 IEEE Region 10 Conference 1203 - 1206 2010年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, fiber networks and undersea fiber optic cables have become widely used throughout the world. Because of its much lower attenuation and interference, optical fiber is superior to copper wires for long-distance applications. Such fibers' transfer rates and distances reach GHz-order and over 100 km. Up to now, a remote configurable FPGA system using current fiber networks was reported. However, since its configuration speed was very low, dynamic highspeed reconfiguration was impossible. This paper therefore presents a high-speed remote reconfiguration experiment using a bundle of fiber networks and an optically reconfigurable gate array. Such architecture presents the possibility of a remote high-speed dynamic reconfigurable hardware system.

DOI： 10.1109/TENCON.2010.5686374

Template matching operations on a dynamically reconfigurable vision-chip architecture 査読

Hironari Nakada, Minoru Watanabe

2010 10th International Symposium on Communications and Information Technologies 1091 - 1096 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper experimentally presents a template matching operations on a dynamically reconfigurable vision-chip architecture. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665152

Formation of holographic memory using subwavelength grating mask for optically reconfigurable gate array 査読

A. Ogiwara, M. Watanabe, T. Mabuchi, F. Kobayashi

MICROOPTICS CONFERENCE 108 - 109 2010年10月

Development of optically reconfigurable gate arrays

Minoru Watanabe

International Symposium on Optical Memory 188 - 189 2010年10月

Fault tolerance of a holographic storage system 査読

Takahiro Watanabe, Minoru Watanabe

2010 10th International Symposium on Communications and Information Technologies 1126 - 1130 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand is increasing daily for large storage systems that are useful for devices operating under a radiation-rich space environment, such as spacecraft, space satellites, and space robots. A holographic storage system, which can easily provide large storage capacity, is a candidate for space embedded systems. The holographic storage system, which requires no rotation mechanism, usually consists of a holographic memory material, a laser array, and a photodiode array. Although a holographic memory itself is an extremely robust device for use in a space radiation environment, its associated components are vulnerable to radiation. Such vulnerable devices can cause severe problems by preventing the reading of all holographic memory contents. This is a turn-off failure mode of a laser array. This paper therefore presents a recovery method for a turn-off failure mode of a laser array on a holographic storage system and presents results of its demonstration. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665158

Recovery method for a laser array failure on Dynamic Optically Reconfigurable Gate Arrays 査読

Daisaku Seto, Minoru Watanabe

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems 411 - 419 2010年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Demand is increasing daily for a large-gate-count robust VLSI chip that can be used in a radiation-rich space environment. Since they exploit the large storage capacity of a holographic memory, optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a recovery method for a turn-off failure mode of a laser array on a DORGA and its demonstration results.

DOI： 10.1109/DFT.2010.55

Programmable optically reconfigurable gate array using a silver-halide holographic memory including six configuration contexts 査読

S. Kubota, M. Watanabe

International Conference on Solid State Devices and Materials 67 - 68 2010年9月

Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array 査読

Yuji Aoyama, Minoru Watanabe

23rd IEEE International SOC Conference 243 - 247 2010年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) have been developed to realize large virtual gates and to increase gate array performance. Since the performance of gate arrays in dynamically reconfigurable gate arrays can be increased as increasing its reconfiguration clock frequency, a high-speed reconfiguration capability is extremely important. However, the efficiency of a conventional optical configuration is not good because the optical configuration speed suffers from the photodiode characteristic variation, optical component variation, alignment errors, and holographic memory properties. This paper therefore presents a proposal of a compensation method using an analog configuration context that can improve the optical configuration efficiency. Based on the experimental results, this paper presents a discussion of its performance. © 2010 IEEE.

DOI： 10.1109/SOCC.2010.5784753

Microelectromechanical Configuration of an Optically Reconfigurable Gate Array 査読

Hironobu Morita, Minoru Watanabe

IEEE JOURNAL OF QUANTUM ELECTRONICS 46 ( 9 ) 1288 - 1294 2010年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper presents a proposal of a novel optically reconfigurable gate array architecture with a microelectromechanical system (MEMS) mirror array that allows high-speed reconfiguration by exploiting large-bandwidth optical connections between the MEMS mirror array and a programmable gate array. The MEMS mirror array is used as a holographic memory. Four configuration contexts can be programmed electrically and dynamically onto the MEMS mirror array as holographic memory information. The configuration procedure is executed by switching both a laser array and an MEMS mirror array. This experiment demonstrated a four-context 146 ns microelectromechanical configuration for a programmable gate array. Submicrosecond configuration is attainable.

DOI： 10.1109/JQE.2010.2047378

Relationship between alignment errors of optical components and power consumption in optoelectronic devices 査読

Hironobu Morita, Minoru Watanabe

2010 IEEE CPMT Symposium Japan, ICSJ10 2010年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Field Programmable Gate Arrays (FPGAs) have been used widely in recent years because of their flexible reconfiguration capabilities. Moreover, demand of high-speed reconfiguration for FPGAs has been increasing. However, since reconfiguration of FPGAs cannot be increased because of the serial transfer of configuration data, new optically reconfigurable gate arrays (ORGAs) have been proposed as an alternative device to achieve high-speed reconfiguration and numerous reconfiguration contexts. However, in the ORGAs, alignment errors affect the configuration power consumption. This paper presents the relation between alignment errors of optical components and power consumption in optoelectronic devices. ©2010 IEEE.

DOI： 10.1109/CPMTSYMPJ.2010.5680217

Superimposing acceleration and optimization method of optical reconfiguration speed without any increase of laser power 査読

Takayuki Mabuchi, Minoru Watanabe

APPLIED OPTICS 49 ( 22 ) 4120 - 4126 2010年8月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

This paper proposes a method of superimposing acceleration and optimizing the optical reconfiguration speed while requiring no increase of laser power. Using this technique, the optical reconfiguration speed is increased by superimposing multiple configuration contexts. Simultaneously, optimization of the number of configuration contexts and reconfiguration speed is possible. A full four-context optically reconfigurable gate array system consisting of an optically reconfigurable gate array VLSI, an easily rewritable liquid crystal holographic memory, and four vertical-cavity surface-emitting lasers was constructed to demonstrate this method. This paper clarifies the method's benefits using experimental results obtained from the demonstration system. (C) 2010 Optical Society of America

DOI： 10.1364/AO.49.004120

Formation of holographic memory for defect tolerance in optically reconfigurable gate arrays 査読

OGIWARA Akifumi, WATANABE Minoru, MABUCHI Takayuki, KOBAYASHI Fuminori

APPLIED OPTICS 49 ( 22 ) 4255 - 4261 2010年8月

A superimposing acceleration and optimization method of optical reconfiguration speed without any increase of laser power 査読

MABUCHI Takayuki, WATANABE Minoru

APPLIED OPTICS 49 ( 22 ) 4120 - 4126 2010年8月

Formation of holographic memory for defect tolerance in optically reconfigurable gate arrays 査読

Akifumi Ogiwara, Minoru Watanabe, Takayuki Mabuchi, Fuminori Kobayashi

APPLIED OPTICS 49 ( 22 ) 4255 - 4261 2010年8月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Holographic polymer-dispersed liquid-crystal (HPDLC) memory using liquid-crystal composites is proposed for new optical information processing. Formation of HPDLC memory using a photomask is discussed for parallel programmability to realize fast reconfiguration of optically reconfigurable gate arrays (ORGAs). The defect tolerance of HPDLC memory is investigated to clarify the defect limitation of holographic configurations using ORGAs. Experimental results show that the noise ratio less than 15% applied to HPDLC memory rarely affects its diffraction pattern or a reconfiguration context. (C) 2010 Optical Society of America

DOI： 10.1364/AO.49.004255

Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array 査読

Shinya Kubota, Minoru Watanabe

2010 53rd IEEE International Midwest Symposium on Circuits and Systems 913 - 916 2010年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. However, comparison of conventional ORGAs with current field programmable gate arrays (FPGAs) reveals one important shortcoming: they are not reprogrammable after fabrication. To remove that shortcoming, a programmable ORGA (PORGA) has been proposed. However, a PORGA must implement a window to detect holographic memory patterns. A PORGA window might have scratches, fingerprints, or other defects that could occur while a PORGA is used. Even under such situations, a PORGA must be programmable. This paper therefore presents influence analysis of a holographic memory window of a PORGA. It has been demonstrated that even if a window of PORGA has scratches, fingerprint, or defects, a programming procedure can be executed correctly.

DOI： 10.1109/MWSCAS.2010.5548776

Excellent fault tolerance of a MEMS optically differential reconfigurable gate array 査読

Hironobu Morita, Minoru Watanabe

2010 International Conference on Optical MEMS and Nanophotonics, Optical MEMS and Nanophotonics 2010 133 - 134 2010年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

(Figure Presented) This paper presents a four-context MEMS optically differential reconfigurable gate array that is useful in a space radiation environment. The technique enables rapid recovery of a programmable device that has been damaged by high-energy charged particles. It can use incorrect configuration data including some error bits resulting from damage by particles. This paper also clarifies the fault tolerance of the MEMS optically differential reconfigurable gate array. ©2010 IEEE.

DOI： 10.1109/OMEMS.2010.5672149

Dynamically reconfigurable vision-chip architecture 査読

Maki Yasuda, Minoru Watanabe

2010 International Conference on Field Programmable Logic and Applications, FPL 2010 508 - 512 2010年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported. © 2010 IEEE.

DOI： 10.1109/FPL.2010.101

Binary MEMS optically reconfigurable gate array 査読

Hironobu Morita, Minoru Watanabe

Proceedings - 9th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2010 63 - 68 2010年8月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand for high-speed dynamic reconfiguration for programmable devices has increased since such fast dynamic reconfiguration can increase the programmable gate array performance. To meet that demand, optically reconfigurable gate arrays (ORGAs) have been developed to achieve the fast dynamic reconfiguration. Among such studies, a MEMS ORGA has been developed. The reconfiguration can be executed not only by switching a laser array but also by switching a holographic memory. The first proposed MEMS ORGA took an analog fringe pattern for generating a configuration context, although the MEMS device is a binary spatial light modulator. The switching capability can therefore not be fully exploited from a MEMS device since a MEMS device requires PWM control for generating an analog fringe pattern. This paper presents a novel binary MEMS ORGA. The binary MEMS ORGA has achieved a 312 ns laser-reconfiguration and 22 μs holographic memory switching. © 2010 IEEE.

DOI： 10.1109/ICIS.2010.89

Programmable optically reconfigurable gate array using a silver-halide holographic memory 査読

Shinya Kubota, Minoru Watanabe

2010 15TH OPTOELECTRONICS AND COMMUNICATIONS CONFERENCE 370 - 371 2010年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a new programmable optically reconfigurable gate array using a silver-halide non-volatile holographic memory and its writer system. This device achieves high-speed reconfiguration, numerous reconfiguration contexts and user programmability.

Partial block-by-block reconfiguration for a dynamic optically reconfigurable gate array 査読

D. Seto, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 232 - 237 2010年7月

A four-context optically reconfigurable gate array using a laser array attachment 査読

T. Mabuchi, M. Watanabe

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies 143 - 147 2010年6月

Recovery method for a turn-off failure mode of a laser array on an ORGA 査読

Daisaku Seto, Minoru Watanabe

2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010 235 - 240 2010年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand for a large-gate-count robust VLSI chip that is usable in a radiation-rich space environment is increasing daily. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. However, the ORGA has only an unallowable failure mode, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal of a recovery method for a turn-off failure mode of a laser array on an ORGA and presents its demonstration results. © 2010 IEEE.

DOI： 10.1109/AHS.2010.5546252

Acceleration method of optical reconfigurations using analog configuration contexts 査読

Yuji Aoyama, Minoru Watanabe

2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010 304 - 308 2010年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) consisting of a holographic memory, a laser array, and a programmable gate array have been developed to realize large virtual gates and to increase a gate array's performance. To date, all ORGAs used binary values for optically applied configuration contexts. However, the energy efficiency is not good. Therefore, this paper presents a novel acceleration method of optical reconfigurations using analog configuration contexts. © 2010 IEEE.

DOI： 10.1109/AHS.2010.5546242

A 100-context optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS 2884 - 2887 2010年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, optically reconfigurable gate arrays (ORGAs) have been developed to realize large virtual gates and to increase gate array performance by combining a holographic memory with a programmable gate array. Among such studies, a 16-context ORGA architecture with nanosecond-order reconfiguration capability has already been demonstrated. However, its reconfiguration contexts are too few to execute large real-time operations. This paper therefore presents a proposal of a more advanced 100-context ORGA architecture in addition to related experimental results.

DOI： 10.1109/ISCAS.2010.5536965

Configuration power reduction effect of an ORGA with analog configuration contexts 査読

Y. Aoyama, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 189 2010年4月

Power reduction method using negative logic implementation 査読

R. Moriwaki, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 192 2010年4月

MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment 査読

Daisaku Seto, Minoru Watanabe

RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS 5992 134 - 144 2010年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Embedded devices used for spacecraft, satellites, and space stations are vulnerable to the effects of high-energy charged particles. To resolve single-event latch-up (SEL)-associated troubles more flexibly using limited hardware resources in a space environment, reconfigurable devices such as field programmable gate arrays (FPGAs) are suitable. However, such reconfigurable systems present the shortcoming that the circuit itself on the gate array is not robust. The configuration context on a configuration SRAM also suffers from single-event upsets (SEUs) and SELs. This paper therefore proposes an MEMS dynamic optically reconfigurable gate array that is usable under a space radiation environment. The technique enables rapid recovery of a programmable device that has been damaged by high-energy charged particles. It uses incorrect configuration data including some error bits that had been damaged by particles. The configuration data are transferred using wireless communications and are retained on an EEP-ROM/SRAM.

DOI： 10.1007/978-3-642-12133-3_14

Fiber remote configuration for a dynamic optically reconfigurable gate array 査読

Yumiko Ueno, Minoru Watanabe

2010 15TH OPTOELECTRONICS AND COMMUNICATIONS CONFERENCE (OECC) Optoelectronics and Communications Conference 250 - 251 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION & COMMUNICATION ENGINEERS

This paper presents a new remotely reconfigurable gate array, based on a dynamic optically reconfigurable gate array architecture, which is intended for use in systems at nuclear power plants, plants with no personnel, and other systems.

Optical buffering technique under a space radiation environment 査読

Mao Nakajima, Minoru Watanabe

OPTICS LETTERS 34 ( 23 ) 3719 - 3721 2009年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

We propose an optical buffering technique for a programmable gate array under a space radiation environment. The technique allows rapid recovery of a programmable device that is damaged by high-energy charged particles. The technique uses invalid configuration data, including error bits that have already been damaged by the particles, while the configuration data are transferred using wireless communications and are retained on electronically erasable, programmable read-only, or static random-access-memory devices. (C) 2009 Optical Society of America

DOI： 10.1364/OL.34.003719

Formation of volume holographic memory using liquid-crystal composites for optically reconfigurable gate array 査読

A. Ogiwara, Y. Ochi, M. Miyake, M. Watanabe, T. Mabuchi, F. Kobayashi

15th MICROOPTICS CONFERENCE 194 - 195 2009年10月

A Four-Context Optically Differential Reconfigurable Gate Array 査読

Mao Nakajima, Minoru Watanabe

JOURNAL OF LIGHTWAVE TECHNOLOGY 27 ( 20 ) 4460 - 4470 2009年10月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Reconfiguration applications based on reconfigurable devices present new computational paradigms since, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, Optically Reconfigurable Gate Arrays (ORGAs) with a holographic memory were developed. They realize rapid reconfigurations and numerous reconfiguration contexts. Furthermore, Optically Differential Reconfigurable Gate Arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However, fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results demonstrating its fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

DOI： 10.1109/JLT.2009.2024173

Scaling prospect of optically differential reconfigurable gate array VLSIs 査読

Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 60 ( 1-2 ) 137 - 143 2009年8月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SPRINGER

Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 mu m and 0.35 mu m CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.

DOI： 10.1007/s10470-008-9210-9

Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI 査読

Shinichi Kato, Minoru Watanabe

Embedded Computer Systems: Architectures, Modeling, and Simulation 5657 139 - 148 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

To date, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present the advantageous capabilities compared with ORGAs: they have increased reconfiguration frequency per unit of laser power and reduced optical power consumption. Dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density, but an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array that adopts only the good factors from both architectures has been developed. This paper presents an inversion/non-inversion implementation for a fabricated 11,424 gate-count dynamic optically reconfigurable gate array VLSI. Based on that implementation, three factors are discussed: gate density, reconfiguration frequency per unit of laser power, and optical power consumption.

DOI： 10.1007/978-3-642-03138-0_15

A multi-context programmable optically reconfigurable gate array

S. Kubota, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 305 - 306 2009年7月

Defect tolerance of an optically reconfigurable gate array with a one-time writable volume holographic memory 査読

Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara

2009 NASA/ESA Conference on Adaptive Hardware and Systems 106 - 111 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the ORGAs capability of perfectly parallel programmability enables avoidance of those defective areas through alternative use of other non-defective areas. Moreover, a holographic memory to store contexts is known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Consequently, damage of a holographic memory rarely affects its diffraction pattern or a reconfiguration context. For that reason, ORGAs are extremely robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability. This paper presents experimentation related to the defect tolerance of new optically reconfigurable gate array with a one-time easily writable volume holographic memory.

DOI： 10.1109/AHS.2009.62

A sixteen-context dynamic optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

2009 NASA/ESA Conference on Adaptive Hardware and Systems 120 - 125 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on a programmable device. Such dynamic reconfiguration necessitates two important features: fast reconfiguration and numerous contexts. However, because fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DOR-GAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a 16-context DORGA architecture. Furthermore, we present experimental results: 530-833 ns reconfiguration times and 5-9.375 mu s retention times.

DOI： 10.1109/AHS.2009.64

Optically reconfigurable gate array with a one-time writable holographic memory 査読

T. Mabuchi, K. Miyashiro, M. Watanabe, A. Ogiwara

International Conference on engineering of reconfigurable systems and algorithms 307 - 308 2009年7月

Alignment compensation method for an optically reconfigurable gate array 査読

H. Morita, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 332 - 333 2009年7月

A 16-context optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

IEEE International Conference on Application-specific Systems, Architectures and Processors 227 - 230 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.

DOI： 10.1109/ASAP.2009.41

A programmable dynamic optically reconfigurable gate array

Shinya Kubota, Minoru Watanabe

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference 323 - 326 2009年6月

Fast reconfiguration experiments of an optically differential reconfigurable gate array with nine configuration contexts 査読

Mao Nakajima, Minoru Watanabe

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 2013 - 2016 2009年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically differential reconfigurable gate arrays (ODRGAs) have been developed to achieve rapid reconfiguration and numerous reconfiguration contexts. Although fast reconfiguration experiments of a four-context ODRGA have been presented in earlier reports, the number of configuration contexts was insufficient for dynamic reconfiguration applications. Therefore, we have developed a more advanced nine-context ODRGA system. This paper presents fast 86.2 ns reconfiguration experiments using a nine-context ODRGA architecture and discusses plans for future work.

DOI： 10.1109/ISCAS.2009.5118187

A Nine-context Programmable Optically Reconfigurable Gate Array with Semiconductor Lasers 査読

Shinya Kubota, Minoru Watanabe

GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI 269 - 273 2009年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ASSOC COMPUTING MACHINERY

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, compared with current field programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and then implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that daunting problem, this paper presents a nine-context programmable ORGA and its writer. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1145/1531542.1531606

Dynamic optically reconfigurable gate array with high defect tolerance 査読

D. Seto, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 171 171 2009年4月

Power reduction effect of an inversion/non-inversion dynamic optically reconfigurable gate array 査読

S. Kato, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 172 2009年4月

Fast Optical Reconfiguration of a Nine-Context DORGA 査読

Mao Nakajima, Minoru Watanabe

International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science 5453 123 - 132 2009年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a nine-context DORGA architecture. Furthermore, this paper presents experimental results: 1.2-8.97 mu s reconfiguration times and 66-221 mu s retention times.

DOI： 10.1007/978-3-642-00641-8_14

An estimation of an inversion/non-inversion dynamic optically reconfigurable gate array VLSI 査読

S. Kato, M. Watanabe

International Conference on Space Optical Systems and Applications ICSOS2009 - 26 2009年2月

Configuration experiments for an optically reconfigurable gate array with a silver-halide holographic memory 査読

M. Nakajima, M. Watanabe

International Conference on Space Optical Systems and Applications ICSOS2009 - 21 2009年2月

Triple-module redundancy for an optically reconfigurable gate array 査読

D. Seto, M. Watanabe

International Conference on Space Optical Systems and Applications ICSOS2009 - 27 2009年2月

An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture 査読

Daisaku Seto, Minoru Watanabe

2009 Asia and South Pacific Design Automation Conference 117 - 118 2009年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

The world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on the use of junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm(2) and a 0.35 mu m-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper shows an experimental result of a long retention time of its photodiode memory architecture.

DOI： 10.1109/ASPDAC.2009.4796460

Programmable Optically Reconfigurable Gate Array Architecture and its writer 査読

KUBOTA Shinya, WATANABE Minoru

APPLIED OPTICS 48 ( 2 ) 302 - 308 2009年1月

Programmable optically reconfigurable gate array architecture and its writer 査読

Shinya Kubota, Minoru Watanabe

APPLIED OPTICS 48 ( 2 ) 302 - 308 2009年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve huge virtual gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teragate counts will be producible. However, compared with current field programmable gate arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world's first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results. (C) 2009 Optical Society of America

DOI： 10.1364/AO.48.000302

An inversion/non-inversion dynamic optically reconfigurable gate array VLSI 査読

M. Watanabe, M. Nakajima, S. Kato

World Scientific and Engineering Academy and Society Transactions on Circuits and Systems 8 ( 1 ) 11 - 20 2009年1月

Fault tolerance analysis of MEMS holographic memory for DORGAs 査読

Daisaku Seto, Minoru Watanabe

20th Anniversary MHS 2009 and Micro-Nano Global COE - 2009 International Symposium on Micro-NanoMechatronics and Human Science 33 - 37 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on its programmable gate array. Such dynamic reconfiguration is dependent upon two important features: fast reconfiguration and numerous contexts. However, fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically recon-figurable gate arrays (ORGAs) have been developed to resolve this dilemma. Among studies of such devices, this paper presents a demonstration of a dynamic ORGA (DORGA) with a MEMS holographic memory and its fault tolerance analysis results. ©2009 IEEE.

DOI： 10.1109/MHS.2009.5352102

A lens-less imaging holographic memory writer system for a programmable optically reconfigurable gate array 査読

Shinya Kubota, Minoru Watanabe

2009 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ELECTRONIC AND PHOTONIC DEVICES AND SYSTEMS (ELECTRO-2009) 112 - 115 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (OR-GAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, in contrast to current field-programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package and reprogrammed outside of the ORGA package using a holographic memory writer. Then it must be implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that problem, this paper presents a new programmable optically reconfigurable gate array and its lens-less imaging holographic memory writer system. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1109/ELECTRO.2009.5441161

Fault tolerance of a dynamic optically reconfigurable gate array with a one-time writable volume holographic memory 査読

Takayuk Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 917 - + 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have particularly high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the perfectly parallel programmable capability of ORGAs enables perfect avoidance of those defective areas through alternative use of other non-defective areas. Moreover, holographic memories to store contexts are known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. For those reasons, the damage of some part of the device rarely affects its diffraction pattern or a reconfiguration context. Consequently, ORGAs are very robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability. This paper presents experimental results of defect tolerance of a new dynamic optically reconfigurable gate array with a one-time easily writable holographic memory.

DOI： 10.1109/MWSCAS.2009.5235916

A multi-context programmable optically reconfigurable gate array without a beam splitter 査読

Shinya Kubota, Minoru Watanabe

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 971 - 974 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, exploitation of the storage capacity of a holographic memory produces ORGAs with more than tera-gate capacity. However, comparison of conventional ORGAs with current field programmable gate arrays (FPGAs) reveals one important shortcoming: they are not reprogrammable after fabrication: to reprogram an ORGA, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and again implemented onto the ORGA package with high precision beyond the capability of manual assembly. Therefore, to remove that shortcoming, a programmable ORGA has been proposed. However, since previously proposed programmable ORGA configurations used a beam splitter, its alignment was complicated. Furthermore, the alignments of lasers were also limited. This paper presents a multi-context programmable optically reconfigurable gate array that uses no beam splitter. Furthermore, this paper presents discussions of the availability of this architecture and future plans based on experimental results.

DOI： 10.1109/MWSCAS.2009.5235928

MEMS OPTICALLY RECONFIGURABLE GATE ARRAY 査読

Hironobu Morita, Minoru Watanabe

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS 511 - 515 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on its programmable gate array. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the world's first demonstration of an ORGA with micro electro mechanical system's (MEMS) holographic memory.

DOI： 10.1109/FPL.2009.5272445

36-Context dynamic optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

2009 IEEE/SICE International Symposium on System Integration: SI International 2008 - The 2nd Symposium on System Integration 19 - 23 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically reconfigurable gate arrays (ORGAs) have been developed for the purposes of realizing large virtual gates and increasing a gate array's performance by combining a holographic memory with a programmable gate array. In addition, dynamic optically reconfigurable gate arrays (DORGAs) using a photodiode memory architecture have been developed to realize a high-density VLSI. We have already demonstrated a 16-context DORGA architecture with a nanosecond-order reconfiguration capability. This paper presents a more advanced 36-context DORGA with performance that exceeds that of current dynamic reconfigurable devices. ©2009 IEEE.

DOI： 10.1109/SI.2009.5384563

An optical configuration acceleration method using negative logic implementation 査読

Retsu Moriwaki, Minoru Watanabe

2009 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ELECTRONIC AND PHOTONIC DEVICES AND SYSTEMS (ELECTRO-2009) 552 - 555 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers. However, such high-power lasers increase power consumption and package size. In the worst case, they might require a cooling system. For that reason, this paper proposes a negative logic implementation method by which optical configurations can be accelerated without ORGA architecture modification and any increase of laser power. This time, the method was demonstrated on a dynamic optically reconfigurable gate array architecture. Based on the experimental results, this paper clarifies the acceleration method's effectiveness.

DOI： 10.1109/ELECTRO.2009.5441043

Fiber remote configuration for an optically reconfigurable gate array 査読

Yumiko Ueno, Minoru Watanabe

2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009) 460 - 463 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A function enabling remote programming is necessary for systems at nuclear power plants, plants with no personnel, and other systems. Recently, an optically reconfigurable gate array (ORGA) architecture has been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. However, ORGA architectures have never realized a remote programming capability. Therefore, this paper proposes a new remotely reconfigurable gate array architecture that enables remote reconfiguration using optical fiber networks. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1109/SOCDC.2009.5423925

MEMS inversion/non-inversion dynamic optically reconfigurable gate array 査読

Daisaku Seto, Minoru Watanabe

2009 IEEE/SICE International Symposium on System Integration: SI International 2008 - The 2nd Symposium on System Integration 24 - 29 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To date, for large system integrations, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present advantageous capabilities compared with ORGAs: they have increased reconfiguration frequency per unit of laser power and reduced optical power consumption. Dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density. Nevertheless, an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array incorporating only the good attributes from both architectures has been developed. This paper presents a novel inversion/non-inversion ORGA using a rewritable MEMS holographic memory. ©2009 IEEE.

DOI： 10.1109/SI.2009.5384560

MEMS Optically Differential Reconfigurable Gate Array 査読

Hironobu Morita, Minoru Watanabe

2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009) 119 - 122 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demands for fast dynamic reconfiguration for programmable devices have increased because the fast dynamic reconfiguration can increase the number of functions on a gate array. This paper presents a proposal of a novel optically differential reconfigurable gate array architecture with a microelectromechanical system (MEMS) mirror array that enables high-speed reconfiguration by exploiting large-bandwidth optical connections between the MEMS mirror array and a programmable gate array. The MEMS mirror array is used as a holographic memory. Four configuration contexts can be programmed electrically and dynamically onto the MEMS mirror array as holographic memory information. A configuration procedure is executed by switching of both a laser array and a MEMS mirror array. This experiment has demonstrated a four-context 9 ns microelectromechanical reconfiguration for a programmable gate array.

DOI： 10.1109/EDSSC.2009.5394174

A 36-context optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009) 412 - 415 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Fast reconfiguration and numerous reconfiguration contexts are two important features of dynamically reconfigurable devices. However, realizing both is difficult in current dynamically reconfigurable devices. Therefore, optically reconfigurable gate arrays (ORGAs) have been under development to solve this problem. Actually, ORGAs can realize a large virtual gate count over current VLSIs by combining a holographic memory storing numerous reconfiguration contexts with an optically reconfigurable gate array VLSI. To date, a 16-configuration-context ORGA has been developed. This paper presents a more advanced demonstration of a 36-configuration-context ORGA architecture, which is larger than the number of reconfiguration contexts of current dynamically reconfigurable devices. The 36-configuration-context ORGA architecture achieved 52 ns - 1.65 mu s fast reconfiguration. In addition, this paper presents a discussion of some technical issues for increasing the number of configuration contexts of a multi-context ORGA and future vision, based on results of several experiments.

DOI： 10.1109/SOCDC.2009.5423866

A 13.75 ns holographic reconfiguration of an optically differential reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing 852 - 855 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Reconfiguration applications based on reconfigurable devices present new computational paradigms because increasing the reconfiguration frequency of such devices can enhance their activity and performance dramatically. Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory were developed, achieving important new advances in the areas of rapid reconfiguration and numerous reconfiguration contexts. Furthermore, optically differential reconfigurable gate arrays have been developed to accelerate optical reconfigurations of conventional ORGAs. This paper presents experimental results of the fastest 13.75 ns holographic reconfiguration of an optically differential reconfigurable gate array, along with discussion of the advantages of optically differential reconfigurable gate array architecture. © 2009 IEEE.

DOI： 10.1109/IIH-MSP.2009.250

Allowable alignment errors of components in an optically reconfigurable gate array 査読

H. Morita, M. Watanabe

International Topical Meeting on Information Photonics 50 - 51 2008年11月

Multi-speed configuration for ORGAs 査読

M. Nakajima, M. Watanabe

International Topical Meeting on Information Photonics 166 - 167 2008年11月

Liquid crystal holographic configurations for ORGAs 査読

YAMAGUCHI Naoki, WATANABE Minoru

APPLIED OPTICS 47 ( 26 ) 4692 - 4700 2008年10月

Liquid crystal holographic configurations for optically reconfigurable gate arrays 査読

Naoki Yamaguchi, Minoru Watanabe

APPLIED OPTICS 47 ( 26 ) 4692 - 4700 2008年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

An optically reconfigurable gate array (ORGA) system, which consists of an ORGA very large scale integration (VLSI), an easily rewritable liquid crystal holographic memory recording four configuration contexts, and a laser array, is proposed. Circuits on a gate array of the ORGA-VLSI can be programmed rapidly by exploiting large parallel connections between a holographic memory and a gate array VLSI; that programming can be executed even as it is being programmed. Consequently, the gate array can be switched from a certain circuit to another circuit instantaneously. We present a demonstration of the ORGA system and experimental results. (C) 2008 Optical Society of America

Optical configuration using a silver-halide holographic memory including four configuration contexts 査読

D. Seto, M. Watanabe

International Conference on Solid State Devices and Materials 116 - 117 2008年9月

A 770ns holographic reconfiguration of a four-context DORGA 査読

M. Nakajima, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 289 - 292 2008年7月

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration ? a 6502 Perspective- 査読

F. Kobayashi, Y. Morikawa, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 222 - 228 2008年7月

A dynamic optically reconfigurable gate array - Perfect emulation 査読

Daisaku Seto, Minoru Watanabe

IEEE JOURNAL OF QUANTUM ELECTRONICS 44 ( 5-6 ) 493 - 500 2008年5月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.

DOI： 10.1109/JQE.2008.916705

Multi-optical configuration using spreading beams 査読

Naoki Yamaguchi, Minoru Watanabe

2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 386 - 389 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. For the laser diode array, a conventional ORGA always required collimated beams, necessitating the use of some lenses and its accurate alignment. Therefore, this paper presents the very compact and simple architecture of a multi-context ORGA that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results of implementation of two configuration contexts and their reconfigurations, in addition to plans for future work.

DOI： 10.1109/MWSCAS.2008.4616817

A 937.5 ns multi-context holographic configuration with a 30-75 mu s retention time 査読

Mao Nakajima, Daisaku Seto, Minoru Watanabe

2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8 3502 - 3507 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However in ORGAs, although a large virtual gate count can be realized by exploiting the large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is still important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However to date, although only a 1.83-1.89 ms single-context holographic configuration and a retention time of 3.495.61 s of DORGA architecture have been confirmed, the performance at nanosecond-scale reconfiguration with a multi-context DORGA architecture has never been analyzed. Therefore, this paper presents the experimental result of a 937.5 ns multi-context holographic configuration and a 30.75 mu s retention time of DORGA architecture. The advantages of this architecture are discussed in relation to the results of this study.

DOI： 10.1109/IPDPS.2008.4536539

Dynamic holographic reconfiguration on a four-context ODRGA 査読

Mao Nakajima, Minoru Watanabe

2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS 173 - 178 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Reconfiguration applications based on reconfigurable devices present new computational paradigms because, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory have been developed to realize rapid reconfigurations and numerous reconfiguration contexts. In addition, optically differential reconfigurable gate arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results that elucidate aspects of fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

DOI： 10.1109/ASAP.2008.4580174

Inversion/non-inversion dynamic optically reconfigurable gate array 査読

Minoru Watanabe, Mao Nakajima

PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS 249 - + 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：WORLD SCIENTIFIC AND ENGINEERING ACAD AND SOC

Up to now, an optically differential reconfigurable gate array taking a differential reconfiguration strategy and a dynamic optically reconfigurable gate array taking a photodiode memory architecture have been proposed. The differential reconfiguration strategy can increase the reconfiguration frequency, with no increase in laser power, compared to other optically reconfigurable gate arrays, but the differential reconfiguration strategy can not achieve a high gate count VLSI because of the area occupied by static configuration memory. On the other hand, the dynamic optically reconfigurable gate array can achieve a high-gate count VLSI, but its configuration speed is slower than that of the optically differential reconfigurable gate array using equivalent laser power. Therefore, to realize both advantages of rapid configuration and a high gate count, this paper presents a novel inversion/non-inversion dynamic optically reconfigurable gate array that combines both architectures. In this study, the effectiveness of the inversion/non-inversion optical configuration method is clarified through some experiments.

Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI 査読

Shinichi Kato, Minoru Watanabe

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY 377 - 380 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a novel inversion / non-inversion zero-overhead dynamic optically reconfigurable gate array that can extract good factors from architectures of both optically differential reconfigurable gate arrays and dynamic optically reconfigurable gate arrays. A full VLSI design using a 0.35 mu m CMOS process technology is presented. Based on that presentation, three factors are discussed: gate density; reconfiguration frequency per unit of laser power, optical power consumption.

DOI： 10.1109/FPT.2008.4762422

An 11,424-gate dynamic optically reconfigurable gate array VLSI 査読

Mao Nakajima, Minoru Watanabe

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY 293 - 296 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A DORGA architecture has been proposed to increase gate density It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the world's largest 11,424 gate-count dynamic optically reconfigurable gale array (DORGA) VLSI fabricated on a 96.04 mm(2) chip using a 0.35 mu m three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture arc, discussed in relation to the results described herein.

An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays 査読

Takayuki Mabuchi, Minoru Watanabe

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY 289 - 292 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

In previously proposed ORGAs, the optical reconfiguration period was designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory differs depending on the number of bright bits included in a configuration context. Therefore, previous ORGAs can not fully exploit reconfiguration performance. For that reason, this paper presents a proposal for an analog reconfiguration-period adjustment technique for ORGAs to reduce each reconfiguration period. The advantages are then discussed herein based on experimental results obtained using an ORGA system on which the technique is adopted.

DOI： 10.1109/FPT.2008.4762400

An acceleration and optimization method for optical reconfiguration 査読

Minoru Watanabe, Naoki Yamaguchi

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS 607 - 612 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.

DOI： 10.1109/VLSI.2008.26

A dynamic optically reconfigurable gate array with a silver-halide holographic memory 査読

Daisaku Seto, Minoru Watanabe

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008 511 - 514 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To increase gate density, a dynamic optically reconfig-urable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted, thereby demonstrating its availability. However, because the resolution of the liquid crystal holographic memory is very low and because the storable configuration contexts are numerically limited to four, that estimation cannot be considered a practical experiment. Therefore, this paper presents a practical demonstration of the DORGA architecture using a silver-halide holographic memory that can store over 3,000 configuration contexts. The DORGA architecture performance, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study. ©2008 IEEE.

DOI： 10.1109/ISVLSI.2008.94

Defect tolerance of holographic configurations in ORGAs 査読

Kouji Shinohara, Minoru Watanabe

2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8 3488 - 3495 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the perfectly parallel programmable capability of ORGAs enables perfect avoidance of those defective areas through alternative use of other non-defective areas. Moreover holographic memories to store contexts are known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Moreover the damage of some fraction rarely affects its diffraction pattern or a reconfiguration context. Therefore, ORGAs are very robust against component defects in devices such as laser arrays, gate arrays, and holographic memory, and are particularly useful for space applications, which require high reliability. However, to date, the degree to which defects in a holographic memory affects holographic configurations has never been analyzed. Therefore, this paper describes analysis results of defect limitations of holographic configurations.

DOI： 10.1109/IPDPS.2008.4536537

An optical reconfiguration system with four contexts 査読

Naoki Yamaguchi, Minoru Watanabe

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS 601 - 606 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. It is noteworthy that ORGA-VLSIs which can be reconfigured in nanoseconds without any overhead have already been fabricated. However to date, no multiholographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has ever been developed. As the first step toward realizing such a device, a four-context optical system is demonstrated experimentally using a liquid crystal spatial light modulator and a He-Ne laser This paper describes those experimental results and plans for future work.

DOI： 10.1109/VLSI.2008.27

Programmable Optically Reconfigurable Gate Array Architecture using a PAL-SLM 査読

Shinya Kubota, Minoru Watanabe

2008 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION 100 - 104 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve huge virtual gate counts that is much larger than those of currently available VLSIs. Using ORGA architecture, greater than 1 tera gate count VLSIs are possible by exploiting the storage capacity of a holographic memory. Conventional ORGAs have only one shortcoming compared with current field programmable gate arrays (FPGAs) : they are not reprogrammable after their fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and implemented into the ORGA package with high precision beyond that available by manual assembly. To improve that shortcoming, this paper presents the world's first programmable ORGA architecture and experimental results. Furthermore, in light of those experimental results, this paper presents discussion of the availability of this architecture and future plans.

DOI： 10.1109/SI.2008.4770434

Optical configuration of an 11,424 gate-count dynamic optically reconfigurable gate array using a VCSEL 査読

Daisaku Seto, Minoru Watanabe

2008 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION 95 - 99 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Recently, to realize large real-time systems, demands for fast computation on large VLSI have continued to increase. An optically reconfigurable gate array has been developed to realize large virtual gates. As part of that research effort, the world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on a concept using junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm(2) and a 0.35 mu m-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper presents an experimental result of along retention time of its photodiode memory architecture.

DOI： 10.1109/SI.2008.4770433

Analysis of retention time under multi-configuration on a DORGA 査読

Daisaku Seto, Minoru Watanabe

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 131 - 134 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, dynamic optically reconfigurable architecture has been proposed to increase the gate count of the ORGA-VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memories. Consequently, extremely high gate count ORGAs have been realized. However, in this architecture, since background diffraction light of configuration contexts reduces the retention time of circuit information stored in junction capacitances of photodiodes, it has remained a concern that under multi-configuration, an optical configuration can reduce the retention time of other circuits that have already been programmed before the configuration and are functioning on a gate array. This paper clarifies that the dynamic optically reconfigurable architecture is effective even under multi-configuration.

DOI： 10.1109/SOCC.2008.4641495

A 9-context Optically Reconfigurable Gate Array 査読

Takayuki Mabuchi, Minoru Watanabe

ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 1 - 4 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. Up to now, four-context ORGAs have been demonstrated. This paper presents the first 9-context ORGA architecture that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results and plans for future work.

DOI： 10.1109/SOCDC.2008.4815560

A double or triple module redundancy model exploiting dynamic reconfigurations 査読

Kouji Shinohara, Minoru Watanabe

PROCEEDINGS OF THE 2008 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS 114 - 121 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Majority voting is a commonly used approach to increase system reliability. Standard triple-module-redundancy (TMR) methods are frequently used in space applications. Using these methods, triple modules and voting circuits are implemented onto an Application Specific Integrated Circuit (ASIC) or an FPGA. When a single event upset occurs, the voting circuit neglects the failure value of a module receiving the single event upset and takes a correct value of the other two modules not receiving it. However, the triple-module implementation requires a large implementation area on VLSIs. Therefore, to reduce the area of TMR implementation, this paper presents a novel double or triple module redundancy (DTMR) method for dynamically reconfigurable devices using a design example of a state machine. Furthermore, this paper presents experimental results of the method using a highly reliable optically reconfigurable gate array.

DOI： 10.1109/AHS.2008.67

Optimization of reconfiguration speed control bits for an Optically Reconfigurable Gate Array 査読

M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 2007年7月

272 gate count optically differential reconfigurable gate array VLSI 査読

M. Watanabe, T. Shiki, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 2007年7月

Power Consumption Reduction Method of Dynamic Optically Reconfigurable Gate Array VLSIs 査読

M. Watanabe, F. Kobayashi

IEEE Symposium on Low-Power and High-Speed Chips 145 2007年4月

Superimposing technique of reconfiguration contexts 査読

M. Watanabe, F. Kobayashi

ACM/SIGDA International Symposium on Field Programmable Gate Arrays 227 - 228 2007年2月

時間領域フーリエ補間による非同期サンプリング・レート・コンバータ, 査読

井上,小林, 渡邊実

計測自動制御学会論文集 43 ( 2 ) 145 - 152 2007年2月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：The Society of Instrument and Control Engineers

A time-domain SRC, sampling rate converter, using Fourier interpolation to achieve less gate count than in frequency domain is proposed. The new SRC is implemented in 1/150 of the circuit size of conventional SRC with moderate performance using filters. It can also be used as back-end for filter-type SRC to achieve high performance efficiently.

DOI： 10.9746/ve.sicetr1965.43.145

Superimposing technique of reconfiguration contexts for increasing reconfiguration speed 査読

M. Watanabe, F. Kobayashi

Mobile Computing Hardware Architectures Design Symposium 2007年1月

Reconfiguration performance analysis of a dynamic optically reconfieurable gate array architecture 査読

Daisaku Seto, Minoru Watanabe

ICFPT 2007: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS 265 - 268 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

DOI： 10.1109/FPT.2007.4439262

Reconfigurations of a dynamic optically reconfigurable architecture under a constant laser exposure 査読

Minoru Watanabe, Daisaku Seto

EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS 405 - 408 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, we have proposed a dynamic optically reconfigurable architecture for ORGAs to increase the gate count of the VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memory. In this architecture, suitable laser exposure time for each implementation circuit is different from each other. Nevertheless, the laser exposure time is always designed as a constant to simplify its optical reconfiguration architecture and procedure. So, the affect for retention time of implementation circuits under such the condition was concerned, however, which has never been analyzed. Therefore, this paper experimentally presents that the dynamic optically reconfigurable architecture is available under a constant laser exposure condition.

DOI： 10.1109/EDSSC.2007.4450148

A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays 査読

Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically Reconfigurable Gate Arrays (ORGAs) offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSIs by exploiting the large storage capacity of a holographic memory. The first ORGA was developed to achieve rapid reconfiguration and a number of reconfiguration contexts
it consisted of a gate array VLSI, a holographic memory, and a laser diode array. The ORGA achieved a 16 μs to 20 μs reconfiguration period that was faster than that of FPGAs, with 100 reconfiguration contexts. However, the ORGA requires the gate array to halt during reconfiguration. Therefore, the ORGA can not be reconfigured frequently because of the associated reconfiguration overhead. On the other hand, new ORGA-VLSIs that have less than 10 ns reconfiguration capability without any related overhead have already been fabricated. However, to date, a multi-holographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has never been developed. For such realization, this paper proposes a four-context ORGA architecture and a multi-context holographic memory recording system used for it. In addition, experimentally demonstrated results of recording a holographic memory and reconfiguring an ORGA-VLSI are described. © 2007 IEEE.

DOI： 10.1109/IPDPS.2007.370391

Holographic memory reconfigurable VLSI 査読

Minoru Watanabe, Fuminori Kobayashi

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 401 - 404 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration for numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed by a laser diode array. It is noteworthy that ORGA-VLSIs that can be reconfigured in less than 10 ns without any overhead have already been fabricated. However, up to now, a multi-holographic reconfiguration system that is suitable for such fast-reconfigurable ORGA-NLSIs without any overhead has never been developed. As the first step toward such realization, a multi-context component is demonstrated experimentally using a liquid crystal spatial light modulator and a pulse laser This paper describes experimental results and plans for future work.

DOI： 10.1109/ISCAS.2007.378474

Optically differential reconfigurable gate array 査読

Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 90 ( 11 ) 132 - 139 2007年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SCRIPTA TECHNICA-JOHN WILEY & SONS

Recent years have seen the development of optically reconfigurable gate arrays, which can be reconfigured using light at high speeds that cannot be implemented with electrical wiring. However, optically reconfigurable gate arrays have reconfiguration speeds of 16 to 20 mu s, which is fast compared to FPGAs (Field Programmable Gate Arrays), but high-speed reconfiguration, approaching the operating clock of a mounted circuit, has not been implemented. Also, partial reconfiguration, which is indispensable for frequent dynamic reconfiguration, has not been considered. The authors propose an Optically Differential Reconfigurable Gate Array (ODRGA), which can be reconfigured at high speeds close to the operating clock of a mounted circuit and which allows partial reconfiguration of any zone in bit units. This paper includes an overview of ODRGA and introduces the optically differential reconfigurable architecture, with which arbitrary, partial reconfiguration is possible, as well as the optically reconfigurable architecture enabling highspeed optical reconfiguration. Then, it is demonstrated that high-speed optical reconfiguration at 200 ns, the world's fastest system-level optical reconfiguration, is possible with an optical system using a pulse laser diode wherein nanosecond optical reconfiguration is possible with a prototype stand-alone VLSI chip. Finally, it is made clear that, in the future, improvement to the optical components will make possible nanosecond high-speed optical reconfiguration at the system level as well. (C) 2007 Wiley Periodicals, Inc.

DOI： 10.1002/ecjb.20420

DORGA holographic memory architecture 査読

Minoru Watanabe, Shoutarou Fukagawa, Fuminori Kobayashi

2007 INTERNATIONAL CONFERENCE ON MICROELECTRONICS 222 - + 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However, in ORGAs, although a large virtual gate count can be realized by exploiting a large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is stilt important to increase the instantaneous performance. In previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context occupied a large implementation area of the ORGA-VLSIs and thereby prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture was proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. This paper presents a perfect DORGA architecture including a holographic memory. The performance of the DORGA architecture, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed relative to the results of this study.

DOI： 10.1109/ICM.2007.4497743

Scaling rule of optically differential reconfigurable gate array VLSIs 査読

Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 101 - 104 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically merely by increasing the reconfiguration frequency. Therefore, the reconfiguration time and reconfiguration overhead of next-generation programmable devices are extremely important parameters. To realize zero-overhead and short reconfiguration, an Optically Differential Reconfigurable Gate Array (ODRGA) VLSIs were developed. However, up to now, the scaling rule of ODRGAs has never been clarified. This paper describes the designs of ODRGA-VLSIs using 0.18 mu m and 0.35 mu m CMOS processes and presents discussion of the scaling rule of ODRGAs using layout results.

DOI： 10.1109/MWSCAS.2007.4488553

A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

ICFPT 2007: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS 297 - 300 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, holographic configuration speeds have remained limited to 16 mu s because of issues related to the architecture of optically reconfigurable gate array VLSIs (ORGA-VLSIs). Therefore, to improve the issue, optically differential reconfigurable gate array VLSIs (ODRGA-VLSIs) have been developed and have achieved zero-overhead and nanosecond optical reconfiguration. Moreover the architecture of an ODRGA-VLSI has the advantage of accelerating the reconfiguration speed compared to that of other ORGAs. However, nanosecond holographic configurations and, in particular rapid holographic reconfiguration exploiting the advantages of ODRGA-VLSIs have not been reported. Therefore, this paper presents results of the world's fastest 62.5 ns holographic reconfiguration, exploiting advantages of the ODRGA-VLSI.

DOI： 10.1109/FPT.2007.4439270

An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI 査読

Minoru Watanabe

20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 75 - 78 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world's largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm(2) chip using 0.35 mu m-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time.

DOI： 10.1109/SOCC.2007.4545430

A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI 査読

Minoru Watanabe, Fuminori Kobayashi

PROCEEDINGS OF THE ASP-DAC 2007 124 - + 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 mu m - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

DOI： 10.1109/ASPDAC.2007.357972

Manufacturing-defect tolerance analysis of optically reconfigurable gate arrays, 査読

M. Watanabe, F. Kobayashi

World Scientific and Engineering Academy and Society Transactions on Signal Processing 11 ( 2 ) 1457 - 1464 2006年11月

位相補間によるPLLの特性改善査読

井上,小林, 渡邊実

計測自動制御学会論文集 42 ( 10 ) 1175 - 1180 2006年10月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：The Society of Instrument and Control Engineers

Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propose a new PLL using phase interpolation based on a counter with a high-frequency internal clock. The PLL can compare phases more than once a cycle of reference and input, thus reducing jitter and improving responsiveness. Also we optimize implementation of phase interpolation, to improve circuit size and maximum operating frequency, even if the circuit compares phases many time a cycle.

DOI： 10.9746/sicetr1965.42.1175

A logic synthesis and place and route environment for ORGAs 査読

M. Watanabe, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 237 - 238 2006年7月

高密度ダイナミック光再構成型ゲートアレーVLSI 査読

渡邊実, 小林

電子情報通信学会論文誌 J89-D ( 6 ) 1082 - 1090 2006年6月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：社団法人電子情報通信学会

近年,光による広いバンド幅を利用することで電気配線では実現できない高速な書込みと,光メモリにより大容量のコンテクストが実現可能なプログラマブル・ゲートアレー,光再構成型ゲートアレーの研究が進められている.しかし,これまでの光再構成型ゲートアレーでは,回路情報が静的なメモリ上に記憶されており,このメモリの実装部がゲートアレー部を圧迫し,光再構成型ゲートアレーの高密度化を妨げていた.そこで,回路情報を保持する静的なメモリを全廃し,受光に用いるフォトダイオードの接合容量をメモリとしても使用する新しいダイナミック光再構成型ゲートアレーが提案された.本論文では,まず,0.35μm-3層メタルのプロセスを使用したダイナミック光再構成型ゲートアレー試作チップの評価結果を示す.そして,同じプロセスを使用することで,14.2mm角チップに26,350ゲート規模の光再構成型ゲートアレーが実現可能であることを示すと同時に,この基本デザインを用いて従来の静的メモリ機能をもつ光再構成型ゲートアレーと比較した実装密度の改善率を明らかにする.

その他リンク： http://hdl.handle.net/10228/4570

Shield effect analysis for a gate array on an Optically Reconfigurable Gate Array 査読

M. Watanabe, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 239 - 240 2006年6月

Differential Reconfiguration Architecture suitable for a Holographic Memory 査読

M. Watanabe, M. Miyano, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 198 - 203 2006年6月

Dynamic optically reconfigurable gate array 査読

M Watanabe, F Kobayashi

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 ( 4B ) 3510 - 3515 2006年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：INST PURE APPLIED PHYSICS

Optically reconfigurable gate arrays (ORGAs) can readily enable both fast reconfiguration and numerous reconfiguration contexts using an optical holographic memory and optical wide-band reconfiguration connections. Such devices present the possibility of large virtual gate-count very large scale integrations (VLSIs). However, the real gate-count of the VLSI part of the devices is too small-only 80. Moreover, the reconfiguration speed is not sufficiently fast: 16 to 20 mu s. For those reasons, this paper clarifies the architecture issues and presents a new architecture of a dynamic optically reconfigurable gate array (DORGA) to improve them. In addition, a comparison is made of results obtained using the previously proposed devices and DORGAs under the same environment. Finally, this paper presents a new design of a 51,272-gate-count DORGA with the new architecture.

DOI： 10.1143/JJAP.45.3510

A 1,632 gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI 査読

Minoru Watanabe, Fuminori Kobayashi

RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS 3985 268 - 273 2006年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SPRINGER-VERLAG BERLIN

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize a single instruction set computer that requires zero-overhead fast reconfiguration. To date, although the concept and architecture have been proposed and some simulation results of designs have been presented, a ZO-ORGA VLSI chip has never been fabricated. In this paper, the first 1,632 gate-count zero-overhead VLSI chip fabricated using 0.35 um CMOS process technology is presented. The 1,632 ZO-DORGA-VLSI is not only the first prototype VLSI chip; it is also the largest gate-count ORGA. Such a large gate count ORGA had never been fabricated until this study. The performance of ZO-DORGA-VLSI is clarified and discussed using experimental results.

Hybrid sample rate converter with 110dB SNR and 1/10 less logic gates 査読

Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe

2006 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY 432 - 436 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An SRC, sampling rate converter, consisting of conventional filter-type SRC and time-domain SRC using Fourier interpolation algorithm is proposed. Filter portion realizes over-sampling, and its output is interpolated by the Fourier portion. The SRC achieves noise level of as low as -110dB for all frequencies, and its gate count is about 1000000 FPGA logic cells.

DOI： 10.1109/EIT.2006.252121

Reconfiguration speed adjustment technique for ORGAs with a holographic memory 査読

Minoru Watanabe, Fuminori Kobayashi

2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS 917 - 922 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array. The gate array of ORGAs is optically reconfigured using diffraction patterns from a holographic memory that is addressed by a laser diode array. In previously proposed ORGAs, the optical reconfiguration speed has been designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory varies depending on the pattern of reconfiguration contexts that is recorded in it. Therefore, this paper proposes a reconfiguration speed adjustment technique for ORGAs to accelerate the reconfiguration speed. In addition, the advantages are discussed from some simulation results of a holographic memory and the experimental results of a fabricated gate array VLSI.

DOI： 10.1109/FPL.2006.311344

An optically differential reconfigurable gate array with a holographic memory 査読

Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi

20th International Parallel and Distributed Processing Symposium, IPDPS 2006 2006 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Optically Reconfigurable Gate Arrays (ORGAs) offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSIs by exploiting the large storage capacity of holographic memory. We developed an Optically Differential Reconfigurable Gate Array (ODRGA-VLSI) with no overhead and fast reconfiguration capability. This paper presents the results of development of a perfect optical reconfigurable system with the ODRGA-VLSI chip and holographic memory. Experimental results of the reconfiguration procedure and circuit performance on a gate array are also presented. © 2006 IEEE.

DOI： 10.1109/IPDPS.2006.1639478

Power consumption advantage of a dynamic optically reconfigurable gate array 査読

Minoru Watanabe, Fuminori Kobayashi

20th International Parallel and Distributed Processing Symposium, IPDPS 2006 2006 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Optically reconfigurable gate arrays (ORGAs) are a type of field programmable gate array (FPGA). However, unlike FPGAs, an ORGA can quickly be reconfigured optically using external optical memories and optical connections. Recently, various types of ORGAs have been developed. However, their gate counts were not satisfactory compared with those of FPGAs. Therefore, to improve the gate density of conventional ORGAs, a dynamic ORGA (DORGA) architecture that can remove static memory functions to store a configuration context has been proposed. The DORGA architecture offers not only the advantages of a high gate count, but also the advantage of low reconfiguration power consumption. To date, its power consumption has never been clarified. For that reason, this paper presents measurement results of the optical reconfiguration power consumption of a DORGA-VLSI chip. In addition, the power consumption advantages of the DORGA architecture are clarified through comparison with other ORGAs. © 2006 IEEE.

DOI： 10.1109/IPDPS.2006.1639490

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 mu m CMOS technology 査読

Minoru Watanabe, Fuminori Kobayashi

ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 108 - + 2006年

Optically Reconfigurable Gate Arrays vs. ASICs 査読

Minoru Watanabe, Fuminori Kobayashi

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 1164 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Reconfigurable Gate Array (ORGA) is a type of Field Programmable Gate Array (FPGA) that can be reconfigured optically in a very short time and with many reconfiguration contexts by combining a holographic memory and a laser array on a gate-array VLSI. An ORGA can be considered as a type of next-generation three-dimensional (31)) VLSI chip. The developments of high-gate count ORGA-VLSIs, optical reconfiguration systems with a holographic memory, and laser arrays have been advanced recently. However, ORGA performance has never been discussed in comparison with current Application Specific Integrated Circuits (ASICs) or full custom VLSIs. In this paper, the performance difference between ORGAs and ASICs is clarified; the future vision of the ORGA is also discussed.

DOI： 10.1109/APCCAS.2006.342348

A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays 査読

Minoru Watanabe, Ryuji Fujime, Fuminori Kobayashi

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II 94 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Differential Reconfigurable Gate Array VLSI (ODRGA-VLSI) presents the advantage that it can be reconfigured more rapidly than other optically reconfigurable gate arrays (ORGAs). In an ORGA, reconfiguration contexts are stored in a holographic memory, which is addressed by a laser array, and read as light. The reconfiguration speed is proportional to the light intensity received in each photodiode on an ORGA-VLSI. In addition, the light intensity from a holographic memory is inversely proportional to the number of its lighting bits corresponding to bits of '1' from the diffraction characteristic of a holographic memory. Therefore, the bit-by-bit programmability of ODRGA-VLSI allows more rapid reconfiguration than for other ORGAs because the light power can be focused onto a reprogrammed area instead of a much larger area. However, the reconfiguration circuit to support bit-by-bit reconfiguration occupies a large implementation area of an ODRGA-VLSI chip. Therefore, a new dynamic reconfiguration circuit has been introduced into ODRGA-VLSIs to reduce the implementation area to realize a high gate-count ODRGA-VLSI. In this paper, the VLSI implementation of the dynamic reconfiguration circuit is shown using 0.35 mu m CMOS process technology; a comparison to results from other optical reconfiguration circuits is presented.

DOI： 10.1109/MWSCAS.2006.382216

Over-sampling PLL for low-jitter and responsive clock synchronization 査読

Manabu Inoue, Furninori Kobayashi, Minoru Watanabe

2006 INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES,VOLS 1-3 809 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Phase Locked Loops (PLLs) are widely used in communication and required to provide low-jitter and fast frequency/phase locking capabilities. For improving these capabilities of PLL, an over-sampling phase detector (PD) using phase interpolation based on a counter with a high-frequency internal clock is proposed. PLL using normal PD compares phases of reference or input signal with its output at the time of their positive transition, but this PLL using over-sampling PD can compare phases more than once a cycle of reference. Thus, the PLL features less jitter than PLL using normal PD, and improved responsiveness. Also we optimized implementation of phase interpolation, to improve maximum operating frequency and circuit size. Experimental results including two jitter characteristics, vital in communication, are shown.

DOI： 10.1109/ISCIT.2006.339842

A 51,272-gate-count Dynamic Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology 査読

M. Watanabe, F. Kobayashi

International Conference on Solid State Devices and Materials, 336 - 337 2005年9月

Fourier/Filter Hybrid Sampling Rate Converter 査読

M. Inoue, F. Kobayashi, M. Watanabe

SICE Annual Conference 176 - 179 2005年8月

A dynamic optically reconfigurable gate array using dynamic method 査読

M. Watanabe, F. Kobayashi

International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science 50 - 58 2005年2月

An Optically Differential Reconfigurable Gate Array VLSI chip with a dynamic reconfiguration circuit 査読

Minoru Watanabe, Fuminori Kobayashi

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 2005 145 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

An Optically Differential Reconfigurable Gate Array (ODRGA) is a type of Field Programmable Gate Array (FPGA), but its gate array can be reconfigured optically in less than 6 ns. We have fabricated a 68 gate-count ODRGA. However, optical differential reconfiguration circuits, which are capable of optical detection of configuration contexts and which can support reconfiguration of an arbitrary part of its gate array bit-by-bit, occupy up to 47% of the implementation area of ODRGA-VLSI chip and prevent realization of a high gate-count ODRGA. Therefore, a dynamic optical differential reconfiguration circuit was developed to reduce the implementation area of optical reconfiguration circuits. It has been evaluated separately. This paper presents the first 476 gate count ODRGA-VLSI chip with a standard 0.35 μm 3-metal CMOS process technology using an improved dynamic optical differential reconfiguration circuit. In addition, the dynamic reconfiguration frequency and performance of logic blocks are shown using HSPICE simulation results. Finally, this paper presents an estimation of the use of a standard 0.35 μm 3-metal 14.2 × 14.2 mm chip.

DOI： 10.1109/IPDPS.2005.105

A 16,000-gate-count optically reconfigurable gate array in a standard 0.35 mu m CMOS technology 査読

M Watanabe, F Kobayashi

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 1214 - 1217 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Up to now, we have fabricated 68-gate-count Optically Reconfigurable Gate Arrays (ORGAs), the reconfiguration period of which has been confirmed as less than 10 us. As the next step, we have begun development of high-gate-count ORGAs. The new ORGA-VLSI chip can achieve a 16,000-gate-count through reduction of photodiode size, photodiode spacing, and through introduction of a small optical reconfiguration circuit, that do not exceed the resolution of available optical components. This paper presents the new design of a 16,000-gate-count ORGA using a standard 0.35 mu m 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip and an evaluation of optical reconfiguration circuits using HSPICE simulation.

DOI： 10.1109/ISCAS.2005.1464812

A zero-overhead dynamic optically reconfigurable gate array 査読

M Watanabe, F Kobayashi

FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS 297 - 298 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a zero-overhead Dynamic Optically Reconfigurable Gate Array (DORGA) that uses the load capacitance of gates to construct a gate array to maintain its state during optical reconfiguration, and uses junction capacitance of photodiodes as configuration memory. It improves a reconfiguration overhead problem of the previously proposed DORGA. The reconfiguration procedure is executable without the overhead of optical reconfiguration by reducing the dispersion delay between optical reconfiguration circuits. This paper presents the design of 1,632 gate count zero-overhead DORGAs reduced the dispersion delay using a standard 0.35 mu m three-metal CMOS process technology.

DOI： 10.1109/FPT.2005.1568569

An improved dynamic optically reconfigurable gate array 査読

M Watanabe, F Kobayashi

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 136 - 141 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

To date, we have proposed Dynamic Optically Reconfigurable Gate Arrays (DORGAs), the implemented photodiodes of which serve not only as receivers but also as memory. DORGA offers the merit of easily providing a high gate count optically reconfigurable gate array (ORGA) because each reconfiguration circuit consists of only a photodiode and a refresh transistor However even though the fast reconfiguration capability has been confirmed as less than 6 ns, such systems have a demerit: their gate arrays can not function during reconfiguration. Consequently, reconfiguration and operation of the implemented circuit on a gate array can not be executed in parallel. Because of that fact, the dynamical reconfiguration frequency of DORGA is slow compared to those of ORGAs with latches, flip-flops, or memory. For that reason, this paper proposes a new optical reconfiguration architecture. Using it, the reconfiguration and implemented circuit operation on a gate array are executable in parallel merely by adding a pass transistor The new design of a 476-gate-count improved DORGA using a standard 0. 35 mu m three-metal CMOS process technology is also shown.

DOI： 10.1109/ISVLSI.2005.16

A 16,000-gate-count Optically Reconfigurable Gate Array in a standard 0.35μm CMOS technology 査読

Minoru Watanabe, Fuminori Kobayashi

Proceedings - IEEE International Symposium on Circuits and Systems 1213 - 1217 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Up to now, we have fabricated 68-gate-count Optically Reconfigurable Gate Arrays (ORGAs), the reconfiguration period of which has been confirmed as less than 10 ns. As the next step, we have begun development of high-gate-count ORGAs. The new ORGA-VLSI chip can achieve a 16,000-gatecount through reduction of photodiode size, photodiode spacing, and through introduction of a small optical reconfiguration circuit, that do not exceed the resolution of available optical components. This paper presents the new design of a 16,000-gate-count ORGA using a standard 0.35 μm 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip and an evaluation of optical reconfiguration circuits using HSPICE simulation. © 2005 IEEE.

DOI： 10.1109/ISCAS.2005.1464812

Rapid reconfiguration of an optically differential reconfigurable gate array with pulse lasers 査読

M Miyano, M Watanabe, F Kobayashi

FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings 287 - 288 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

We have developed an Optically Differential Reconfigurable Gate Array (ODRGA-VLSI) to realize no-overhead and fast reconfigurable devices. The no-overheadand fast reconfiguration capability of a fabricated VLSI chip has been confirmed experimentally However to date, evaluation of nanosecond reconfiguration speed with an entire system combining a VLSI chip, spatial light modulators (SLMs) used as optical memories, and lasers has never been conducted. Therefore, this paper presents an entire ODRGA system including SLMs, pulse lasers, and an ODRGA-VLSI chip. Results show a 220 ns fast reconfiguration and circuit performance on the gate array.

DOI： 10.1109/FPT.2005.1568564

Optically differential reconfigurable gate array using an optical system with VCSELs 査読

M Miyano, M Watanabe, F Kobayashi

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 274 - 275 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically Reconfigurable Gate Arrays (ORGAs) have been developed to allow rapid reconfiguration. We have developed an Optically Differential Reconfigurable Gate Array (ODRGA) to realize fast and arbitrary partial reconfiguration capabilities. This paper presents the structure of a fabricated ODRGA-VLSI chip using an optical system with Vertical Cavity Surface Emitting Lasers (VCSELs) along with experimental results of reconfiguration.

DOI： 10.1109/ISVLSI.2005.54

Sampling rate conversion by Fourier interpolation 査読

M Inoue, F Kobayashi, M Watanabe

SICE 2004 ANNUAL CONFERENCE, VOLS 1-3 1613 - 1616 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SOC INSTRUMENT CONTROL ENGINEERS JAPAN

New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35 mu m process is 5.728mm(2), smaller than the conventional SRC using filters. The noise level is reduced down to the quantizaion error level by using several improving methods.

An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation 査読

M Watanabe, F Kobayashi

17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS 735 - 738 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

This paper proposes an optically differential reconfigurable gate array (ODRGA) with a partial reconfiguration optical system. The ODRGA not only realizes a partial reconfiguration capability; it also reduces the amount of memory required to store reconfiguration contexts while reducing optical reconfiguration power consumption. This paper presents ODRGA-VLSI, which is available for a partial reconfiguration technique. Advantages of reducing the amount of memory and power consumption are estimated theoretically and compared with a conventional optically reconfigurable gate array.

DOI： 10.1109/ICVD.2004.1261015

Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors 査読

M Watanabe, F Kobayashi

ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS 311 - 311 2004年

An optical reconfiguration circuit for optically reconfigurable gate arrays 査読

M Watanabe, F Kobayashi

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS 529 - 532 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An optical reconfiguration circuit suitable for Optically Reconfigurable Gate Arrays (ORGAs) is proposed to improve the gate density of ORGAs. The optical reconfiguration circuit works as a receiver circuit and temporary memory for optically-supplied reconliguration contexts. The circuit is connected for each programming element of the gate array. Reducing the implementation area of optical reconfiguration circuits is very important to improve the gate density because the number of programming elements of the gate array is extremely large. This paper presents an optical reconfiguration circuit reduced to 43% implementation area compared with that of conventional circuits and an ORGA design with the optical reconfiguration circuit using 0.35 mum 3-Metal CMOS technology. In addition, this study presents an evaluation using HSPICE simulation and photodiode characteristics extracted from experimental results.

DOI： 10.1109/MWSCAS.2004.1354044

Testing method for optical connections using gate array structure in ORGAs 査読

M Watanabe, F Kobayashi

ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS 299 - 299 2004年

A high-density optically reconfigurable gate array using dynamic method 査読

M Watanabe, F Kobayashi

FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS 3203 261 - 269 2004年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SPRINGER-VERLAG BERLIN

A high-density optically reconfigurable gate array (ORGA) is proposed to improve the gate density of conventional ORGAs, which are a type of Field Programmable Gate Array (FPGA). However, unlike FPGAs, an ORGA is reconfigured optically with external optical memories. A conventional ORGA has many programming elements, just as FPGAs do. One programming element consists of a photodiode to detect an optical reconfiguration signal; a latch, a flip-flop or a bit of memory to temporarily store the reconfiguration bit; and some transistors. Among those components, the latch, flip-flop, or memory occupies a large implementation area on a typical VLSI chip-, it prevents realization of a high-gate-density ORGA. This paper presents a high-density ORGA structure that eliminates latches, flip-flops, and memory using a dynamic method and a design of an ORGA-VLSI chip with four optically reconfigurable logic blocks, five optically reconfigurable switching matrices, and four optical reconfigurable I/O blocks including four I/O bits. It uses 0.35 mum 3-Metal CMOS process technology. This study also includes some experimental results.

DOI： 10.1007/978-3-540-30117-2_28

An optically differential reconfigurable gate array using a 0.18 mu m CMOS process 査読

M Watanabe, F Kobayashi

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 281 - 284 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18 mum - 5 Metal CMOS process technology. ODRGA is a type of Field Programmable Gate Arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35 mum - 3 Metal CMOS process technology, their gate-density remains unsatisfactory. For that reason, a new ODRGA-VLSI chip with four logic blocks, five switching matrices, and 16 I/O bits was fabricated on a 7.82 mm(2) chip using more advanced process technology. This paper presents the detailed design of a fabricated ODRGA-VLSI chip, the optical reconfiguration circuit, the gate array structure, the CAD layout, and an ODRGA-VLSI chip mounted on an estimation board. This study also includes experimental results regarding the reconfiguration period.

DOI： 10.1109/SOCC.2004.1362436

部分再構成が可能な光再構成型ゲートアレイVLSI 査読

渡邊実, 小林

電子情報通信学会論文誌 J86-C ( 8 ) 869 - 877 2003年8月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：一般社団法人電子情報通信学会

近年,光による広いバンド幅を利用することで,電気配線では実現できない高速な書込みが可能なプログラマブルゲートアレー,光再構成型ゲートアレーが研究されている.しかし,これまでの光再構成型ゲートアレーでは,回路すべてを書き換えることはできるが,部分的に書き換えることはできなかった.このため,ダイナミックに再構成を行う場合,メモリの使用効率が著しく低下する問題があった.本論文では,部分的な再構成を可能にした光再構成型ゲートアレーのアーキテクチャを示し,0.35μmプロセスに対して4個の論理ブロック,5個のスイッチングマトリックス,4個のI/Oブロックを実装した68ゲート規模の光再構成型ゲートアレーVLSIの実装レイアウトを示す.また,論理ブロック,スイッチングマトリックス,I/Oブロック個別に受光部,差分再構成回路部,ゲートアレー部の占有面積の比率について評価し,0.35μmプロセスを用いた場合,将来的に65kゲート規模の光再構成型ゲートアレーが実現可能なことを示す.

FPGA implementation of Finite Physical Quantity Neural Network 査読

T. Sotohebo, M. Watanabe, F. Kobayashi

Journal of Robotics and Mechatronics 15 ( 2 ) 136 - 142 2003年4月

Configuration for an optically differential reconfigurable gate array 査読

M Miyano, M Watanabe, F Kobayashi

SICE 2003 ANNUAL CONFERENCE, VOLS 1-3 1984 - 1987 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Differential Reconfigurable Gate Array (ODRGA) has been proposed to enable dynamic reconfiguration of an arbitrary location on its gate array. The dynamic reconfiguration of an arbitrary location can be realized by calculating the difference between previous configuration data stored on a VLSI chip and subsequent optically-supplied configuration data. This paper presents an optical reconfiguration sysytem for ODRGA VLSI chips using a liquid crystal television spatial light modulator and shows the experimental results of dynamic reconfiguration of an arbitrary location on an ODRGA VLSI chip.

A finite physical quantity neural network VLSI with a learning capability 査読

M Watanabe, F Kobayashi

SICE 2003 ANNUAL CONFERENCE, VOLS 1-3 1988 - 1991 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A finite physical quantity neural network (FPQNN) VLSI with a learning capability is proposed. The FPQNN model has a feature that the total electric charge stored in all neurons in a network is monotone decreasing while recalling. Despite the restriction of never increasing, the FPQNN model can produce a good performance for pattern classification. This paper presents an analog Circuit implementation with a learning capability that can calculate the movement of electric charge of the FPQNN model precisely and rapidly.

Design of an Optically Differential Reconfigurable Gate Array VLSI chip with optically and electrically controlled logic blocks 査読

M Watanabe, F Kobayashi

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 287 - 288 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Differential Reconfigurable Gate Array (ODRGA) was developed to achieve a partial dynamic reconfiguration capability. This paper proposes a novel optically and electrically controlled logic block structure suitable for ODRGAs. In addition, it presents a design of an optically differential reconfigurable gate array VLSI chip with 4 optically and electrically controlled logic blocks, 5 switching matrices, and 12 optically and electrically controlled I/O bits using 0.35 mum 3-Metal CMOS technology.

DOI： 10.1109/SOC.2003.1241524

An optically differential reconfigurable gate array with a dynamic reconfiguration circuit 査読

Minoru Watanabe, Fuminori Kobayashi

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

An optically differential reconfigurable gate array (ODRGA) using a dynamic circuit technique is proposed to reduce the area occupied by the configuration circuit on a VLSI chip. The ODRGA reconfiguration process is performed by calculating the difference between previous configuration data stored on a VLSI chip and subsequent optically-supplied configuration data. The reconfiguration circuit of our previously proposed ODRGA using static circuit techniques required a large implementation area. This paper introduces a new dynamic reconfiguration circuit and compares an estimate of its area on the VLSI chip with that obtained by the static technique.

DOI： 10.1109/IPDPS.2003.1213349

A neural network model using finite physical quantities and its realization on LSIs 査読

M Watanabe, F Kobayashi

SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1863 - 1864 2002年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A CMOS circuit for a finite physical quantities neural network model is proposed. The circuit can precisely express the movement of the finite physical quantities and quickly execute the enormous iterative calculations in the finite physical quantities model. This paper presents a HSPICE simulation result for pattern recognition and estimation of the circuit.

DOI： 10.1109/SICE.2002.1196607

Motion image compression circuit using the silicon retina as active sensor 査読

M Amagasaki, F Kobayashi, M Watanabe, T Yagi

SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1859 - 1860 2002年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Silicon retina, modeling a biological architecture, can implement parallel operations with low power. To implement a compact, fast image-processing system, this paper describes a circuit with FPGA (Field Programmable Gate Array) and silicon retina combined together. Circuit optimization by DCT (Discrete Cosine Transform) is proposed.

DOI： 10.1109/SICE.2002.1196605

An optically differential reconfigurable gate array and its power consumption estimation 査読

M Watanabe, F Kobayashi

2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS 197 - 202 2002年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A new optically differential reconfigurable gate array (ODRGA) is proposed to reduce configuration power consumption. The ODRGA has a simple architecture that adds a small circuit to conventional optically reconfigurable gate arrays (ORGAs) and uses differential configuration data stored in an optical holographic memory. In this paper configuration power consumption of ORGAs is estimated theoretically. Based on results, we show an estimation of configuration power consumption and comparative area occupied by the configuration circuit for ODRGA and conventional ORGAs.

DOI： 10.1109/FPT.2002.1188682

A compressed implementation of neural network with finite physical quantities on FPGAs 査読

T Sotohebo, M Watanabe, F Kobayashi

SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1861 - 1862 2002年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents the implementation of a multilayer neural network with finite physical quantities on a FPGA. The FPGA implementation extensively reduces much computer time for the neural network that requires iterative operation to exchange the physical quantities between neurons little by little.

DOI： 10.1109/SICE.2002.1196606

ニューラルネットワークVLSI

渡邊実, 小林史典

計測と制御 = Journal of the Society of Instrument and Control Engineers 40 ( 12 ) 893 - 896 2001年12月

An optical energy neural networkwith self-organizing capability 査読

M. Watanabe, A. Itoh, F. Kobayashi

17th annual conference of International Conference on Circuits/Systems Computers and Communications 2 1292 - 1295 2001年7月

DIGITAL ASSOCIATIVE MEMORY NEURAL-NETWORK WITH OPTICAL LEARNING CAPABILITY 査読

M WATANABE, J OHTSUBO

OPTICS COMMUNICATIONS 113 ( 1-3 ) 31 - 38 1994年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ELSEVIER SCIENCE BV

A digital associative memory neural network system with optical learning and recalling capabilities is proposed by using liquid crystal television spatial light modulators and an Optic RAM detector. In spite of the drawback of the limited memory capacity compared with optical analogue associative memory neural network, the proposed optical digital neural network has the advantage of all optical learning and recalling capabilities, thus an all optics network system is easily realized. Some experimental results of the learning and the recalling for character recognitions are presented. This new optical architecture offers compactness of the system and the fast learning and recalling properties. Based on the results, the practical system for the implementation of a faster optical digital associative memory neural network system with ferro-electric liquid crystal SLMs is also proposed.

DOI： 10.1016/0030-4018(94)90588-6

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