研究者詳細 - 渡邊　実

論文 - 渡邊　実

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Power reduction method using negative logic implementation 査読

R. Moriwaki, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 192 2010年4月

MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment 査読

Daisaku Seto, Minoru Watanabe

RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS 5992 134 - 144 2010年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Embedded devices used for spacecraft, satellites, and space stations are vulnerable to the effects of high-energy charged particles. To resolve single-event latch-up (SEL)-associated troubles more flexibly using limited hardware resources in a space environment, reconfigurable devices such as field programmable gate arrays (FPGAs) are suitable. However, such reconfigurable systems present the shortcoming that the circuit itself on the gate array is not robust. The configuration context on a configuration SRAM also suffers from single-event upsets (SEUs) and SELs. This paper therefore proposes an MEMS dynamic optically reconfigurable gate array that is usable under a space radiation environment. The technique enables rapid recovery of a programmable device that has been damaged by high-energy charged particles. It uses incorrect configuration data including some error bits that had been damaged by particles. The configuration data are transferred using wireless communications and are retained on an EEP-ROM/SRAM.

DOI： 10.1007/978-3-642-12133-3_14

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Fiber remote configuration for a dynamic optically reconfigurable gate array 査読

Yumiko Ueno, Minoru Watanabe

2010 15TH OPTOELECTRONICS AND COMMUNICATIONS CONFERENCE (OECC) Optoelectronics and Communications Conference 250 - 251 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION & COMMUNICATION ENGINEERS

This paper presents a new remotely reconfigurable gate array, based on a dynamic optically reconfigurable gate array architecture, which is intended for use in systems at nuclear power plants, plants with no personnel, and other systems.

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Optical buffering technique under a space radiation environment 査読

Mao Nakajima, Minoru Watanabe

OPTICS LETTERS 34 ( 23 ) 3719 - 3721 2009年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

We propose an optical buffering technique for a programmable gate array under a space radiation environment. The technique allows rapid recovery of a programmable device that is damaged by high-energy charged particles. The technique uses invalid configuration data, including error bits that have already been damaged by the particles, while the configuration data are transferred using wireless communications and are retained on electronically erasable, programmable read-only, or static random-access-memory devices. (C) 2009 Optical Society of America

DOI： 10.1364/OL.34.003719

Formation of volume holographic memory using liquid-crystal composites for optically reconfigurable gate array 査読

A. Ogiwara, Y. Ochi, M. Miyake, M. Watanabe, T. Mabuchi, F. Kobayashi

15th MICROOPTICS CONFERENCE 194 - 195 2009年10月

A Four-Context Optically Differential Reconfigurable Gate Array 査読

Mao Nakajima, Minoru Watanabe

JOURNAL OF LIGHTWAVE TECHNOLOGY 27 ( 20 ) 4460 - 4470 2009年10月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Reconfiguration applications based on reconfigurable devices present new computational paradigms since, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, Optically Reconfigurable Gate Arrays (ORGAs) with a holographic memory were developed. They realize rapid reconfigurations and numerous reconfiguration contexts. Furthermore, Optically Differential Reconfigurable Gate Arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However, fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results demonstrating its fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

DOI： 10.1109/JLT.2009.2024173

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Scaling prospect of optically differential reconfigurable gate array VLSIs 査読

Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 60 ( 1-2 ) 137 - 143 2009年8月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SPRINGER

Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 mu m and 0.35 mu m CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.

DOI： 10.1007/s10470-008-9210-9

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Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI 査読

Shinichi Kato, Minoru Watanabe

Embedded Computer Systems: Architectures, Modeling, and Simulation 5657 139 - 148 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

To date, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present the advantageous capabilities compared with ORGAs: they have increased reconfiguration frequency per unit of laser power and reduced optical power consumption. Dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density, but an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array that adopts only the good factors from both architectures has been developed. This paper presents an inversion/non-inversion implementation for a fabricated 11,424 gate-count dynamic optically reconfigurable gate array VLSI. Based on that implementation, three factors are discussed: gate density, reconfiguration frequency per unit of laser power, and optical power consumption.

DOI： 10.1007/978-3-642-03138-0_15

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A multi-context programmable optically reconfigurable gate array

S. Kubota, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 305 - 306 2009年7月

Defect tolerance of an optically reconfigurable gate array with a one-time writable volume holographic memory 査読

Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara

2009 NASA/ESA Conference on Adaptive Hardware and Systems 106 - 111 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the ORGAs capability of perfectly parallel programmability enables avoidance of those defective areas through alternative use of other non-defective areas. Moreover, a holographic memory to store contexts is known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Consequently, damage of a holographic memory rarely affects its diffraction pattern or a reconfiguration context. For that reason, ORGAs are extremely robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability. This paper presents experimentation related to the defect tolerance of new optically reconfigurable gate array with a one-time easily writable volume holographic memory.

DOI： 10.1109/AHS.2009.62

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A sixteen-context dynamic optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

2009 NASA/ESA Conference on Adaptive Hardware and Systems 120 - 125 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on a programmable device. Such dynamic reconfiguration necessitates two important features: fast reconfiguration and numerous contexts. However, because fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DOR-GAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a 16-context DORGA architecture. Furthermore, we present experimental results: 530-833 ns reconfiguration times and 5-9.375 mu s retention times.

DOI： 10.1109/AHS.2009.64

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Optically reconfigurable gate array with a one-time writable holographic memory 査読

T. Mabuchi, K. Miyashiro, M. Watanabe, A. Ogiwara

International Conference on engineering of reconfigurable systems and algorithms 307 - 308 2009年7月

Alignment compensation method for an optically reconfigurable gate array 査読

H. Morita, M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 332 - 333 2009年7月

A 16-context optically reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

IEEE International Conference on Application-specific Systems, Architectures and Processors 227 - 230 2009年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.

DOI： 10.1109/ASAP.2009.41

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A programmable dynamic optically reconfigurable gate array

Shinya Kubota, Minoru Watanabe

2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference 323 - 326 2009年6月

Fast reconfiguration experiments of an optically differential reconfigurable gate array with nine configuration contexts 査読

Mao Nakajima, Minoru Watanabe

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 2013 - 2016 2009年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically differential reconfigurable gate arrays (ODRGAs) have been developed to achieve rapid reconfiguration and numerous reconfiguration contexts. Although fast reconfiguration experiments of a four-context ODRGA have been presented in earlier reports, the number of configuration contexts was insufficient for dynamic reconfiguration applications. Therefore, we have developed a more advanced nine-context ODRGA system. This paper presents fast 86.2 ns reconfiguration experiments using a nine-context ODRGA architecture and discusses plans for future work.

DOI： 10.1109/ISCAS.2009.5118187

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A Nine-context Programmable Optically Reconfigurable Gate Array with Semiconductor Lasers 査読

Shinya Kubota, Minoru Watanabe

GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI 269 - 273 2009年5月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ASSOC COMPUTING MACHINERY

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, compared with current field programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and then implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that daunting problem, this paper presents a nine-context programmable ORGA and its writer. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1145/1531542.1531606

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Dynamic optically reconfigurable gate array with high defect tolerance 査読

D. Seto, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 171 171 2009年4月

Power reduction effect of an inversion/non-inversion dynamic optically reconfigurable gate array 査読

S. Kato, M. Watanabe

IEEE Symposium on Low-Power and High-Speed Chips 172 2009年4月

Fast Optical Reconfiguration of a Nine-Context DORGA 査読

Mao Nakajima, Minoru Watanabe

International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science 5453 123 - 132 2009年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SPRINGER-VERLAG BERLIN

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a nine-context DORGA architecture. Furthermore, this paper presents experimental results: 1.2-8.97 mu s reconfiguration times and 66-221 mu s retention times.

DOI： 10.1007/978-3-642-00641-8_14

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