研究者詳細 - 渡邊　実

論文 - 渡邊　実

分割表示 385 件中 81 - 100 件目／全件表示 >>

Full-hardware robot controller

Y. Takaki, M. Watanabe, K. Sano

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Radiation-hardened power supply unit

Shinya Fujisaki, Minoru Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Radiation-hardened optically reconfigurable gate array 査読

M. Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

An optically reconfigurable gate array using four liquid crystal spatial light modulators 査読

Y. Takaki, M. Watanabe

IEEE CPMT Symposium Japan 185 - 188 2018年11月

Triple modular redundancy optically reconfigurable gate array

T. Yoshinaga, M. Watanabe

Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning” 2018年11月

Optically reconfigurable gate array using a colored configuration, 査読

T. Fujimori, M. Watanabe

Applied Optics 57 ( 29 ) 8625 - 8631 2018年10月

Effects of radiation exposure on volume gratings formed in liquid crystal composites 査読

A Ogiwara, M. Toda, M. Watanabe, H. Kakiuchida

2018 KJF International Conference on Organic Materials for Electronics and Photonics 2018年9月

Total-Ionizing-Dose Tolerance of the configuration function of MAX3000A CPLDs 査読

T. Fujimori, M. Watanabe

Data Workshop 2018年9月

Radiation-hardened and stabilized power supply unit based on a lithiumion battery 査読

S. Fujisaki, M. Watanabe

Radiation and its Effects on Components and Systems conference 2018年9月

Ultrasonic sensor system with a 94 Mrad total-ionizing-dose tolerance 査読

S. Fujisaki, M. Watanabe

IEEE International Conference on Semiconductor Electronics 263 - 266 2018年8月

A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory 査読

T. Fujimori, M. Watanabe

NASA/ESA Conference on Adaptive Hardware and Systems 2018年8月

Tolerance of radiation exposure on volume gratings using liquid crystal composites

M.Toda, A.Ogiwara, M.Watanabe

27th International Liquid Crystal Conference (ILCC2018) P4-C2-47 2018年7月

A 603 Mrad total-ionizing-dose tolerance optically reconfigurable gate array VLSI 査読

T. Fujimori, M. Watanabe

International Conference on Signals and Systems 249 - 254 2018年5月

High total-ionizing-dose tolerance field programmable gate array 査読

T. Fujimori, M. Watanabe

IEEE International Symposium on Circuits and Systems 1 - 4 2018年5月

An 807 Mrad total dose tolerance of an optically reconfigurable gate array VLSI

IEEE Workshop on Silicon Errors in Logic – System Effects 2018年4月

FFT implementation using mono-instruction set computer (MISC) architecture 査読

H. Shinba, M. Watanabe

Second Workshop on Pioneering Processor Paradigms 2018年2月

Holographic memory calculation FPGA accelerator for optically reconfigurable gate arrays 査読

Takumi Fujimori, Minoru Watanabe

Proceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017 2018- 620 - 625 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V
Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770
Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770
Intel Corp.).

DOI： 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.109

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Resistance evaluation of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation 査読

Akifumi Ogiwara, Minoru Watanabe, Yoshizumi Ito

22nd Microoptics Conference, MOC 2017 2017- 200 - 201 2017年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are investigated for the applications requiring high reliability using an optically reconfigurable gate array. The optical properties and internal grating structures are investigated by using a cobalt 60 gamma radiation source to examine the resistance of 100 Mrad total-ionizing-dose.

DOI： 10.23919/MOC.2017.8244556

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Parallel light configuration that increases the radiation tolerance of integrated circuits 査読

Takumi Fujimori, Minoru Watanabe

OPTICS EXPRESS 25 ( 23 ) 28136 - 28145 2017年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：OPTICAL SOC AMER

Total ionizing dose tolerances of current integrated circuits are limited to 3-10 kGy because semiconductor devices are fundamentally vulnerable to radiation. However, using programmable architecture, the total ionizing dose tolerances of integrated circuits can be increased if the integrated circuits can be repaired each time a permanent failure occurs. Nevertheless, current programmable devices cannot allow such repairable use because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged. To increase the radiation tolerance of integrated circuits, this paper presents a proposal of a new optoelectronic programmable device with a parallel light configuration architecture instead of current field programmable gate arrays which have a serial configuration architecture. This demonstration confirms 1.9 MGy radiation tolerance on an optoelectronic programmable device using a non-radiation-hardened standard complementary metal oxide semiconductor process. (C) 2017 Optical Society of America

DOI： 10.1364/OE.25.028136

Web of Science

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Small Area Implementation for Optically Reconfigurable Gate Array VLSI: FFT Case 査読

Ili Shairah Abdul Halim, Fuminori Kobayashi, Minoru Watanabe, Koichiro Mashiko, Ooi Chia Yee

JOURNAL OF SCIENTIFIC & INDUSTRIAL RESEARCH 76 ( 11 ) 697 - 700 2017年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：NATL INST SCIENCE COMMUNICATION-NISCAIR

Optically reconfigurable gate array (ORGA) is a type of multi-context field programmable gate array (FPGA) that has achieved a nanosecond-order reconfiguration capability as well as attaining numerous reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the function of multi-core processor. ORGA system has high dependability in a radiation rich environment and the development is progressing towards better radiation tolerance. In this paper, size minimization of the ORGA-VLSI is the main concern to maintain its high dependability; hence wire complexity needs special consideration during floor planning. A case of Fast Fourier Transform (FFT) is shown to demonstrate the effectiveness of circuit modification by implementing dynamic reconfiguration for area optimization. Results show that, compared with a normal FFT configuration, the minimum wirelength is reduced 5.5% for a 32-point FFT implementation.

Web of Science

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