研究者詳細 - 渡邊　実

論文 - 渡邊　実

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Analysis of retention time under multi-configuration on a DORGA 査読

Daisaku Seto, Minoru Watanabe

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 131 - 134 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, dynamic optically reconfigurable architecture has been proposed to increase the gate count of the ORGA-VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memories. Consequently, extremely high gate count ORGAs have been realized. However, in this architecture, since background diffraction light of configuration contexts reduces the retention time of circuit information stored in junction capacitances of photodiodes, it has remained a concern that under multi-configuration, an optical configuration can reduce the retention time of other circuits that have already been programmed before the configuration and are functioning on a gate array. This paper clarifies that the dynamic optically reconfigurable architecture is effective even under multi-configuration.

DOI： 10.1109/SOCC.2008.4641495

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A 9-context Optically Reconfigurable Gate Array 査読

Takayuki Mabuchi, Minoru Watanabe

ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 1 - 4 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. Up to now, four-context ORGAs have been demonstrated. This paper presents the first 9-context ORGA architecture that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results and plans for future work.

DOI： 10.1109/SOCDC.2008.4815560

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A double or triple module redundancy model exploiting dynamic reconfigurations 査読

Kouji Shinohara, Minoru Watanabe

PROCEEDINGS OF THE 2008 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS 114 - 121 2008年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Majority voting is a commonly used approach to increase system reliability. Standard triple-module-redundancy (TMR) methods are frequently used in space applications. Using these methods, triple modules and voting circuits are implemented onto an Application Specific Integrated Circuit (ASIC) or an FPGA. When a single event upset occurs, the voting circuit neglects the failure value of a module receiving the single event upset and takes a correct value of the other two modules not receiving it. However, the triple-module implementation requires a large implementation area on VLSIs. Therefore, to reduce the area of TMR implementation, this paper presents a novel double or triple module redundancy (DTMR) method for dynamically reconfigurable devices using a design example of a state machine. Furthermore, this paper presents experimental results of the method using a highly reliable optically reconfigurable gate array.

DOI： 10.1109/AHS.2008.67

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Optimization of reconfiguration speed control bits for an Optically Reconfigurable Gate Array 査読

M. Watanabe

International Conference on engineering of reconfigurable systems and algorithms 2007年7月

272 gate count optically differential reconfigurable gate array VLSI 査読

M. Watanabe, T. Shiki, F. Kobayashi

International Conference on engineering of reconfigurable systems and algorithms 2007年7月

Power Consumption Reduction Method of Dynamic Optically Reconfigurable Gate Array VLSIs 査読

M. Watanabe, F. Kobayashi

IEEE Symposium on Low-Power and High-Speed Chips 145 2007年4月

Superimposing technique of reconfiguration contexts 査読

M. Watanabe, F. Kobayashi

ACM/SIGDA International Symposium on Field Programmable Gate Arrays 227 - 228 2007年2月

時間領域フーリエ補間による非同期サンプリング・レート・コンバータ, 査読

井上,小林, 渡邊実

計測自動制御学会論文集 43 ( 2 ) 145 - 152 2007年2月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：The Society of Instrument and Control Engineers

A time-domain SRC, sampling rate converter, using Fourier interpolation to achieve less gate count than in frequency domain is proposed. The new SRC is implemented in 1/150 of the circuit size of conventional SRC with moderate performance using filters. It can also be used as back-end for filter-type SRC to achieve high performance efficiently.

DOI： 10.9746/ve.sicetr1965.43.145

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Superimposing technique of reconfiguration contexts for increasing reconfiguration speed 査読

M. Watanabe, F. Kobayashi

Mobile Computing Hardware Architectures Design Symposium 2007年1月

Reconfiguration performance analysis of a dynamic optically reconfieurable gate array architecture 査読

Daisaku Seto, Minoru Watanabe

ICFPT 2007: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS 265 - 268 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

DOI： 10.1109/FPT.2007.4439262

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Reconfigurations of a dynamic optically reconfigurable architecture under a constant laser exposure 査読

Minoru Watanabe, Daisaku Seto

EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS 405 - 408 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, we have proposed a dynamic optically reconfigurable architecture for ORGAs to increase the gate count of the VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memory. In this architecture, suitable laser exposure time for each implementation circuit is different from each other. Nevertheless, the laser exposure time is always designed as a constant to simplify its optical reconfiguration architecture and procedure. So, the affect for retention time of implementation circuits under such the condition was concerned, however, which has never been analyzed. Therefore, this paper experimentally presents that the dynamic optically reconfigurable architecture is available under a constant laser exposure condition.

DOI： 10.1109/EDSSC.2007.4450148

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A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays 査読

Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Optically Reconfigurable Gate Arrays (ORGAs) offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSIs by exploiting the large storage capacity of a holographic memory. The first ORGA was developed to achieve rapid reconfiguration and a number of reconfiguration contexts
it consisted of a gate array VLSI, a holographic memory, and a laser diode array. The ORGA achieved a 16 μs to 20 μs reconfiguration period that was faster than that of FPGAs, with 100 reconfiguration contexts. However, the ORGA requires the gate array to halt during reconfiguration. Therefore, the ORGA can not be reconfigured frequently because of the associated reconfiguration overhead. On the other hand, new ORGA-VLSIs that have less than 10 ns reconfiguration capability without any related overhead have already been fabricated. However, to date, a multi-holographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has never been developed. For such realization, this paper proposes a four-context ORGA architecture and a multi-context holographic memory recording system used for it. In addition, experimentally demonstrated results of recording a holographic memory and reconfiguring an ORGA-VLSI are described. © 2007 IEEE.

DOI： 10.1109/IPDPS.2007.370391

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Holographic memory reconfigurable VLSI 査読

Minoru Watanabe, Fuminori Kobayashi

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 401 - 404 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration for numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed by a laser diode array. It is noteworthy that ORGA-VLSIs that can be reconfigured in less than 10 ns without any overhead have already been fabricated. However, up to now, a multi-holographic reconfiguration system that is suitable for such fast-reconfigurable ORGA-NLSIs without any overhead has never been developed. As the first step toward such realization, a multi-context component is demonstrated experimentally using a liquid crystal spatial light modulator and a pulse laser This paper describes experimental results and plans for future work.

DOI： 10.1109/ISCAS.2007.378474

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Optically differential reconfigurable gate array 査読

Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 90 ( 11 ) 132 - 139 2007年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SCRIPTA TECHNICA-JOHN WILEY & SONS

Recent years have seen the development of optically reconfigurable gate arrays, which can be reconfigured using light at high speeds that cannot be implemented with electrical wiring. However, optically reconfigurable gate arrays have reconfiguration speeds of 16 to 20 mu s, which is fast compared to FPGAs (Field Programmable Gate Arrays), but high-speed reconfiguration, approaching the operating clock of a mounted circuit, has not been implemented. Also, partial reconfiguration, which is indispensable for frequent dynamic reconfiguration, has not been considered. The authors propose an Optically Differential Reconfigurable Gate Array (ODRGA), which can be reconfigured at high speeds close to the operating clock of a mounted circuit and which allows partial reconfiguration of any zone in bit units. This paper includes an overview of ODRGA and introduces the optically differential reconfigurable architecture, with which arbitrary, partial reconfiguration is possible, as well as the optically reconfigurable architecture enabling highspeed optical reconfiguration. Then, it is demonstrated that high-speed optical reconfiguration at 200 ns, the world's fastest system-level optical reconfiguration, is possible with an optical system using a pulse laser diode wherein nanosecond optical reconfiguration is possible with a prototype stand-alone VLSI chip. Finally, it is made clear that, in the future, improvement to the optical components will make possible nanosecond high-speed optical reconfiguration at the system level as well. (C) 2007 Wiley Periodicals, Inc.

DOI： 10.1002/ecjb.20420

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DORGA holographic memory architecture 査読

Minoru Watanabe, Shoutarou Fukagawa, Fuminori Kobayashi

2007 INTERNATIONAL CONFERENCE ON MICROELECTRONICS 222 - + 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However, in ORGAs, although a large virtual gate count can be realized by exploiting a large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is stilt important to increase the instantaneous performance. In previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context occupied a large implementation area of the ORGA-VLSIs and thereby prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture was proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. This paper presents a perfect DORGA architecture including a holographic memory. The performance of the DORGA architecture, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed relative to the results of this study.

DOI： 10.1109/ICM.2007.4497743

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Scaling rule of optically differential reconfigurable gate array VLSIs 査読

Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 101 - 104 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically merely by increasing the reconfiguration frequency. Therefore, the reconfiguration time and reconfiguration overhead of next-generation programmable devices are extremely important parameters. To realize zero-overhead and short reconfiguration, an Optically Differential Reconfigurable Gate Array (ODRGA) VLSIs were developed. However, up to now, the scaling rule of ODRGAs has never been clarified. This paper describes the designs of ODRGA-VLSIs using 0.18 mu m and 0.35 mu m CMOS processes and presents discussion of the scaling rule of ODRGAs using layout results.

DOI： 10.1109/MWSCAS.2007.4488553

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A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array 査読

Mao Nakajima, Minoru Watanabe

ICFPT 2007: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS 297 - 300 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To date, holographic configuration speeds have remained limited to 16 mu s because of issues related to the architecture of optically reconfigurable gate array VLSIs (ORGA-VLSIs). Therefore, to improve the issue, optically differential reconfigurable gate array VLSIs (ODRGA-VLSIs) have been developed and have achieved zero-overhead and nanosecond optical reconfiguration. Moreover the architecture of an ODRGA-VLSI has the advantage of accelerating the reconfiguration speed compared to that of other ORGAs. However, nanosecond holographic configurations and, in particular rapid holographic reconfiguration exploiting the advantages of ODRGA-VLSIs have not been reported. Therefore, this paper presents results of the world's fastest 62.5 ns holographic reconfiguration, exploiting advantages of the ODRGA-VLSI.

DOI： 10.1109/FPT.2007.4439270

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An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI 査読

Minoru Watanabe

20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 75 - 78 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world's largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm(2) chip using 0.35 mu m-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time.

DOI： 10.1109/SOCC.2007.4545430

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A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI 査読

Minoru Watanabe, Fuminori Kobayashi

PROCEEDINGS OF THE ASP-DAC 2007 124 - + 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 mu m - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

DOI： 10.1109/ASPDAC.2007.357972

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Manufacturing-defect tolerance analysis of optically reconfigurable gate arrays, 査読

M. Watanabe, F. Kobayashi

World Scientific and Engineering Academy and Society Transactions on Signal Processing 11 ( 2 ) 1457 - 1464 2006年11月

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