研究者詳細 - 渡邊　実

論文 - 渡邊　実

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A zero-overhead dynamic optically reconfigurable gate array 査読

M Watanabe, F Kobayashi

FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS 297 - 298 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a zero-overhead Dynamic Optically Reconfigurable Gate Array (DORGA) that uses the load capacitance of gates to construct a gate array to maintain its state during optical reconfiguration, and uses junction capacitance of photodiodes as configuration memory. It improves a reconfiguration overhead problem of the previously proposed DORGA. The reconfiguration procedure is executable without the overhead of optical reconfiguration by reducing the dispersion delay between optical reconfiguration circuits. This paper presents the design of 1,632 gate count zero-overhead DORGAs reduced the dispersion delay using a standard 0.35 mu m three-metal CMOS process technology.

DOI： 10.1109/FPT.2005.1568569

An improved dynamic optically reconfigurable gate array 査読

M Watanabe, F Kobayashi

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 136 - 141 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

To date, we have proposed Dynamic Optically Reconfigurable Gate Arrays (DORGAs), the implemented photodiodes of which serve not only as receivers but also as memory. DORGA offers the merit of easily providing a high gate count optically reconfigurable gate array (ORGA) because each reconfiguration circuit consists of only a photodiode and a refresh transistor However even though the fast reconfiguration capability has been confirmed as less than 6 ns, such systems have a demerit: their gate arrays can not function during reconfiguration. Consequently, reconfiguration and operation of the implemented circuit on a gate array can not be executed in parallel. Because of that fact, the dynamical reconfiguration frequency of DORGA is slow compared to those of ORGAs with latches, flip-flops, or memory. For that reason, this paper proposes a new optical reconfiguration architecture. Using it, the reconfiguration and implemented circuit operation on a gate array are executable in parallel merely by adding a pass transistor The new design of a 476-gate-count improved DORGA using a standard 0. 35 mu m three-metal CMOS process technology is also shown.

DOI： 10.1109/ISVLSI.2005.16

A 16,000-gate-count Optically Reconfigurable Gate Array in a standard 0.35μm CMOS technology 査読

Minoru Watanabe, Fuminori Kobayashi

Proceedings - IEEE International Symposium on Circuits and Systems 1213 - 1217 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Up to now, we have fabricated 68-gate-count Optically Reconfigurable Gate Arrays (ORGAs), the reconfiguration period of which has been confirmed as less than 10 ns. As the next step, we have begun development of high-gate-count ORGAs. The new ORGA-VLSI chip can achieve a 16,000-gatecount through reduction of photodiode size, photodiode spacing, and through introduction of a small optical reconfiguration circuit, that do not exceed the resolution of available optical components. This paper presents the new design of a 16,000-gate-count ORGA using a standard 0.35 μm 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip and an evaluation of optical reconfiguration circuits using HSPICE simulation. © 2005 IEEE.

DOI： 10.1109/ISCAS.2005.1464812

Rapid reconfiguration of an optically differential reconfigurable gate array with pulse lasers 査読

M Miyano, M Watanabe, F Kobayashi

FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings 287 - 288 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

We have developed an Optically Differential Reconfigurable Gate Array (ODRGA-VLSI) to realize no-overhead and fast reconfigurable devices. The no-overheadand fast reconfiguration capability of a fabricated VLSI chip has been confirmed experimentally However to date, evaluation of nanosecond reconfiguration speed with an entire system combining a VLSI chip, spatial light modulators (SLMs) used as optical memories, and lasers has never been conducted. Therefore, this paper presents an entire ODRGA system including SLMs, pulse lasers, and an ODRGA-VLSI chip. Results show a 220 ns fast reconfiguration and circuit performance on the gate array.

DOI： 10.1109/FPT.2005.1568564

Optically differential reconfigurable gate array using an optical system with VCSELs 査読

M Miyano, M Watanabe, F Kobayashi

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 274 - 275 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

Optically Reconfigurable Gate Arrays (ORGAs) have been developed to allow rapid reconfiguration. We have developed an Optically Differential Reconfigurable Gate Array (ODRGA) to realize fast and arbitrary partial reconfiguration capabilities. This paper presents the structure of a fabricated ODRGA-VLSI chip using an optical system with Vertical Cavity Surface Emitting Lasers (VCSELs) along with experimental results of reconfiguration.

DOI： 10.1109/ISVLSI.2005.54

Sampling rate conversion by Fourier interpolation 査読

M Inoue, F Kobayashi, M Watanabe

SICE 2004 ANNUAL CONFERENCE, VOLS 1-3 1613 - 1616 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SOC INSTRUMENT CONTROL ENGINEERS JAPAN

New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35 mu m process is 5.728mm(2), smaller than the conventional SRC using filters. The noise level is reduced down to the quantizaion error level by using several improving methods.

An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation 査読

M Watanabe, F Kobayashi

17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS 735 - 738 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE COMPUTER SOC

This paper proposes an optically differential reconfigurable gate array (ODRGA) with a partial reconfiguration optical system. The ODRGA not only realizes a partial reconfiguration capability; it also reduces the amount of memory required to store reconfiguration contexts while reducing optical reconfiguration power consumption. This paper presents ODRGA-VLSI, which is available for a partial reconfiguration technique. Advantages of reducing the amount of memory and power consumption are estimated theoretically and compared with a conventional optically reconfigurable gate array.

DOI： 10.1109/ICVD.2004.1261015

Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors 査読

M Watanabe, F Kobayashi

ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS 311 - 311 2004年

An optical reconfiguration circuit for optically reconfigurable gate arrays 査読

M Watanabe, F Kobayashi

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS 529 - 532 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An optical reconfiguration circuit suitable for Optically Reconfigurable Gate Arrays (ORGAs) is proposed to improve the gate density of ORGAs. The optical reconfiguration circuit works as a receiver circuit and temporary memory for optically-supplied reconliguration contexts. The circuit is connected for each programming element of the gate array. Reducing the implementation area of optical reconfiguration circuits is very important to improve the gate density because the number of programming elements of the gate array is extremely large. This paper presents an optical reconfiguration circuit reduced to 43% implementation area compared with that of conventional circuits and an ORGA design with the optical reconfiguration circuit using 0.35 mum 3-Metal CMOS technology. In addition, this study presents an evaluation using HSPICE simulation and photodiode characteristics extracted from experimental results.

DOI： 10.1109/MWSCAS.2004.1354044

Testing method for optical connections using gate array structure in ORGAs 査読

M Watanabe, F Kobayashi

ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS 299 - 299 2004年

A high-density optically reconfigurable gate array using dynamic method 査読

M Watanabe, F Kobayashi

FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS 3203 261 - 269 2004年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SPRINGER-VERLAG BERLIN

A high-density optically reconfigurable gate array (ORGA) is proposed to improve the gate density of conventional ORGAs, which are a type of Field Programmable Gate Array (FPGA). However, unlike FPGAs, an ORGA is reconfigured optically with external optical memories. A conventional ORGA has many programming elements, just as FPGAs do. One programming element consists of a photodiode to detect an optical reconfiguration signal; a latch, a flip-flop or a bit of memory to temporarily store the reconfiguration bit; and some transistors. Among those components, the latch, flip-flop, or memory occupies a large implementation area on a typical VLSI chip-, it prevents realization of a high-gate-density ORGA. This paper presents a high-density ORGA structure that eliminates latches, flip-flops, and memory using a dynamic method and a design of an ORGA-VLSI chip with four optically reconfigurable logic blocks, five optically reconfigurable switching matrices, and four optical reconfigurable I/O blocks including four I/O bits. It uses 0.35 mum 3-Metal CMOS process technology. This study also includes some experimental results.

DOI： 10.1007/978-3-540-30117-2_28

An optically differential reconfigurable gate array using a 0.18 mu m CMOS process 査読

M Watanabe, F Kobayashi

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 281 - 284 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18 mum - 5 Metal CMOS process technology. ODRGA is a type of Field Programmable Gate Arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35 mum - 3 Metal CMOS process technology, their gate-density remains unsatisfactory. For that reason, a new ODRGA-VLSI chip with four logic blocks, five switching matrices, and 16 I/O bits was fabricated on a 7.82 mm(2) chip using more advanced process technology. This paper presents the detailed design of a fabricated ODRGA-VLSI chip, the optical reconfiguration circuit, the gate array structure, the CAD layout, and an ODRGA-VLSI chip mounted on an estimation board. This study also includes experimental results regarding the reconfiguration period.

DOI： 10.1109/SOCC.2004.1362436

部分再構成が可能な光再構成型ゲートアレイVLSI 査読

渡邊実, 小林

電子情報通信学会論文誌 J86-C ( 8 ) 869 - 877 2003年8月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：一般社団法人電子情報通信学会

近年,光による広いバンド幅を利用することで,電気配線では実現できない高速な書込みが可能なプログラマブルゲートアレー,光再構成型ゲートアレーが研究されている.しかし,これまでの光再構成型ゲートアレーでは,回路すべてを書き換えることはできるが,部分的に書き換えることはできなかった.このため,ダイナミックに再構成を行う場合,メモリの使用効率が著しく低下する問題があった.本論文では,部分的な再構成を可能にした光再構成型ゲートアレーのアーキテクチャを示し,0.35μmプロセスに対して4個の論理ブロック,5個のスイッチングマトリックス,4個のI/Oブロックを実装した68ゲート規模の光再構成型ゲートアレーVLSIの実装レイアウトを示す.また,論理ブロック,スイッチングマトリックス,I/Oブロック個別に受光部,差分再構成回路部,ゲートアレー部の占有面積の比率について評価し,0.35μmプロセスを用いた場合,将来的に65kゲート規模の光再構成型ゲートアレーが実現可能なことを示す.

FPGA implementation of Finite Physical Quantity Neural Network 査読

T. Sotohebo, M. Watanabe, F. Kobayashi

Journal of Robotics and Mechatronics 15 ( 2 ) 136 - 142 2003年4月

Configuration for an optically differential reconfigurable gate array 査読

M Miyano, M Watanabe, F Kobayashi

SICE 2003 ANNUAL CONFERENCE, VOLS 1-3 1984 - 1987 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Differential Reconfigurable Gate Array (ODRGA) has been proposed to enable dynamic reconfiguration of an arbitrary location on its gate array. The dynamic reconfiguration of an arbitrary location can be realized by calculating the difference between previous configuration data stored on a VLSI chip and subsequent optically-supplied configuration data. This paper presents an optical reconfiguration sysytem for ODRGA VLSI chips using a liquid crystal television spatial light modulator and shows the experimental results of dynamic reconfiguration of an arbitrary location on an ODRGA VLSI chip.

A finite physical quantity neural network VLSI with a learning capability 査読

M Watanabe, F Kobayashi

SICE 2003 ANNUAL CONFERENCE, VOLS 1-3 1988 - 1991 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A finite physical quantity neural network (FPQNN) VLSI with a learning capability is proposed. The FPQNN model has a feature that the total electric charge stored in all neurons in a network is monotone decreasing while recalling. Despite the restriction of never increasing, the FPQNN model can produce a good performance for pattern classification. This paper presents an analog Circuit implementation with a learning capability that can calculate the movement of electric charge of the FPQNN model precisely and rapidly.

Design of an Optically Differential Reconfigurable Gate Array VLSI chip with optically and electrically controlled logic blocks 査読

M Watanabe, F Kobayashi

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS 287 - 288 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

An Optically Differential Reconfigurable Gate Array (ODRGA) was developed to achieve a partial dynamic reconfiguration capability. This paper proposes a novel optically and electrically controlled logic block structure suitable for ODRGAs. In addition, it presents a design of an optically differential reconfigurable gate array VLSI chip with 4 optically and electrically controlled logic blocks, 5 switching matrices, and 12 optically and electrically controlled I/O bits using 0.35 mum 3-Metal CMOS technology.

DOI： 10.1109/SOC.2003.1241524

An optically differential reconfigurable gate array with a dynamic reconfiguration circuit 査読

Minoru Watanabe, Fuminori Kobayashi

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003 2003年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

An optically differential reconfigurable gate array (ODRGA) using a dynamic circuit technique is proposed to reduce the area occupied by the configuration circuit on a VLSI chip. The ODRGA reconfiguration process is performed by calculating the difference between previous configuration data stored on a VLSI chip and subsequent optically-supplied configuration data. The reconfiguration circuit of our previously proposed ODRGA using static circuit techniques required a large implementation area. This paper introduces a new dynamic reconfiguration circuit and compares an estimate of its area on the VLSI chip with that obtained by the static technique.

DOI： 10.1109/IPDPS.2003.1213349

A neural network model using finite physical quantities and its realization on LSIs 査読

M Watanabe, F Kobayashi

SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1863 - 1864 2002年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A CMOS circuit for a finite physical quantities neural network model is proposed. The circuit can precisely express the movement of the finite physical quantities and quickly execute the enormous iterative calculations in the finite physical quantities model. This paper presents a HSPICE simulation result for pattern recognition and estimation of the circuit.

DOI： 10.1109/SICE.2002.1196607

Motion image compression circuit using the silicon retina as active sensor 査読

M Amagasaki, F Kobayashi, M Watanabe, T Yagi

SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1859 - 1860 2002年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Silicon retina, modeling a biological architecture, can implement parallel operations with low power. To implement a compact, fast image-processing system, this paper describes a circuit with FPGA (Field Programmable Gate Array) and silicon retina combined together. Circuit optimization by DCT (Discrete Cosine Transform) is proposed.

DOI： 10.1109/SICE.2002.1196605

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