研究者詳細 - 豊田　啓孝

論文 - 豊田　啓孝

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Lossy resonators for suppressing power-bus resonance of printed circuit boards 査読

Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe

IEEE Electromagnetic Compatibility Magazine 3 ( 1 ) 65 - 69 2014年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Power-bus resonance of printed circuit boards causes electromagnetic interference and detraction of power integrity. To suppress the power-bus resonance, we propose the application of lossy resonators in the power bus. Here, we first explain the concepts of the proposed resonators, focusing especially on the application based on the impedance characteristics. Then, we explain the full-wave simulation conducted to demonstrate that the proposed resonator effectively suppressed power-bus resonance.

DOI： 10.1109/MEMC.2014.6798799

Investigation in Burst Pulse Injection Method for Fault Based Cryptanalysis 査読

Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC) 743 - 747 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

電源線から侵入した外乱に起因するクロックグリッチによるFPGA誤動作事例

五百旗頭健吾, 前島一仁, 渡辺哲史, 籠谷裕人, 野上保之, 林優一, 豊田啓孝, 曽根秀昭

エレクトロニクス実装学術講演大会講演論文集 28 ( 0 ) 63 - 66 2014年

記述言語：日本語出版者・発行元：一般社団法人エレクトロニクス実装学会

バルク電流やバーストといった外乱注入により発生した暗号FPGAの誤動作に関して考察した。特に発生した誤動作の直接原因がクロックグリッチの場合について、まず、外乱によりFPGAのクロック配線にグリッチが重畳することを実験により検証した。次に、発生した誤動作をグリッチ付クロックをFPGAに直接与える構成において再現し、回路動作とグリッチの関係を検証した。以上の実験結果に基づき、外乱によりクロックグリッチが発生した場合の誤動作発生機構、および評価環境における誤動作発生確率を示した。

DOI： 10.11486/ejisso.28.0_63

Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits 査読

Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility 834 - 839 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation. © 2013 IEEE.

DOI： 10.1109/ISEMC.2013.6670526

Experimental Model Validation of Mode-conversion Sources Introduced to Modal Equivalent Circuit 査読

Kota Sejima, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Tetsushi Watanabe

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC) 492 - 497 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Delta h). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Delta h becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity.

Equivalent Current Source of Side-channel Signal for Countermeasure Design with Analog Circuit Simulator 査読

Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC) 806 - 811 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication.

Identification of Equivalent Current Source of Cryptographic Circuit Based on Impedance and Current Measurements at Board Level 査読

Kaoru Okamoto, Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

2012 PROCEEDINGS OF SICE ANNUAL CONFERENCE (SICE) 73 - 78 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：SOC INSTRUMENT CONTROL ENGINEERS JAPAN

Side-channel attacks are a kind of cryptanalytic attacks by means of the electric current in the range of radio frequency (RF) leaking out from a cryptographic integrated circuit (IC) and/or the electromagnetic radiation generated by the RF power current. The RF power current is caused by simultaneous switching activities of logic gates during an encryption process operated in the cryptographic IC. The RF power current is a major cause of the electromagnetic interference (EMI). To decrease the RF power current at PCB level can lead to decrease designing costs. As a preparation of applying LECCS models to a cryptographic IC for estimating the RF power current occurred during an encryption process, the model parameters were identified from measurements in this paper. The LECCS models were composed of a current source that expressed the RF power current occurred in the cryptographic circuit and a passive network. The current source identified grown in amplitude 200 ns after the beginning of the encryption process. This agreed to the beginning of the target round. In frequency domain, current spectra were seen at 24 MHz and its harmonics. The authors obtained waveforms of the RF power current from analog circuit simulations with the LECCS model identified, and validated the cryptographic device in security against the side-channel attacks by means of the correlation power analysis (CPA) method. Results of CPA with the simulated waveforms were consistent to CPA results with measured waveforms. These results means that model parameters were identified correctly, and suggests that the LECCS model is effective for validation of cryptographic devices with respect to side-channel attacks.

Insertion of Parallel RL Circuits into Power Distribution Network for Simultaneous Switching Current Reduction and Power Integrity 査読

Kengo Iokibe, Yusuke Yano, Yoshitaka Toyota

2012 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) 417 - 420 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

Experimental model validation of mode-conversion sources introduced to modal equivalent circuit 査読

Kota Sejima, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility 492 - 497 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Δh). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Δh becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity. © 2012 IEEE.

DOI： 10.1109/ISEMC.2012.6351682

Evaluation of Relationship between STP-cable Grounding and Mode Conversion Taking into Account Imbalance Factor 査読

Tatsuya Nobunaga, Yoshitaka Toyota, Kengo Iokibe, Liuji Koga, Tetsushi Watanabe

2012 6TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS (CEEM' 2012) 119 - 119 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

In grounding an STP cable, mode conversion occurs depending on how to ground it. For investigating the mode conversion in a four-conductor transmission-line system that consists of three conductors and the system ground such as the STP cable above the system ground, as shown in Fig. I. we have developed modal equivalent circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in a three-conductor transmission-line system. The modal equivalent circuit consists of three modal equivalent circuits of normal mode (Fig. 2), primary common mode (Fig. 3), and secondary common mode(Fig. 4). In this paper, mode conversion between normal mode and primary common mode was evaluated using mixed-mode S parameters and the measured data validated the modal equivalent circuit. As a result, it was found that mode conversion depends on the imbalance factor and it was examined how to ground for suppressing mode conversion.

Verification of Common-Made-Current Prediction Method Based on Imbalance Difference Model for Single-Channel Differential Signaling System 査読

Tohlu Matsushima, Osami Wada, Tetsushi Watanabe, Yoshitaka Toyota, Liuji R. Koga

2012 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) 409 - 412 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

In a differential transmission line, a large common-mode current is excited due to its asymmetry. In this paper, the authors demonstrate experimentally the common-mode current and verify the imbalance difference model that was proposed for prediction of the common-mode current reduction. Experimental results show that the reduction of common-mode current of about 20 dB is achieved by changing the position of the transmission line. In addition, the differences that are calculated using the imbalance difference model are in agreement with the measured ones within 2 dB.

DOI： 10.1109/APEMC.2012.6237956

Optimal Resistance Determination Method for RL Damper Circuits in Power Distribution Network of ICs 査読

Ryosuke Yamagata, Kengo Iokibe, Yoshitaka Toyota

2012 6TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS (CEEM' 2012) 222 - 225 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

Equivalent current source of side-channel signal for countermeasure design with analog circuit simulator 査読

Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility 806 - 811 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication. © 2012 IEEE.

DOI： 10.1109/ISEMC.2012.6351661

Power/Ground Layers with EBG Structure and Ferrite Film for Noise Suppression and Power Integrity Improvement 査読

Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs). We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for noise-suppression and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit. Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results.

On-Board Decoupling of Cryptographic FPGA to Improve Tolerance to Side-Channel Attacks 査読

Kengo Iokibe, Tetsuo Amano, Yoshitaka Toyota

2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC) 925 - 930 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules.

On-board decoupling of cryptographic FPGA to improve tolerance to side-channel attacks 査読

Kengo Iokibe, Tetsuo Amano, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility 925 - 930 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules. © 2011 IEEE.

DOI： 10.1109/ISEMC.2011.6038441

Development of equivalent circuit model with transmission line model for designing filters formed on printed circuit boards 査読

Keisuke Matsumoto, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga

IEEE International Symposium on Electromagnetic Compatibility 289 - 294 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator. ©2010 IEEE.

DOI： 10.1109/ISEMC.2010.5711287

単一のスリットセグメントへの領域分割によるプリント回路基板の電源系共振の高速解析(放送/一般)

濱上雄大, 豊田啓孝, 五百旗頭健吾, 古賀隆治

映像情報メディア学会技術報告 33 25 - 30 2009年

記述言語：日本語出版者・発行元：一般社団法人映像情報メディア学会

多層プリント回路基板の電源系共振は,グリーン関数のモード展開を適用したポート間インピーダンス解析に高速化手法を適用することで,短時間でその特性を計算することができる.この手法では,電源層にスリットを含む場合も,スリット間の電磁結合を表現するモデルを用いて共振特性が求められる.しかし,このスリットモデルの表現ではスリットが幅を持たないため,複数のスリットがある場合など,スリットの幅が電源層の大きさに影響を与える場合には計算結果が正しくなくなる可能性がある.そこで本論文では,スリット間の電磁結合を表現するため,結合マイクロストリップ線路から求めた等価回路モデルを用いて単一のスリットのみを含むスリットセグメントを構成し,これを電源系共振解析に適用することを検討した.結果として,従来モデルと同等かそれ以上の精度で電源系共振解析が可能であることが分かった.

DOI： 10.11485/itetr.33.15.0_25

Estimation of Radiated Emissions from Multilayered Printed Circuit Board by Common-Mode Antenna Model 査読

Yuli Wakaduki, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga

CEEM: 2009 5TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS 242 - + 2009年

De-embedding of Board Parasitics with T-parameters for S-parameter Measurements of Integrated Circuits on PCB-Examinations in One-port Measurements 査読

Kazuki Maeda, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga

CEEM: 2009 5TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS 246 - 249 2009年

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