研究者詳細 - 豊田　啓孝

論文 - 豊田　啓孝

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Differential-skew mitigation by rotating meshed ground

Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota

2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility, EMC/APEMC 2018 31 2018年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

The asymmetry, or imbalance, of a differential-transmission-line pair over a meshed ground plane depending on their position leads to the differential skew. This study is focused on the angle between the differential-transmission-line pair and the meshed ground to investigate the angle dependence of differential skew. In a full-wave simulation after preliminary evaluation by a simple model, it is found that the differential skew does not depend on the position of the differential transmission lines to the pattern of the meshed ground and keeps a comparatively small value at the rotation angle around 30°.

DOI： 10.1109/ISEMC.2018.8394024

Optimum rotation angle for mitigating differential skew induced by glass cloth in PCBs

C. Wang, K. Iokibe, Y. Toyota

2018 International Conference on Electronics Packaging and iMAPS All Asia Conference, ICEP-IAAC 2018 328 - 332 2018年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

In high speed signal transmissions, glass cloth of the dielectric in printed circuit boards can cause a differential skew. It has been reported that the differential skew is mitigated when the angle between the differential transmission lines and the thread of the glass cloth is around 10°. However, the angle dependence between 10° and 45° and the optimum angle have not yet been investigated. This study focuses on the angle between the trace of the differential transmission lines and the thread of the glass cloth to investigate the angle dependence of the differential skew. We conducted a preliminary evaluation by analytical estimation of the phase delay difference in the differential transmission lines using our simple glass-cloth model. In a full-wave simulation, it was confirmed that the optimum angle between the threads of the glass cloth and the traces of the differential transmission lines is around 40°.

DOI： 10.23919/ICEP.2018.8374316

グラウンド端に近接した差動伝送線路を対象とした平衡度不整合モデルに基づくコモンモード電流低減量予測法の検証査読

松嶋徹, 渡辺哲史, 豊田啓孝, 古賀隆治, 和田修己

エレクトロニクス実装学会誌 21 ( 2 ) 178 - 185 2018年3月

記述言語：日本語掲載種別：研究論文（学術雑誌）出版者・発行元：一般社団法人エレクトロニクス実装学会

プリント配線板の近接グラウンド幅が変化する差動伝送線路では，線路がグラウンド端に寄るなどの非対称構造によりコモンモード放射が発生する。本論文では，線路が近接グラウンド端近傍に配線されている差動伝送線路を対象に，コモンモード放射の発生量を予測するための平衡度不整合モデルの精度を検証した。放射に最も寄与する全ての導体を同相に流れる2次コモンモード電流に着目し，近接グラウンド端からの距離が異なる試験基板を用いて，平衡度不整合モデル，実験，3次元電磁界解析により2次コモンモード電流変化量を比較した。その結果，提案する平衡度不整合モデルは最大3 dBの誤差で実験および3次元電磁界解析の結果と一致した。

DOI： 10.5104/jiep.21.178

Identification of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis

Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

2018 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE) 439 - 444 2018年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

ノイズ源振幅変調と相関解析に基づく放射源デバイス毎の電磁妨害波放射強度推定

吉野慎平, 石田千晶, 五百旗頭健吾, 豊田啓孝

エレクトロニクス実装学術講演大会講演論文集 32 316 - 319 2018年

Application of PRBS for dominant source identification electromagnetic interference caused by digital integrated circuits 査読

Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota

2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017 245 - 246 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Pseudo-random binary sequence (PRBS) was applied to identify dominant noise sources of electromagnetic interference (EMI) radiated from a printed circuit board (PCB) including line driver ICs. The ICs were controlled in activation of output according to a set of PRBSs that varied amplitude of switching current generated in the ICs and also changes the strength of EMI. Correlation coefficients between the temporal variation of conducted EMI strength and PRBS were examined. Results showed that PRBS has a potential to identify dominant noise sources of EMI.

DOI： 10.1109/ICCE-China.2017.7991087

Signal-to-noise ratio measurements of side-channel traces for establishing low-cost countermeasure design 査読

Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota, Toshiaki Teshima

2017 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2017 93 - 95 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

Improving the countermeasures against side-channel attacks (SCAs) increases the cost of both designing the countermeasures and evaluating SCA resistance. This may force cryptographic ICs to remain vulnerable. The increased cost is due to an indispensable procedure where a large number of side-channel traces need to be analyzed in order to evaluate the SCA resistance. In this work, a low-cost method to design and evaluate countermeasures using the signal-to-noise ratio (SNR) of side-channel traces as design and evaluation criteria is proposed. The method combines two existing methods: A prediction method of correlation coefficients between side-channel traces and a power model based on the SNR of the side-channel traces, and an estimation method of the number of traces needed to disclose the secret key based on the correlation coefficients. We construct a method to measure the SNR of side-channel traces and validate it for the design and evaluation criteria. In our method, the SNR is first calculated from signal and noise variances extracted from side-channel traces by increasing the number of averaging in side-channel trace measurements, and then the correlation coefficients and the number of traces for key-disclose are estimated on the basis of the calculated SNR. We confirmed that the estimated correlation coefficient and the number of traces for key-disclose were in good agreement with the corresponding measured ones. This result demonstrates that the proposed method can accurately measure the SNR of side-channel traces.

DOI： 10.1109/APEMC.2017.7975433

Miniaturization of planar EBG structure using dual power planes 査読

Xingxiaoyu Lin, Yoshitaka Toyota, Kengo Iokibe, Toshiyuki Kaneko

2017 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2017 241 - 243 2017年7月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

The miniaturization of unit cells in planar electromagnetic bandgap (EBG) structures has been difficult because the stopband frequency depends on the unit-cell size. To solve this problem, we developed an EBG structure that uses two power planes (dual power plane: DPP) with the addition of a capacitive coupling element. This enables us to easily enlarge the capacitance formed in the unit cell and achieve miniaturization with a stopband frequency of interest. Using full-wave simulation, we tested a 2-mm-square (4-mm2) unit cell of the DPP-EBG structure and measured a stopband frequency around 2.4 GHz.

DOI： 10.1109/APEMC.2017.7975472

振幅変調したスイッチング電流とEMI測定の相関係数に基づくノイズ源推定〜ラインドライバICを用いた原理検証〜

石田千晶, 五百旗頭健吾, 豊田啓孝

エレクトロニクス実装学術講演大会講演論文集 31 311 - 314 2017年

Optimal Design of Vialess Open-stub EBG structure for Power-bus Noise Reduction 査読

Kohtaro Okimoto, Kengo Iokibe, Yoshitaka Toyota, Koichi Kondo, Shigeyoshi Yoshida, Toshiyuki Kaneko

2016 IEEE CPMT SYMPOSIUM JAPAN (ICSJ) 243 - 246 2016年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

To overcome the intra EMC problems in wireless communications, electromagnetic bandgap (EBG) structures can be used to effectively reduce power-bus noise. We previously proposed a vialess open-stub EBG structure. However, it still has the intrinsic disadvantage of a narrow stopband because it uses the open-stub's resonance. Thus, this paper aims to optimize the structural parameters of the vialess open-stub EBG structure to sufficiently suppress power-bus noise in a wider stopband. The structural parameters to determine the noise-reduction performance of the vialess open-stub EBG structure are the branch width rob, the stub width w(s), and the unit-cell length alpha. Rectangular power buses were designed as test vehicles through the analytical approach and used to evaluate the stopband expansion and the noise suppression in the stopband in a full wave simulation. The transmission characteristics showed that, after w(b), W-s, and a are optimized, the stopband is expanded from 0.61 GHz (2.23-2.84 GHz) to 1.56 GHz (2.20-3.76 GHz). In addition, an optimized structure was made that reduced the amount of noise by approximately 10 dB.

Design Methodology of Tightly Coupled Asymmetrically Tapered Bend for High-density Mounting in Differential Transmission Lines 査読

Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota

2016 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) 463 - 465 2016年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

The bend in a pair of differential transmission lines on printed circuit boards causes a path difference, which leads to mode conversion due to the phase difference. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion. In this paper, we propose a design methodology of our tightly coupled asymmetrically tapered bend that limits the bend structure within the area of the original classic bend for high-density mounting. We also evaluated the 45-degree-angle bend formed based on our design methodology and found that the methodology helps improve or maintain its transmission characteristics compared to those of the classic bend.

Security simulation against side-channel attacks on Advanced Encryption Standard circuits based on equivalent circuit model 査読

Kengo Iokibe, Kazuhiro Maeshima, Tetsushi Watanabe, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility 2015- 224 - 229 2015年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

DOI： 10.1109/ISEMC.2015.7256163

岡山大学大学院自然科学研究科産業創成工学専攻光電磁波工学研究室

豊田啓孝

エレクトロニクス実装学会誌 18 ( 4 ) 279 - 279 2015年

Reduction methods of power supply noise due to power distribution network resonance in ICs 査読

Kengo Iokibe, Yoshitaka Toyota

Journal of Japan Institute of Electronics Packaging 18 ( 5 ) 344 - 347 2015年

Analysis on equivalent current source of AES-128 circuit for HD power model verification

Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility 2014-December 302 - 305 2014年12月

掲載種別：研究論文（国際会議プロシーディングス）

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

Suppression of mode conversion by decreasing path difference by using an asymmetrically tapered bend in differential transmission lines

Shohei Kan, Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility 2014- 129 - 132 2014年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

Guard trace with periodic structure for reducing common-mode radiation and maintaining signal integrity

Yuho Terai, Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility 2014- 545 - 548 2014年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

Modal equivalent circuit of bend discontinuity in differential transmission lines

Yoshitaka Toyota, Shohei Kan, Kengo Iokibe

IEEE International Symposium on Electromagnetic Compatibility 2014- 117 - 120 2014年12月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

Ferrite-covered open stub as lossy resonator filter for suppressing noise propagation in power bus 査読

Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

IEEE International Symposium on Electromagnetic Compatibility 765 - 769 2014年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

DOI： 10.1109/EMCEurope.2014.6931007

Investigation in burst pulse injection method for fault based cryptanalysis 査読

Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility 2014- ( September ) 743 - 747 2014年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

DOI： 10.1109/ISEMC.2014.6899067

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