論文 - 豊田　啓孝

Investigation of relationship between learning amount and interval solution range in multi-objective optimal design using ANN model

Shohei Kan, Masaki Himuro, Ryo Maekawa, Kengo Iokibe, Yoshitaka Toyota

IEICE Transactions on Communications   1 - 9   2025年

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掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.23919/transcom.2024mcp0008

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Identification of Dominant Side-Channel Information Leaking Mechanism Induced by Split Ground Planes

Kengo Iokibe, Kohei Shimoda, Masaki Himuro, Yoshitaka Toyota

IEICE Transactions on Communications   E107-B ( 12 )   852 - 860   2024年12月

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掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.23919/transcom.2024cei0010

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Derivation of Target Transfer Function in Simulated IC Switching Current to Design PCB Secure Against Side-Channel Attack

Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota

2024 International Symposium on Electromagnetic Compatibility – EMC Europe   51 - 56   2024年9月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope59828.2024.10722159

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Identification of Internal Impedance of Brush Motor in Operation Using AMN

Akito Mashino, Shohei Kan, Kengo Iokibe, Yoshitaka Toyota

2024 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI)   430 - 435   2024年8月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi49824.2024.10705536

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Measured Traces Reduction Using SNR of Leakage for Tolerance Evaluation to Deep Learning-based Side-channel Attack

Tatsuya Sakagami, Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota

2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa)   2024年5月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10585228

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An Algorithm to Find Interval Solution Ranges and Its Use to Improve Prediction Accuracy in Multi-Objective Optimal Design

Ryo Maekawa, Shohei Kan, Masaki Himuro, Akito Mashino, Kengo Iokibe, Yoshitaka Toyota

2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa)   2024年5月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10584970

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Tolerance Evaluation Against Deep Learning Side-Channel Attack on AES in Automotive Microcontroller With Uncertain Leakage Model

Masaki Himuro, Naoto Kawahara, Yoshiyuki Amanuma, Kengo Iokibe, Yasuyuki Nogami, Yoshitaka Toyota

2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa)   2024年5月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10584961

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Challenges in Feasible Simulation of Side-Channel Attack Resistance for Cryptographic Hardware

Kengo Iokibe, Masaki Himuro, Yoshitaka Toyota

2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa)   2024年5月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10585053

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Field-And-Circuit Co-Analysis of Mode Conversion Caused by Continuous Imbalance Factor Changes in Three-Conductor System

Kohno Kazuto, Kanao Sho, Iokibe Kengo, Toyota Yoshitaka

IEICE Proceeding Series   82   70 - 73   2024年5月

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記述言語：英語   出版者・発行元：The Institute of Electronics, Information and Communication Engineers  

The direct connection of a micro strip line (MSL)to coupled lines causes a mode transformation that is
proportional to the difference in the equilibria of the lines,
which can be represented by the equilibrium mismatch model.
In this paper, we show that the mode conversion can be
accurately represented by using the staircase approximation to
represent the continuously varying unbalance coefficient as the
distance between the coupled lines and the system ground is
varied. When the coupled lines are placed perpendicular to the
system ground, full-wave calculations show that mode
conversion occurs as the distance between the coupled lines and
the system ground changes. This mode transformation is
represented using an unbalance mismatch model utilizing field
and circuit co-analysis in the commercial simulator HFSS. The
continuous variation of the unbalance factor is represented by
a staircase approximation, and by increasing the number of
steps in the staircase approximation, the peak value of the
spectrum of the DM voltage generated by the common-mode
resonance approaches the value obtained in the full-wave
calculation.

DOI： 10.34385/proc.82.monpm2c.3

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Effective EMI Suppression Procedure Using RL Snubbers for Automotive Brush Motor Systems 査読

Shohei Kan, Zhenhong Xu, Akito Mashino, Kengo Iokibe, Yoshitaka Toyota

IEEE Letters on Electromagnetic Compatibility Practice and Applications   2024年2月

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LEMCPA.2024.3366881

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Triangular Pulse-Based IC Switching Current Model Using Multiple Regression Analysis for Fast Side-Channel Attack Prediction

Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota

IEEE Transactions on Electromagnetic Compatibility   1 - 12   2024年

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掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.1109/temc.2023.3345883

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Conducted Noise Prediction for DC–DC Converter by Noise Source Model Accounting for Switching Fluctuation 査読

Shuqi Zhang, Kengo Iokibe, Yoshitaka Toyota

IEEE Transactions on Electromagnetic Compatibility   11 ( 11 )   691 - 696   2023年11月

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TEMC.2023.3236674

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Prediction Accuracy Improvement of Side-channel Information Leakage by Using EM-Circuit Co-simulation of PDN with Filters

Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota

2023 International Symposium on Electromagnetic Compatibility – EMC Europe   2023年9月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope57790.2023.10274220

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Multi-Objective Design of Filter Installed in Brush Motor by Artificial Neural Network Accounting for Cable Length

Shohei Kan, Norikazu Takahashi, Masaki Himuro, Akito Mashino, Kengo Iokibe, Yoshitaka Toyota

2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI)   2023年7月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241637

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Experimental Investigation of Side-Channel Information Leakage from Printed Circuit Board with Split Ground Planes

Kengo Iokibe, Kohei Shimoda, Masaki Himuro, Yoshitaka Toyota

2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI)   2023年7月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241643

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損失を有する共振器型フィルタによる平行平板共振抑制における放射要因分解に基づく不要電磁放射評価

金尾 奨, 五百旗頭 健吾, 豊田 啓孝

電子情報通信学会論文誌B 通信   J106-B ( 7 )   400 - 402   2023年7月

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記述言語：日本語   出版者・発行元：電子情報通信学会  

損失を有する共振器型フィルタは，回路基板の平行平板共振抑制時におけるオープンスタブ構造からの不要放射が懸念される．本論文では，放射要因ごとに分解したモデルを用いて共振抑制時の放射を評価した結果，当該構造からの放射増は無視できる程度と判明した．

DOI： 10.14923/transcomj.2022bll0005

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Artificial-Voice-Based Conversational Lecture Video Clips for Flipped Classroom

Kazuhiro Umetani, Yoshitaka Toyota, Masataka Ishihara, Eiji Hiraki

2023 IEEE 32nd International Symposium on Industrial Electronics (ISIE)   1 - 7   2023年6月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/isie51358.2023.10228017

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Prediction of Conducted Emissions from Various DC-DC Converters by Using Two-Port Noise-Source Equivalent-Circuit Model

Yoshitaka Toyota, Yanyu Jin, Shuqi Zhang, Kengo Iokibe

2023 Joint Asia-Pacific International Symposium on Electromagnetic Compatibility and International Conference on ElectroMagnetic Interference & Compatibility (APEMC/INCEMIC)   1 - 4   2023年5月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc57782.2023.10217366

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Unintentional radiated emissions from unshielded twisted pair cable attributed to twist structure 査読

Shun Igarashi, Daisuke Miyawaki, Suguru Yamagishi, Ichiro Kuwayama, Kengo Iokibe, Yoshitaka Toyota

IEICE Communications Express   11 ( 11 )   691 - 696   2022年11月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/comex.2022xbl0101

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A Load-variable Noise-source Equivalent Circuit Model for DC-DC Converter Considering Cubic Spline Interpolation 査読

Shuqi Zhang, Kengo Iokibe, Yoshitaka Toyota

11th IEEE CPMT Symposium Japan (ICSJ 2022)   154 - 157   2022年11月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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Co-simulation Analysis of Mode Conversion Due to Imbalance difference by Structural Discontinuity 査読

Sho Kanao, Hiroaki Iwasaki, Kengo Iokibe, Yoshitaka Toyota

2022 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC 2022)   2022年9月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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FPGA Switching Current Modeling Based on Register Transfer Level Logic Simulation for Power Side-channel Attack Prediction

Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility   2022-September   172 - 177   2022年9月

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We investigated the prediction of side-channel leak-age on the power delivery network (PDN) outside a cryptographic IC. To predict the leakage, it is necessary to estimate the switching current caused by the switching activity. So far, high temporal resolution estimation based on gate-level logic simulation has been proposed, but due to the decoupling property of the PDN, the switching current leaking out of the IC chip attenuates signif-icantly. Therefore, this paper calculates the mean of the switching currents over the clock period based on register transfer level (RTL) logic simulation, and then approximates it into a triangle waveform. This approach enables us to simulate the switching current faster than with gate-level simulation. In addition, the simulation time is further shortened by calculating the switching current only to the targeted round of a cryptographic algorithm (AES). Switching currents of the previous rounds were given as statistical models with the same sample mean and variance as the targeted round. As a result of simulating the switching current of an FPGA with the proposed method, we were able to obtain the low-order harmonic components of the current in almost the same magnitude as the gate-level simulation. We also simulated correlation power analysis (CPA) results for the printed circuit board on which the FPGA with the AES circuit was mounted, and found that the proposed method could predict the dynamic power supply voltage observed on the board and CPA results with sufficient accuracy.

DOI： 10.1109/EMCEurope51680.2022.9900948

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Suppression of Power-Bus Resonance and Unintentional Radiation by Lossy Resonator Filter

Sho Kanao, Shuhei Kodama, Kengo Iokibe, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility   2022-September   361 - 365   2022年9月

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担当区分：最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

We previously proposed a lossy resonator filter to suppress the parallel-plate resonance of printed circuit boards (PCBs). The filter consists of an open stub (a quarter-wavelength resonator) covered with a ferrite thin film (inducing a small loss). This paper evaluates the effect of the small loss by investigating the suppression of parallel-plate resonance and the unintentional radiation from a PCB with or without the ferrite thin film. An open stub can work as a narrow-band filter but may also work as an antenna and radiate unintentionally, which causes a secondary noise problem at frequencies other than the target frequency of 2.4 GHz. The electric field distribution between the parallel plates and the total radiated power were thus investigated to validate the effect of the small loss of the lossy resonator filter. The results showed that the total radiated power from parallel plates resonating at 2.4 GHz was suppressed by about 12 dB by using open stubs with a resonant frequency of 2.4 GHz, regardless of the presence or absence of the ferrite thin film. At 2.54 GHz, however, the open stubs without ferrite increased the radiated power by about 10 dB, whereas those with ferrite did not increase it at all. It was thus found that the lossy resonator filter could suppress not only the parallel-plate resonance but also unintentional radiation around the target frequency without causing any other problems.

DOI： 10.1109/EMCEurope51680.2022.9901324

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Multi-Objective Design of Filter Installed in Brush Motor by Preference Set-based Design Accounging for Cable Length 査読

Shohei Kan, Ryuta Nakanishi, Zhenhong Xu, Kengo Iokibe, Yoshitaka Toyota

2022 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2022   595 - 595   2022年8月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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A Study for Improving Signal-to-Noise Ratio Measurement Method in Side-Channel Information Leakage of Cryptographic Hardware 査読

Kengo Iokibe, Masaki Himuro, Yoshitaka Toyota

2022 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2022   294 - 298   2022年8月

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Once the signal-tu-noise ratio (SNR) of the side- channel (SC) leakage trace is known, the intensity of the SC information leakage source inside the integrated circuit (IC) can be identified from measurements carried out outside the IC, SNR observation of SC leakage can also make it possible to set quantitative design targets to achieve the demanded leakage intensity. We discuss an improved method for identifying the SNR of SC leakage traces composed of multiple transient responses of IC switching current. The IC switching current repeatedly occurs as the IC runs the cryptographic operation since the cryptographic algorithm repeats a set of sub-operations. The method was applied to simulated and measured leakage traces to eliminate the effect of transient IC switching current caused before the target sub-operation was processed. As a result, a transient component more extensive than the signal component of side-channel analysis was identified in the decoupling capacitor configuration, where the convergence of the transient response is slow. In addition, the correlation coefficients obtained by the correlation power analysis, a major side-channel analysis method, were plotted as a function of SNR, and the plot of the simulated traces agreed with the theoretical curve. On the other hand, some errors remained in the plot of the measured traces.

DOI： 10.1109/EMCSI39492.2022.9889660

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Detection of AC magnetic field distribution using optical magnetometer with digital micro-mirror device 招待 査読

Shuji Taue, Takumi Tanaka, Hiroto Suzuki, Yoshitaka Toyota

Optical Technology and Measurement for Industrial Applications Conference 2022   2022年4月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPIE  

DOI： 10.1117/12.2660186

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An Approach to Identify Noise-source Parameters of DC-DC Converter and Predict Conducted Emissions with Different Loads 査読

Shuqi Zhang, Kengo Iokibe, Yoshitaka Toyota

IEEE Letters on Electromagnetic Compatibility Practice and Applications   1 - 1   2022年

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.1109/lemcpa.2022.3228199

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Common-mode Current Reduction by Applying Mode-conversion Suppression Technique to Power Delivery Network as Side-channel Attack Countermeasure

Md. Ashraful Islam, Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota

2021 International Conference on Computer, Communication, Chemical, Materials and Electronic Engineering (IC4ME2)   2021年12月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ic4me253898.2021.9768521

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Mode Conversion Suppression at the Discontinuity point on Power Delivery Network for Side-channel Attack Countermeasure

Md. Ashraful Islam, Masaki Himuro, Kengo Iokibe, and Yoshitaka Toyota

2021年12月

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担当区分：最終著者   記述言語：英語  

A Study for Low Calculation Cost Side-Channel Resistance Prediction Based on Transfer Impedance of Leakage Path 査読

Kengo Iokibe, Masaki Himuro, Yoshitaka Toyota

2021 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)   2021年9月

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担当区分：最終著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc49932.2021.9597127

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An Approach to Predicting Conducted Noise from DC-DC Converter Accounting for Switching Fluctuation 査読

Shuqi Zhang, Kengo Iokibe, Yoshitaka Toyota

2021 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)   2021年9月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc49932.2021.9596844

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Noise-Source Parameter Identification Considering Switching Fluctuation of DC-DC Converter 査読

Shuqi Zhang, Taishi Uematsu, Kengo Iokibe, Yoshitaka Toyota

2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium   186   2021年7月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper proposes noise-source parameter identification of the noise-source equivalent-circuit model for predicting conducted noise while considering the switching fluctuation of a DC/DC converter. We decomposed measured conducted noise into ripple noise, turn-on spike noise, and turn- off spike noise to prevent the accuracy degradation in the parameter identification. The predicted conducted noise spectra show the error with the measurement was within 3 dB up to 200 MHz, which is more accurate than that in our previous study.

DOI： 10.1109/emc/si/pi/emceurope52599.2021.9559182

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Efficient Estimation of Noise Suppression Amount in Power Bus with Decoupling Capacitors Using Lossy Resonator Filters 査読

Sho Kanao, Kengo Iokibe, Yoshitaka Toyota

2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium   323   2021年7月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To estimate the amount of noise suppressed by lossy resonator filters (LRFs) in a power bus with a decoupling capacitor, we used an equivalent circuit model considering the effect of the capacitor to know the suppression mechanism using the LRF. The discrepancy between the model and a full-wave simulation was approximately 2 dB.

DOI： 10.1109/emc/si/pi/emceurope52599.2021.9559213

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Practical Design Methodology of Mode-Conversion-Free Tightly Coupled Asymmetrically Tapered Bend for High-Density Differential Wiring 査読

WANG Chenyu, IOKIBE Kengo, TOYOTA Yoshitaka

IEICE Transactions on Communications   E104.B ( 3 )   304 - 311   2021年3月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.</p>

DOI： 10.1587/transcom.2020ebp3056

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Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices 査読

YANO Yusuke, IOKIBE Kengo, TESHIMA Toshiaki, TOYOTA Yoshitaka, KATASHITA Toshihiro, HORI Yohei

IEICE Transactions on Communications   E104.B ( 2 )   178 - 186   2021年2月

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>Side-channel (SC) leakage from a cryptographic device chip is simulated as the dynamic current flowing out of the chip. When evaluating the simulated current, an evaluation by comparison with an actual measurement is essential; however, it is difficult to compare them directly. This is because a measured waveform is typically the output voltage of probe placed at the observation position outside the chip, and the actual dynamic current is modified by several transfer impedances. Therefore, in this paper, the probe voltage is converted into the dynamic current by using an EMC macro-model of a cryptographic device being evaluated. This paper shows that both the amplitude and the SC analysis (correlation power analysis and measurements to disclosure) results of the simulated dynamic current were evaluated appropriately by using the EMC macro-model. An evaluation confirms that the shape of the simulated current matches the measured one; moreover, the SC analysis results agreed with the measured ones well. On the basis of the results, it is confirmed that a register-transfer level (RTL) simulation of the dynamic current gives a reasonable estimation of SC traces.</p>

DOI： 10.1587/transcom.2020ebp3015

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Suppression of Mode Conversion at Ethernet Connector by using Modal-Equivalent Circuit Model based on Imbalance Matching 査読

Islam Md. Ashraful, Iokibe Kengo, Toyota Yoshitaka

電気学会論文誌． Ａ   140 ( 12 )   586 - 592   2020年12月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電気学会  

<p>When a shielded-twisted-pair (STP) cable is connected with a printed circuit board (PCB) via an Ethernet (RJ45) connector, mode conversion between primary- and secondary-common modes occurs at the connector section due to their structural difference that causes the difference in the imbalance factor of the transmission line. In this paper, we investigate the suppression of the mode conversion at the connector section by using a modal-equivalent circuit model based on imbalance matching. We focus on improving the PCB pattern below the shielded Ethernet connector by placing a copper layer on the PCB surface, and the inadequate shielding at the connector section by soldering and wrapping with copper tape. The application of this improvement based on imbalance matching at the connector section makes the imbalance factor of the connector section closer to that of the cable section and results in the suppression of the mode conversion. Based on the concept of imbalance matching, we confirmed the effect of the shield-improved connector with an improved PCB pattern on the suppression of the mode conversion at the connector section through circuit simulation and measurement, and it was validated that the circuit simulation results obtained from the modal-equivalent circuit model agree well with the measurement results.</p>

DOI： 10.1541/ieejfms.140.586

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M系列変調TDRによる有線ネットワークのインピーダンス不連続点特定の基礎検討 査読

亀山大樹, 五百旗頭健吾, 豊田啓孝

電子情報通信学会技術研究報告(Web)   120 ( 20(EMCJ2020 5-10) )   2020年9月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/emceurope48519.2020.9245855

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Two-port Noise Source Equivalent Circuit Model for DC/DC Buck Converter with Consideration of Load Effect 査読

Shuqi Zhang, Taishi Uematsu, Kengo Iokibe, Yoshitaka Toyota

2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE   2020年9月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

As the conducted disturbance of a power converter changes with its load value, the relationship between the electromagnetic interference of the power converter and its load needs to be investigated. This work examines a 2-port equivalent circuit model for a DC/DC buck converter with consideration of the load effect. Factors that influence the model accuracy are also discussed. We used a synchronous buck converter operating under a continuous conduction mode condition to determine the load effect and evaluate the model. Results showed that the input port of the fixed-load model and load-variable model had good accuracy up to 70 MHz. We also predicted the load effect on input port noise and found that the input port noise of an 8.2-? load could be predicted from the other two load values (6.6 ? and 11.6 ?).

DOI： 10.1109/emceurope48519.2020.9245680

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Suppression of Mode Conversion Due to Asymmetric Geometry of Dense Parallel Traces in Differential-Transmission Lines 査読

Tomoya Takeuchi, Kengo Iokibe, Yoshitaka Toyota

2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE   2020年9月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Symmetry is important for differential-transmission lines, but the dense parallel traces easily break the symmetry due to coupling with the adjacent conductor, leading to mode conversion. We propose an asymmetric geometry of differential-transmission lines placed on the side of a nonadjacent conductor to suppress mode conversion and maintain signal integrity in the cases of loosely coupled and tightly coupled parallel traces. By designing the asymmetric geometry of dense differential-transmission lines by taking into account coupling with the adjacent conductor, mode conversion was successfully suppressed by decreasing the line width on the side of the non-adjacent conductor. It was also found that the asymmetric geometry can suppress mode conversion and maintain signal integrity in tightly coupled parallel traces. In loosely coupled parallel traces, on the other hand, the tightly coupled asymmetrically tapered bend we previously proposed suppresses mode conversion.

DOI： 10.1109/emceurope48519.2020.9245880

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Estimation of Power-bus Noise Suppression by Lossy Resonator Filter Using Lumped-constant Multi-ports Equivalent Circuit Model 査読

Sho Kanao, Kengo Iokibe, Yoshitaka Toyota

2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (2020 IEEE EMC+SIPI)   2020年8月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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A Study on Evaluation Board Requirements for Assessing Vulnerability of Cryptographic Modules to Side-Channel Attacks 査読

Kengo Iokibe, Tomonobu Kan, Yoshitaka Toyota

2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)   2020年7月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsi38923.2020.9191655

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Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits 査読

Wang Chenyu, Iokibe Kengo, Toyota Yoshitaka

IEICE Electronics Express   17 ( 10 )   20200101 - 20200101   2020年5月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>Asymmetry of differential transmission lines over a meshed ground plane causes differential skew, which leads to signal integrity issues. We measured to evaluate how the angle between the differential transmission lines and meshed ground (the rotation angle) affected differential skew. We also investigated the effect of the lines' position on characteristic impedance and the feasibility of high-density layout of the differential transmission lines, including the bend structure. We found that the differential skew and characteristic impedance are not significantly affected by the position of the differential transmission lines and meshed ground when the rotation angle is set to 30°, a relatively small value. Measurements showed that our design is effective.</p>

DOI： 10.1587/elex.17.20200101

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Signal-source estimation from magnetic field image obtained using atomic magnetometer and digital micro-mirror device 査読

Shuji Taue, Yoshitaka Toyota

OPTICAL REVIEW   27 ( 2 )   258 - 263   2020年4月

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC JAPAN  

Visualization of an electromagnetic field distribution is helpful for spatial evaluation of field leakage and can aid in solving inverse problems of signal-source estimation. Optical detection is more accurate and less invasive than other methods owing to a low metal content in the sensing probes and signal wires. We have previously reported optical detection of alternating magnetic fields using an alkali-metal atomic magnetometer. In this study, we have proposed a method for imaging the field in a 10 mm diameter area in the sensor head and achieved a resolution below 0.3 mm using a digital micro-mirror device. In this paper, we demonstrate the visualization of an alternating magnetic field at 70 kHz, generated using a Helmholtz coil and a 0.5-mm diameter metal wire attached to the sensor head. Both the uniform field image from the coil and the gradient field image from the wire were clearly observed. The output linearity of the magnetometer was investigated by varying the electric current applied to the coil. In addition, we performed signal-source estimation from the gradient field image. The obtained and calculated distributions were compared to estimate the position of the wire. The estimated wire depth of 1.41 mm was within the range of actual wire depths. This measurement technique has the potential for application in precise position estimation of signal sources with high sensitivity.

DOI： 10.1007/s10043-020-00591-y

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コモンモード放射シミュレーション用電流配分率算出のためのコネクタの簡易モデル構築

豊田 啓孝, 金尾 奨, 佐田野 勝水, 五百旗頭 健吾

エレクトロニクス実装学術講演大会講演論文集   34   3B4 - 3   2020年

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

<p>ケーブル-コネクタ間の平衡度不整合によるコモンモード発生、さらに、放射シミュレーションを行うには、コネクタの電流配分率を容易に算出できることが不可欠である。今回、コネクタのSパラメータから電流配分率を算出する簡易モデルを構築したのでこれを報告する。</p>

DOI： 10.11486/ejisso.34.0_3B4-03

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Design of Vialess Open-stub EBG Structure by Using Preference Set-based Design Method 査読

Yoshitaka Toyota, Sho Kanao, Kengo Iokibe

2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE   2019年9月

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2019.8871971

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AC magnetic field imaging by using atomic magnetometer and micro-mirror device 査読

Shuji Taue, Nao Arita, Yoshitaka Toyota

2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE   253 - 256   2019年9月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Visualizing an AC magnetic field distribution is valuable to evaluate spatially as signal or noise components and to estimate locations of signal sources. We propose an optical imaging technique to visualize AC magnetic field distributions. An atomic magnetometer with phase sensitive detections realize optical detections of the AC field with dividing into two axes. A digital micro-mirror device enables us to obtain the field image in 10 mm square area with sub-mm spatial resolution. As a result, bi-directional AC-field images from a fine metal-wire were obtained. The obtained images allow us to evaluate field distributions clearly. This imaging technique has a potential for spatial evaluations of AC field from electrical and electronic devices.

DOI： 10.1109/emceurope.2019.8871985

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Modifying Noise Source Amplitude Modulation Technique to Estimate Magnitude and Phase of Emissions from Individual Integrated Circuits 査読

Kengo Iokibe, Shimpei Yoshino, Yusuke Yano, Yoshitaka Toyota

2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE   2019年9月

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2019.8871562

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A Method for Optimally Designing Snubber Circuits for Buck Converter Circuits to Damp LC Resonance 査読

Yusuke Yano, Naoki Kawata, Kengo Iokibe, Yoshitaka Toyota

IEEE Transactions on Electromagnetic Compatibility   61 ( 4 )   1217 - 1225   2019年8月

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

A method for optimally designing RL and RC snubber circuits is presented to reduce the electromagnetic interference caused by parasitic LC resonance. The Q factor of the resonance is used as the design criteria. Optimum snubber parameters are determined analytically and uniquely by using a simplified equivalent circuit of the resonant loop and deriving an analytical formula for the Q factor as a function of the snubber parameters. The optimally designed snubbers can adequately adjust the Q factor to any design target. They can also minimize the increases in the negative effects of the snubbers, i.e., overshoot and power loss. The method was applied to RL and RC snubbers to be added to a synchronous buck converter. The effects of the snubbers were reproduced by simulation program with integrated circuit emphasis ( SPICE) simulation to validate the method from the perspective of resonance damping, overshoot, and power loss. The results showed that the damping effects obtained with the optimized snubbers met the Q factor design targets. They also demonstrate that the parameters are optimum in terms of suppressing overshoot and power loss. These results indicate that the method is suitable for optimizing RL and RC snubbers to damp parasitic LC resonance.

DOI： 10.1109/temc.2018.2841424

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Suppression of Mode Conversion by Improved Shielding Effect of Ethernet Cable Connector Based on Imbalance Factor Matching

Md. Ashraful Islam, Ryota Irishika, Kengo Iokibe, Yoshitaka Toyota

International Conference on Computer, Communication, Chemical, Materials and Electronic Engineering (IC4ME2)   2019年7月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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Parameter Identification Based on Measurement and EMI Prediction of Noise-source Equivalent Circuit Model for Power Converters 招待

Yoshitaka Toyota

International Conference on Computer, Communication, Chemical, Materials and Electronic Engineering (IC4ME2)   2019年7月

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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Randomly Shifted Mesh Position of Meshed Ground for High-Density Mounting in FPCs 査読

Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota

2019 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity (2019 IEEE EMC+SIPI)   2019年7月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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Reduction Mechanism of Differential-Mode Crosstalk between Adjacent Differential Pairs with Periodic Structure 査読

Chenyu Wang, Hiroaki Takeda, Kengo Iokibe, Yoshitaka Toyota

2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sapporo (EMC Sapporo & APEMC 2019)   2019年7月

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担当区分：筆頭著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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Suppression of Mode Conversion by Improving Shielding Around Ethernet Connector with Imbalance Matching 査読

Md. Ashraful Islam, Ryota Irishika, Kengo Iokibe, Yoshitaka Toyota

2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sapporo (EMC Sapporo & APEMC 2019)   2019年6月

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担当区分：最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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Improvement of Prediction Accuracy of Noise-source Equivalent-circuit Model Based on Parameter Extraction by Port Voltage/Current Measurement 査読

Taishi Uematsu, Yuhei Osaki, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota

2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sapporo (EMC Sapporo & APEMC 2019)   2019年6月

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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Experimental Identification of Relationship between Leakage Trace SNR and Correlation Coefficient in Differential Power Analysis 査読

Yusuke Yano, Toshiaki Teshima, Kengo Iokibe, Yoshitaka Toyota

2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sapporo(EMC Sapporo & APEMC 2019)   2019年6月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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ノイズ源振幅変調と相関解析に基づくノイズ源IC毎の電磁妨害波強度推定 査読

吉野 慎平, 五百旗頭 健吾, 矢野 佑典, 豊田 啓孝

エレクトロニクス実装学会誌   22 ( 3 )   218 - 225   2019年5月

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担当区分：最終著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

<p>EMI対策および評価コストの削減を目的として，ノイズ源IC毎の放射強度推定法を提案する。この手法はEMI発生要因の1つであるスイッチング電流を振幅変調し，その時の電磁妨害波の時間変化を観測することで得られるノイズ源強度比から各ICの放射強度を推定する。本論文では，プリント回路板に提案手法を適用し，遠方界放射から複数ICによる放射の強度を算出，さらにIC個別に駆動した測定結果と比較し推定精度を評価した。その結果，各ICに起因する放射が同相と見なせる場合に放射強度を高い精度で推定可能であることを示した。</p>

DOI： 10.5104/jiep.22.218

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差動配線とメッシュグラウンドのなす角に着目した差動スキュー低減 査読

王 晨宇, 五百旗頭 健吾, 豊田 啓孝

電子情報通信学会論文誌 B   J102-B ( 3 )   228 - 236   2019年3月

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担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

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Identification of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis

Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

IEEE International Symposium on Electromagnetic Compatibility   2018-August   439 - 444   2018年10月

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掲載種別：研究論文（国際会議プロシーディングス）  

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

DOI： 10.1109/EMCEurope.2018.8485011

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A Study of Installation Location and Mechanism to Suppress Power-Bus Resonance Efficiently Using Lossy Resonator Filters

Sho Kanao, Kengo Iokibe, Yoshitaka Toyota

2018 International Symposium on Electromagnetic Compatibility (EMC EUROPE)   2018年8月

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2018.8485052

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Extension of signal-to-noise ratio measurement method to byte-by-byte side-channel attack

Kengo Iokibe, Toshiaki Teshima, Yusuke Yano, Yoshitaka Toyota

2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility, EMC/APEMC 2018   745 - 748   2018年6月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Signal-to-noise ratio (SNR) of side-channel traces leaked from cryptographic ICs can be a candidate of system-designer-friendly design index in security evaluation against the side-channel attack (SCA). A method to calculate SNR of side-channel traces from measured side-channel traces was proposed for the scenario of the byte-by-byte attack on AES cryptographic circuits. The proposed method was a simple extension of an SNR calculation method for the brute force attack scenario proposed in a previous study. Measured SNRs according to the methods were validated by comparison with analytical formulas. Results suggested that the proposed method could provide SNRs of side-channel traces accurately.

DOI： 10.1109/ISEMC.2018.8393880

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Differential-skew mitigation by rotating meshed ground

Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota

2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility, EMC/APEMC 2018   31   2018年6月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The asymmetry, or imbalance, of a differential-transmission-line pair over a meshed ground plane depending on their position leads to the differential skew. This study is focused on the angle between the differential-transmission-line pair and the meshed ground to investigate the angle dependence of differential skew. In a full-wave simulation after preliminary evaluation by a simple model, it is found that the differential skew does not depend on the position of the differential transmission lines to the pattern of the meshed ground and keeps a comparatively small value at the rotation angle around 30°.

DOI： 10.1109/ISEMC.2018.8394024

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Optimum rotation angle for mitigating differential skew induced by glass cloth in PCBs

C. Wang, K. Iokibe, Y. Toyota

2018 International Conference on Electronics Packaging and iMAPS All Asia Conference, ICEP-IAAC 2018   328 - 332   2018年6月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

In high speed signal transmissions, glass cloth of the dielectric in printed circuit boards can cause a differential skew. It has been reported that the differential skew is mitigated when the angle between the differential transmission lines and the thread of the glass cloth is around 10°. However, the angle dependence between 10° and 45° and the optimum angle have not yet been investigated. This study focuses on the angle between the trace of the differential transmission lines and the thread of the glass cloth to investigate the angle dependence of the differential skew. We conducted a preliminary evaluation by analytical estimation of the phase delay difference in the differential transmission lines using our simple glass-cloth model. In a full-wave simulation, it was confirmed that the optimum angle between the threads of the glass cloth and the traces of the differential transmission lines is around 40°.

DOI： 10.23919/ICEP.2018.8374316

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グラウンド端に近接した差動伝送線路を対象とした平衡度不整合モデルに基づくコモンモード電流低減量予測法の検証 査読

松嶋 徹, 渡辺 哲史, 豊田 啓孝, 古賀 隆治, 和田 修己

エレクトロニクス実装学会誌   21 ( 2 )   178 - 185   2018年3月

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

プリント配線板の近接グラウンド幅が変化する差動伝送線路では，線路がグラウンド端に寄るなどの非対称構造によりコモンモード放射が発生する。本論文では，線路が近接グラウンド端近傍に配線されている差動伝送線路を対象に，コモンモード放射の発生量を予測するための平衡度不整合モデルの精度を検証した。放射に最も寄与する全ての導体を同相に流れる2次コモンモード電流に着目し，近接グラウンド端からの距離が異なる試験基板を用いて，平衡度不整合モデル，実験，3次元電磁界解析により2次コモンモード電流変化量を比較した。その結果，提案する平衡度不整合モデルは最大3 dBの誤差で実験および3次元電磁界解析の結果と一致した。

DOI： 10.5104/jiep.21.178

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Identification of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis

Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

2018 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE)   439 - 444   2018年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

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ノイズ源振幅変調と相関解析に基づく放射源デバイス毎の電磁妨害波放射強度推定

吉野 慎平, 石田 千晶, 五百旗頭 健吾, 豊田 啓孝

エレクトロニクス実装学術講演大会講演論文集   32   316 - 319   2018年

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.11486/ejisso.32.0_316

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Application of PRBS for dominant source identification electromagnetic interference caused by digital integrated circuits 査読

Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota

2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017   245 - 246   2017年7月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Pseudo-random binary sequence (PRBS) was applied to identify dominant noise sources of electromagnetic interference (EMI) radiated from a printed circuit board (PCB) including line driver ICs. The ICs were controlled in activation of output according to a set of PRBSs that varied amplitude of switching current generated in the ICs and also changes the strength of EMI. Correlation coefficients between the temporal variation of conducted EMI strength and PRBS were examined. Results showed that PRBS has a potential to identify dominant noise sources of EMI.

DOI： 10.1109/ICCE-China.2017.7991087

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Signal-to-noise ratio measurements of side-channel traces for establishing low-cost countermeasure design 査読

Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota, Toshiaki Teshima

2017 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2017   93 - 95   2017年7月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Improving the countermeasures against side-channel attacks (SCAs) increases the cost of both designing the countermeasures and evaluating SCA resistance. This may force cryptographic ICs to remain vulnerable. The increased cost is due to an indispensable procedure where a large number of side-channel traces need to be analyzed in order to evaluate the SCA resistance. In this work, a low-cost method to design and evaluate countermeasures using the signal-to-noise ratio (SNR) of side-channel traces as design and evaluation criteria is proposed. The method combines two existing methods: A prediction method of correlation coefficients between side-channel traces and a power model based on the SNR of the side-channel traces, and an estimation method of the number of traces needed to disclose the secret key based on the correlation coefficients. We construct a method to measure the SNR of side-channel traces and validate it for the design and evaluation criteria. In our method, the SNR is first calculated from signal and noise variances extracted from side-channel traces by increasing the number of averaging in side-channel trace measurements, and then the correlation coefficients and the number of traces for key-disclose are estimated on the basis of the calculated SNR. We confirmed that the estimated correlation coefficient and the number of traces for key-disclose were in good agreement with the corresponding measured ones. This result demonstrates that the proposed method can accurately measure the SNR of side-channel traces.

DOI： 10.1109/APEMC.2017.7975433

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Miniaturization of planar EBG structure using dual power planes 査読

Xingxiaoyu Lin, Yoshitaka Toyota, Kengo Iokibe, Toshiyuki Kaneko

2017 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2017   241 - 243   2017年7月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The miniaturization of unit cells in planar electromagnetic bandgap (EBG) structures has been difficult because the stopband frequency depends on the unit-cell size. To solve this problem, we developed an EBG structure that uses two power planes (dual power plane: DPP) with the addition of a capacitive coupling element. This enables us to easily enlarge the capacitance formed in the unit cell and achieve miniaturization with a stopband frequency of interest. Using full-wave simulation, we tested a 2-mm-square (4-mm2) unit cell of the DPP-EBG structure and measured a stopband frequency around 2.4 GHz.

DOI： 10.1109/APEMC.2017.7975472

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振幅変調したスイッチング電流とEMI測定の相関係数に基づくノイズ源推定〜ラインドライバICを用いた原理検証〜

石田 千晶, 五百旗頭 健吾, 豊田 啓孝

エレクトロニクス実装学術講演大会講演論文集   31   311 - 314   2017年

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.11486/ejisso.31.0_311

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Optimal Design of Vialess Open-stub EBG structure for Power-bus Noise Reduction 査読

Kohtaro Okimoto, Kengo Iokibe, Yoshitaka Toyota, Koichi Kondo, Shigeyoshi Yoshida, Toshiyuki Kaneko

2016 IEEE CPMT SYMPOSIUM JAPAN (ICSJ)   243 - 246   2016年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To overcome the intra EMC problems in wireless communications, electromagnetic bandgap (EBG) structures can be used to effectively reduce power-bus noise. We previously proposed a vialess open-stub EBG structure. However, it still has the intrinsic disadvantage of a narrow stopband because it uses the open-stub's resonance. Thus, this paper aims to optimize the structural parameters of the vialess open-stub EBG structure to sufficiently suppress power-bus noise in a wider stopband. The structural parameters to determine the noise-reduction performance of the vialess open-stub EBG structure are the branch width rob, the stub width w(s), and the unit-cell length alpha. Rectangular power buses were designed as test vehicles through the analytical approach and used to evaluate the stopband expansion and the noise suppression in the stopband in a full wave simulation. The transmission characteristics showed that, after w(b), W-s, and a are optimized, the stopband is expanded from 0.61 GHz (2.23-2.84 GHz) to 1.56 GHz (2.20-3.76 GHz). In addition, an optimized structure was made that reduced the amount of noise by approximately 10 dB.

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Design Methodology of Tightly Coupled Asymmetrically Tapered Bend for High-density Mounting in Differential Transmission Lines 査読

Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota

2016 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)   463 - 465   2016年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The bend in a pair of differential transmission lines on printed circuit boards causes a path difference, which leads to mode conversion due to the phase difference. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion. In this paper, we propose a design methodology of our tightly coupled asymmetrically tapered bend that limits the bend structure within the area of the original classic bend for high-density mounting. We also evaluated the 45-degree-angle bend formed based on our design methodology and found that the methodology helps improve or maintain its transmission characteristics compared to those of the classic bend.

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Security simulation against side-channel attacks on Advanced Encryption Standard circuits based on equivalent circuit model 査読

Kengo Iokibe, Kazuhiro Maeshima, Tetsushi Watanabe, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility   2015-   224 - 229   2015年9月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

DOI： 10.1109/ISEMC.2015.7256163

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岡山大学大学院自然科学研究科産業創成工学専攻光電磁波工学研究室

豊田 啓孝

エレクトロニクス実装学会誌   18 ( 4 )   279 - 279   2015年

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記述言語：日本語   出版者・発行元：The Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.18.279

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Reduction methods of power supply noise due to power distribution network resonance in ICs 査読

Kengo Iokibe, Yoshitaka Toyota

Journal of Japan Institute of Electronics Packaging   18 ( 5 )   344 - 347   2015年

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.18.344

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Analysis on equivalent current source of AES-128 circuit for HD power model verification

Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility   2014-December   302 - 305   2014年12月

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掲載種別：研究論文（国際会議プロシーディングス）  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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Suppression of mode conversion by decreasing path difference by using an asymmetrically tapered bend in differential transmission lines

Shohei Kan, Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility   2014-   129 - 132   2014年12月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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Guard trace with periodic structure for reducing common-mode radiation and maintaining signal integrity

Yuho Terai, Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility   2014-   545 - 548   2014年12月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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Modal equivalent circuit of bend discontinuity in differential transmission lines

Yoshitaka Toyota, Shohei Kan, Kengo Iokibe

IEEE International Symposium on Electromagnetic Compatibility   2014-   117 - 120   2014年12月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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Ferrite-covered open stub as lossy resonator filter for suppressing noise propagation in power bus 査読

Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

IEEE International Symposium on Electromagnetic Compatibility   765 - 769   2014年10月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

DOI： 10.1109/EMCEurope.2014.6931007

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Investigation in burst pulse injection method for fault based cryptanalysis 査読

Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility   2014- ( September )   743 - 747   2014年9月

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

DOI： 10.1109/ISEMC.2014.6899067

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Lossy resonators for suppressing power-bus resonance of printed circuit boards 査読

Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe

IEEE Electromagnetic Compatibility Magazine   3 ( 1 )   65 - 69   2014年3月

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Power-bus resonance of printed circuit boards causes electromagnetic interference and detraction of power integrity. To suppress the power-bus resonance, we propose the application of lossy resonators in the power bus. Here, we first explain the concepts of the proposed resonators, focusing especially on the application based on the impedance characteristics. Then, we explain the full-wave simulation conducted to demonstrate that the proposed resonator effectively suppressed power-bus resonance.

DOI： 10.1109/MEMC.2014.6798799

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Investigation in Burst Pulse Injection Method for Fault Based Cryptanalysis 査読

Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   743 - 747   2014年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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電源線から侵入した外乱に起因するクロックグリッチによるFPGA誤動作事例

五百旗頭 健吾, 前島 一仁, 渡辺 哲史, 籠谷 裕人, 野上 保之, 林 優一, 豊田 啓孝, 曽根 秀昭

エレクトロニクス実装学術講演大会講演論文集   28 ( 0 )   63 - 66   2014年

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

バルク電流やバーストといった外乱注入により発生した暗号FPGAの誤動作に関して考察した。特に発生した誤動作の直接原因がクロックグリッチの場合について、まず、外乱によりFPGAのクロック配線にグリッチが重畳することを実験により検証した。次に、発生した誤動作をグリッチ付クロックをFPGAに直接与える構成において再現し、回路動作とグリッチの関係を検証した。以上の実験結果に基づき、外乱によりクロックグリッチが発生した場合の誤動作発生機構、および評価環境における誤動作発生確率を示した。

DOI： 10.11486/ejisso.28.0_63

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Improvement of linear equivalent circuit model to identify simultaneous switching noise current in cryptographic integrated circuits 査読

Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility   834 - 839   2013年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation. © 2013 IEEE.

DOI： 10.1109/ISEMC.2013.6670526

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Experimental Model Validation of Mode-conversion Sources Introduced to Modal Equivalent Circuit 査読

Kota Sejima, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Tetsushi Watanabe

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   492 - 497   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Delta h). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Delta h becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity.

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Equivalent Current Source of Side-channel Signal for Countermeasure Design with Analog Circuit Simulator 査読

Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   806 - 811   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication.

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Identification of Equivalent Current Source of Cryptographic Circuit Based on Impedance and Current Measurements at Board Level 査読

Kaoru Okamoto, Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

2012 PROCEEDINGS OF SICE ANNUAL CONFERENCE (SICE)   73 - 78   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SOC INSTRUMENT CONTROL ENGINEERS JAPAN  

Side-channel attacks are a kind of cryptanalytic attacks by means of the electric current in the range of radio frequency (RF) leaking out from a cryptographic integrated circuit (IC) and/or the electromagnetic radiation generated by the RF power current. The RF power current is caused by simultaneous switching activities of logic gates during an encryption process operated in the cryptographic IC. The RF power current is a major cause of the electromagnetic interference (EMI). To decrease the RF power current at PCB level can lead to decrease designing costs. As a preparation of applying LECCS models to a cryptographic IC for estimating the RF power current occurred during an encryption process, the model parameters were identified from measurements in this paper. The LECCS models were composed of a current source that expressed the RF power current occurred in the cryptographic circuit and a passive network. The current source identified grown in amplitude 200 ns after the beginning of the encryption process. This agreed to the beginning of the target round. In frequency domain, current spectra were seen at 24 MHz and its harmonics. The authors obtained waveforms of the RF power current from analog circuit simulations with the LECCS model identified, and validated the cryptographic device in security against the side-channel attacks by means of the correlation power analysis (CPA) method. Results of CPA with the simulated waveforms were consistent to CPA results with measured waveforms. These results means that model parameters were identified correctly, and suggests that the LECCS model is effective for validation of cryptographic devices with respect to side-channel attacks.

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Insertion of Parallel RL Circuits into Power Distribution Network for Simultaneous Switching Current Reduction and Power Integrity 査読

Kengo Iokibe, Yusuke Yano, Yoshitaka Toyota

2012 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)   417 - 420   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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Experimental model validation of mode-conversion sources introduced to modal equivalent circuit 査読

Kota Sejima, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Tetsushi Watanabe

IEEE International Symposium on Electromagnetic Compatibility   492 - 497   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Δh). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Δh becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity. © 2012 IEEE.

DOI： 10.1109/ISEMC.2012.6351682

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Evaluation of Relationship between STP-cable Grounding and Mode Conversion Taking into Account Imbalance Factor 査読

Tatsuya Nobunaga, Yoshitaka Toyota, Kengo Iokibe, Liuji Koga, Tetsushi Watanabe

2012 6TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS (CEEM' 2012)   119 - 119   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In grounding an STP cable, mode conversion occurs depending on how to ground it. For investigating the mode conversion in a four-conductor transmission-line system that consists of three conductors and the system ground such as the STP cable above the system ground, as shown in Fig. I. we have developed modal equivalent circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in a three-conductor transmission-line system. The modal equivalent circuit consists of three modal equivalent circuits of normal mode (Fig. 2), primary common mode (Fig. 3), and secondary common mode(Fig. 4). In this paper, mode conversion between normal mode and primary common mode was evaluated using mixed-mode S parameters and the measured data validated the modal equivalent circuit. As a result, it was found that mode conversion depends on the imbalance factor and it was examined how to ground for suppressing mode conversion.

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Verification of Common-Made-Current Prediction Method Based on Imbalance Difference Model for Single-Channel Differential Signaling System 査読

Tohlu Matsushima, Osami Wada, Tetsushi Watanabe, Yoshitaka Toyota, Liuji R. Koga

2012 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)   409 - 412   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In a differential transmission line, a large common-mode current is excited due to its asymmetry. In this paper, the authors demonstrate experimentally the common-mode current and verify the imbalance difference model that was proposed for prediction of the common-mode current reduction. Experimental results show that the reduction of common-mode current of about 20 dB is achieved by changing the position of the transmission line. In addition, the differences that are calculated using the imbalance difference model are in agreement with the measured ones within 2 dB.

DOI： 10.1109/APEMC.2012.6237956

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Optimal Resistance Determination Method for RL Damper Circuits in Power Distribution Network of ICs 査読

Ryosuke Yamagata, Kengo Iokibe, Yoshitaka Toyota

2012 6TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS (CEEM' 2012)   222 - 225   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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Equivalent current source of side-channel signal for countermeasure design with analog circuit simulator 査読

Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility   806 - 811   2012年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication. © 2012 IEEE.

DOI： 10.1109/ISEMC.2012.6351661

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Power/Ground Layers with EBG Structure and Ferrite Film for Noise Suppression and Power Integrity Improvement 査読

Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS)   2011年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs). We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for noise-suppression and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit. Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results.

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On-Board Decoupling of Cryptographic FPGA to Improve Tolerance to Side-Channel Attacks 査読

Kengo Iokibe, Tetsuo Amano, Yoshitaka Toyota

2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   925 - 930   2011年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules.

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On-board decoupling of cryptographic FPGA to improve tolerance to side-channel attacks 査読

Kengo Iokibe, Tetsuo Amano, Yoshitaka Toyota

IEEE International Symposium on Electromagnetic Compatibility   925 - 930   2011年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules. © 2011 IEEE.

DOI： 10.1109/ISEMC.2011.6038441

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Development of equivalent circuit model with transmission line model for designing filters formed on printed circuit boards 査読

Keisuke Matsumoto, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga

IEEE International Symposium on Electromagnetic Compatibility   289 - 294   2010年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator. ©2010 IEEE.

DOI： 10.1109/ISEMC.2010.5711287

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単一のスリットセグメントへの領域分割によるプリント回路基板の電源系共振の高速解析(放送/一般)

濱上 雄大, 豊田 啓孝, 五百旗頭 健吾, 古賀 隆治

映像情報メディア学会技術報告   33   25 - 30   2009年

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記述言語：日本語   出版者・発行元：一般社団法人 映像情報メディア学会  

多層プリント回路基板の電源系共振は,グリーン関数のモード展開を適用したポート間インピーダンス解析に高速化手法を適用することで,短時間でその特性を計算することができる.この手法では,電源層にスリットを含む場合も,スリット間の電磁結合を表現するモデルを用いて共振特性が求められる.しかし,このスリットモデルの表現ではスリットが幅を持たないため,複数のスリットがある場合など,スリットの幅が電源層の大きさに影響を与える場合には計算結果が正しくなくなる可能性がある.そこで本論文では,スリット間の電磁結合を表現するため,結合マイクロストリップ線路から求めた等価回路モデルを用いて単一のスリットのみを含むスリットセグメントを構成し,これを電源系共振解析に適用することを検討した.結果として,従来モデルと同等かそれ以上の精度で電源系共振解析が可能であることが分かった.

DOI： 10.11485/itetr.33.15.0_25

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Estimation of Radiated Emissions from Multilayered Printed Circuit Board by Common-Mode Antenna Model 査読

Yuli Wakaduki, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga

CEEM: 2009 5TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS   242 - +   2009年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

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De-embedding of Board Parasitics with T-parameters for S-parameter Measurements of Integrated Circuits on PCB-Examinations in One-port Measurements 査読

Kazuki Maeda, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga

CEEM: 2009 5TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS   246 - 249   2009年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

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Stopband prediction with dispersion diagram for electromagnetic bandgap structures in printed circuit boards 査読

Yoshitaka Toyota, Arif Ege Engin, Tae Hong Kim, Madhavan Swaminathan, Kazuhide Uriu

2006 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3, PROCEEDINGS   807 - 811   2006年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Electromagnetic bandgap (EBG) structures that prevent propagation of electromagnetic waves within a given frequency range are quite effective in suppressing simultaneous switching noise on parallel power planes. However, it is quite time consuming to compute the stopband frequencies of interest using full-wave electromagnetic simulation of the entire structure. In contrast, using dispersion-diagram analysis based on a unit-cell network of EBG structures is more efficient and less time consuming. This paper presents an approach for two-dimensional EBG structures by extending a well-known dispersion-diagram analysis of one-dimensional infinite periodic structures. The stopbands predicted with the proposed analysis were compared with good agreement to measured and simulated results. In addition, the concept was applied to test the stopband range of EBG structures formed on an actual printed circuit board with a test coupon of an EBG unit cell placed on the same board.

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Translation of the electromagnetic mode-splitting along a microstrip line with a slit in the ground plane 査読

Ryuji Koga, Tohlu Matsushima, Tetsushi Watanabe, Youhei Sakai, Osami Wada, Kengo Iokibe, Yoshitaka Toyota

CEEM' 2006: ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS, VOLS 1 AND 2, PROCEEDINGS   15 - +   2006年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Is proposed an approach to know magnitudes of parasitic electromagnetic modes excited by the micro-strip line passing over a slit in the return plane. A part of the power having been carried along, the microstrip-line is transferred to the coplanar-line modes along the slot, and the cylindrical. mode in between the pair of re. turn and ground planes. Magnitudes of those modes are expressed by the ratio of powers of the excited electromagnetic mode to the original microstrip line mode, discarding information of phase. Calculation was done with FDTD in the limited domain., around the cross-point in a moderate time of calculation. This approach contributes to the efficient designing of PCB of commercial electronic devices.

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Excitation of electromagnetic modes by a signal transmission line overpassing a slit of return plane

Tohlu Matsushima, Youhei Sakai, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga, Tetsushi Watanabe, Osami Wada

Progress in Electromagnetics Research Symposium   92 - 95   2006年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Electromagnetics Academy  

Printed circuit boards (PCBs) sometimes have a separated power or ground plane. Differential mode having been propagated along the microstrip line is divided into multiple modes when the differential mode arrives at the intersection of the signal line and the slit. They are differential mode that reflects backward and runs through, slot line mode and parallel plane mode. In order to evaluate excitation of undesirable electromagnetic modes, "transmission factor" is defined as a power ratio of excited mode to incident mode and is expressed in a matrix form like S matrix. The transmission factor is obtained by the electromagnetic calculation near the slit, since it is determined only by the structure of the intersection between the signal line and the slit.

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Finite difference modeling of multiple planes in packages

A. Ege Engin, Madhavan Swaminathan, Yoshitaka Toyota

17th International Zurich Symposium on Electromagnetic Compatibility, 2006   2006   549 - 552   2006年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

Power/ground planes in electronic packaging can be a major factor for noise coupling. There can be noise coupling not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. Due to the large size of the power/ground planes, it is difficult to analyze them using full-wave simulators. It is known that the finite difference solution of the Helmholtz equation provides a faster approach with a comparable accuracy. This paper presents new circuit models for a single plane pair based on the finite difference method: T- and X-Models. It also presents a modeling approach for multiple plane pairs that are coupled through apertures.

DOI： 10.1109/emczur.2006.214993

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Analysis and design of electromagnetic bandgap (EBG) structures for power plane isolation using 2D dispersion diagrams and scalability

A. Ege Engin, Yoshitaka Toyota, Tae Hong Kim, Madhavan Swaminathan

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006   79 - 82   2006年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Simultaneous switching noise (SSN) is one of the major bottlenecks for successful design of high-performance systems. Especially mixed-signal designs are very sensitive to SSN due to the low voltage levels applied in analog circuits. One way of isolation is by placing the digital and analog domains far from each other. Even then, the power planes can transfer noise voltages both vertically and horizontally through out the board and total board area is a major concern in microminiaturized convergent systems. Electromagnetic bandgap structures (EBG) have been successfully applied for such isolation. Although any periodical shape can be used for isolation, only a few shapes have been reported, with various analysis methods. We present a new EBG with narrow slits, which shows a higher attenuation constant compared with existing structures. We also present a new analysis methodology for 2D EBG structures. Finally, a method to scale such EBG structures for different stopband requirements is introduced. ©2006 IEEE.

DOI： 10.1109/SPI.2006.289196

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Modeling of gapped power bus structures for isolation using cavity modes and segmentation 査読

ZL Wang, S Wada, Y Toyota, R Koga

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY   47 ( 2 )   210 - 218   2005年5月

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Resonance characteristics of gapped power bus structures with a slit or a gap were studied, using a fast algorithm based on a full cavity-mode resonator model and the segmentation method. Inductance and capacitance models were used to account for a field coupling along the slit and across the gap, respectively. The effectiveness of the segmentation method and the inductance model for the slit has been demonstrated by good agreement between the calculated and measured results, while the capacitance model for the gap is shown to be useful when the coupling between the segments is relatively weak.

DOI： 10.1109/TEMC.2005.847414

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Power current modeling of IC/LSI with load dependency for EMI simulation 査読

H Osaka, T Kinoshita, D Tanaka, O Wada, Y Toyota, R Koga

2003 IEEE SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SYMPOSIUM RECORD, VOLS 1 AND 2   16 - 21   2003年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In this paper, we describe how we modeled EMI noise from the power-pin current of an LSI that has two ports: a power-ground port and a driver output port. We named this modeling the "Linear Equivalent Circuit and Current Source for I/O (LECCS-I/O)" model and with it measured power current and power-ground impedance for various combinations of loading capacitances and decoupling inductances using a small scale IC (74LVC04). Results showed that up to 500 MHz, the LECCS-I/O model could predict peak and valley frequencies of the power current where the error was within 2.5 MHz, and where the peak current error was less than 5 dB. The application range of the LECCS-I/O model is valid where the non-overlap duration of the dumping oscillation wave between cycles is longer than twice the time constant of the waveform.

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High-speed common-mode prediction method for PCBs having a signal line close to the ground edge 査読

T Watanabe, H Fujihara, O Wada, A Namba, Y Toyota, R Koga

2003 IEEE SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SYMPOSIUM RECORD, VOLS 1 AND 2   28 - 33   2003年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Evaluation of common-mode excitation is important to efficiently reduce the EMI radiated from printed circuit boards (PCBs). We have focused on the excitation mechanisms of the common-mode current flowing on a PCB. In a previous paper, we explained a mechanism of common-mode excitation in terms of the current division factor, which expresses the degree of imbalance of a transmission line. The calculation is two-dimensional so the evaluation time is much shorter than that of FDTD or other 3D fullwave simulations. The calculated reduction of common-mode radiation from simple PCBs agreed well with the measured value. In this paper, to demonstrate the effectiveness of this approach, we apply it to various PCBs, such as one that has a signal trace close to a board edge or one with guard bands, and evaluate the effectiveness of the common-mode reduction. Our calculated and experimental results are in good agreement.

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Analysis of resonance characteristics of a power bus with rectangle and triangle elements in multilayer PCBs 査読

ZL Wang, O Wada, Y Toyota, R Koga

ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS, CEEM'2003, PROCEEDINGS   73 - 76   2003年

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：PUBLISHING HOUSE BEIJING UNIV POSTS & TELECOMMUNICATIONS  

One of the major source of radiated EMI is attributed to power bus resonance in a printed circuit board(PCB). A fast algorithm, combined with the segmentation method, is applied for calculating resonance characteristics of a power bus whose pattern consisting of several segments of rectangles and/or right-angled triangles. Good agreements between the calculated and measured results demonstrate the usefulness and accuracy of the fast algorithm and the segmentation method.

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Stable inversion method for a polarized-lidar: Analysis and simulation 査読

He Wei, Ryuji Koga, Kengo Iokibe, Osami Wada, Yoshitaka Toyota

Journal of the Optical Society of America A: Optics and Image Science, and Vision   18 ( 2 )   392 - 398   2001年

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

A new inversion inhomogeneous atmosphere (IA) method that is more stable than Fernald’s method for two-component (molecule and aerosol) scattering analysis of polarized Mie lidar signals is proposed and examined. The backscattering coefficient and the extinction-to-backscattering ratio (EBR) can be calculated for specified regions at which the depolarization ratio is less than that of molecule without further assumptions. The inversion procedure can be extended to both inward stepwise and outward stepwise integration algorithms. Simulation results indicate that a higher precision was achieved with the IA method than with Fernald’s method in terms of error and random noise in estimating boundary value and EBR. Experimental results were also better with the IA method than with Fernald’s method. © 2001 Optical Society of America.

DOI： 10.1364/JOSAA.18.000392

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微細周期構造にイオン注入したときの素子帯電のシミュレーション

酒井 滋樹, 辻 博司, 後藤 康仁, 豊田 啓孝, 石川 順三, 丹上 正安, 松田 耕自

真空   38 ( 3 )   228 - 230   1995年3月

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記述言語：日本語   出版者・発行元：The Vacuum Society of Japan  

DOI： 10.3131/jvsj.38.228

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その他リンク： https://jlc.jst.go.jp/DN/JALC/00032679687?from=CiNii

高周波プラズマスパッタ型負重イオン源における気体材料の負イオン生成

辻 博司, 岡山 芳央, 豊田 啓孝, 後藤 康仁, 石川 順三

真空   38 ( 3 )   218 - 220   1995年3月

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記述言語：日本語   出版者・発行元：The Vacuum Society of Japan  

DOI： 10.3131/jvsj.38.218

CiNii Article

CiNii Books

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その他リンク： https://jlc.jst.go.jp/DN/JALC/00032679656?from=CiNii

Special Number/Negative-Ion Beam Technology and Its Application to Materials Science. Surface Potential Measurement of Negative-Ion-Implanted Insulators by Analysing Secondary Electron Energy Distribution. 査読

豊田啓孝, 辻博司, 南雲正二, 酒井滋樹, 後藤康仁, 石川順三

Ionics   20 ( 1 )   71 - 76   1994年1月

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記述言語：英語  

J-GLOBAL

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Special Number/Negative-Ion Beam Technology and Its Application to Materials Science. Surface Potential Measurement of Insulated Electrode by Negative-Ion Implantation. 査読

辻博司, 酒井滋樹, 豊田啓孝, 岡山芳央, 後藤康仁, 石川順三

Ionics   20 ( 1 )   57 - 64   1994年1月

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記述言語：英語  

J-GLOBAL

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