Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Authorship：Corresponding author   Language：English   Publishing type：Research paper (scientific journal)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Lead author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

DOI： 10.14923/transcomj.2017PEP0001

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.14923/transcomj.2017PEP0001

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

DOI： 10.1587/transinf.2015ICP0018

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A connector model expressed as an inductance is proposed for use in a previously reported common-mode antenna model. The common-mode antenna model is an equivalent model for estimating only common-mode radiation from a printed circuit board (PCB) more quickly and with less computational resources than a calculation method that fully divides the entire structure of the PCB into elemental cells, such as narrow signal traces and thin dielectric layers. Although the common-mode antenna model can estimate the amount of radiation on the basis of the pin configuration of the connector between two PCBs, the calculation results do not show the peak frequency shift in the radiation spectrum when there is a change in the pin configuration. A previous study suggested that the frequency shift depends on the total inductance of the connector, which led to the development of the connector model reported here, which takes into account the effective inductance of the connector. The common-mode antenna model with the developed connector model accurately simulates the peak frequency shift caused by a change in the connector pin configuration. The results agree well with measured spectra (error of 3 dB).

DOI： 10.1587/transcom.2015EBP3269

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

DOI： 10.1541/ieejfms.136.365

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

DOI： 10.1587/transcom.E98.B.1188

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IOP PUBLISHING LTD  

The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.011502

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (scientific journal)  

In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

DOI： 10.1109/TEMC.2013.2250505

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Authorship：Lead author   Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emceurope59828.2024.10722159

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10584970

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10584961

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10585053

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10585228

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emceurope57790.2023.10274220

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241637

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241643

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Language：Japanese   Publishing type：Research paper (scientific journal)  

This paper investigates unintentional radiation from the open-stub structure of a lossy resonator filter suppressing power-bus resonance of printed circuit boards. Using radiation-factor decomposition models obtained by applying Thevenin's theorem, it is found that the increase in radiation from the open-stub structure is negligible.

DOI： 10.14923/transcomj.2022bll0005

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (scientific journal)  

J-GLOBAL

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper examines the possibility of an electromagnetic interference (EMI) caused by unintentional radiated emissions from an unshielded twisted pair (UTP) cable in the sub-6GHz band of 5G. First, it is experimentally and numerically confirmed that a UTP cable with a twist pitch of 20mm and a sheath with relative permittivity of 2.9 radiates above 5.7GHz. It is also clarified that the radiated emissions are attributable to the twist structure. In addition, the usefulness of two equations, derived in developing radiating pair cables, to easily calculate the radiation band and the radiation angle to solve the EMI problem is validated.

DOI： https://doi.org/10.1587/comex.2022XBL0101

Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/comex.2022xbl0101

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Language：English   Publishing type：Research paper (international conference proceedings)  

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

We investigated the prediction of side-channel leak-age on the power delivery network (PDN) outside a cryptographic IC. To predict the leakage, it is necessary to estimate the switching current caused by the switching activity. So far, high temporal resolution estimation based on gate-level logic simulation has been proposed, but due to the decoupling property of the PDN, the switching current leaking out of the IC chip attenuates signif-icantly. Therefore, this paper calculates the mean of the switching currents over the clock period based on register transfer level (RTL) logic simulation, and then approximates it into a triangle waveform. This approach enables us to simulate the switching current faster than with gate-level simulation. In addition, the simulation time is further shortened by calculating the switching current only to the targeted round of a cryptographic algorithm (AES). Switching currents of the previous rounds were given as statistical models with the same sample mean and variance as the targeted round. As a result of simulating the switching current of an FPGA with the proposed method, we were able to obtain the low-order harmonic components of the current in almost the same magnitude as the gate-level simulation. We also simulated correlation power analysis (CPA) results for the printed circuit board on which the FPGA with the AES circuit was mounted, and found that the proposed method could predict the dynamic power supply voltage observed on the board and CPA results with sufficient accuracy.

DOI： 10.1109/EMCEurope51680.2022.9900948

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Language：English   Publishing type：Research paper (international conference proceedings)  

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Language：English   Publishing type：Research paper (international conference proceedings)  

We previously proposed a lossy resonator filter to suppress the parallel-plate resonance of printed circuit boards (PCBs). The filter consists of an open stub (a quarter-wavelength resonator) covered with a ferrite thin film (inducing a small loss). This paper evaluates the effect of the small loss by investigating the suppression of parallel-plate resonance and the unintentional radiation from a PCB with or without the ferrite thin film. An open stub can work as a narrow-band filter but may also work as an antenna and radiate unintentionally, which causes a secondary noise problem at frequencies other than the target frequency of 2.4 GHz. The electric field distribution between the parallel plates and the total radiated power were thus investigated to validate the effect of the small loss of the lossy resonator filter. The results showed that the total radiated power from parallel plates resonating at 2.4 GHz was suppressed by about 12 dB by using open stubs with a resonant frequency of 2.4 GHz, regardless of the presence or absence of the ferrite thin film. At 2.54 GHz, however, the open stubs without ferrite increased the radiated power by about 10 dB, whereas those with ferrite did not increase it at all. It was thus found that the lossy resonator filter could suppress not only the parallel-plate resonance but also unintentional radiation around the target frequency without causing any other problems.

DOI： 10.1109/EMCEurope51680.2022.9901324

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

Once the signal-tu-noise ratio (SNR) of the side- channel (SC) leakage trace is known, the intensity of the SC information leakage source inside the integrated circuit (IC) can be identified from measurements carried out outside the IC, SNR observation of SC leakage can also make it possible to set quantitative design targets to achieve the demanded leakage intensity. We discuss an improved method for identifying the SNR of SC leakage traces composed of multiple transient responses of IC switching current. The IC switching current repeatedly occurs as the IC runs the cryptographic operation since the cryptographic algorithm repeats a set of sub-operations. The method was applied to simulated and measured leakage traces to eliminate the effect of transient IC switching current caused before the target sub-operation was processed. As a result, a transient component more extensive than the signal component of side-channel analysis was identified in the decoupling capacitor configuration, where the convergence of the transient response is slow. In addition, the correlation coefficients obtained by the correlation power analysis, a major side-channel analysis method, were plotted as a function of SNR, and the plot of the simulated traces agreed with the theoretical curve. On the other hand, some errors remained in the plot of the measured traces.

DOI： 10.1109/EMCSI39492.2022.9889660

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Language：English   Publishing type：Research paper (international conference proceedings)  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/ic4me253898.2021.9768521

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/apemc49932.2021.9596844

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/apemc49932.2021.9597127

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Language：English   Publishing type：Research paper (international conference proceedings)  

To estimate the amount of noise suppressed by lossy resonator filters (LRFs) in a power bus with a decoupling capacitor, we used an equivalent circuit model considering the effect of the capacitor to know the suppression mechanism using the LRF. The discrepancy between the model and a full-wave simulation was approximately 2 dB.

DOI： 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559213

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes noise-source parameter identification of the noise-source equivalent-circuit model for predicting conducted noise while considering the switching fluctuation of a DC/DC converter. We decomposed measured conducted noise into ripple noise, turn-on spike noise, and turn- off spike noise to prevent the accuracy degradation in the parameter identification. The predicted conducted noise spectra show the error with the measurement was within 3 dB up to 200 MHz, which is more accurate than that in our previous study.

DOI： 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559182

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

<p>The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.</p>

DOI： 10.1587/transcom.2020EBP3056

CiNii Article

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Language：English   Publishing type：Research paper (international conference proceedings)  

In recent years, some lightweight cipher algorithms for IoT devices have been proposed. These algorithms can be applied to a variety of IoT devices without occupying too much memory and power consumption, and compared to traditional ciphers, such as AES, these algorithms have higher efficiency. The Speck algorithm is a lightweight block cipher, proposed by the NSA in June 2013, and it is specifically optimized for IoT microcontrollers. A few previous studies have shown that the Speck algorithm can be attacked through power analysis. Based on Arduino Uno as the implementation platform of the Speck 128/128 algorithm, in this paper, we propose a method to attack the Speck 128/128 algorithm. Our experiment results have shown that when the attack point in the last round of Speck 128/128 XOR operation, the round key can be successfully recovered by the Correlation Power Analysis attack.

DOI： 10.1109/CANDARW51189.2020.00076

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Language：English   Publishing type：Research paper (international conference proceedings)  

Symmetry is important for differential-transmission lines, but the dense parallel traces easily break the symmetry due to coupling with the adjacent conductor, leading to mode conversion. We propose an asymmetric geometry of differential-transmission lines placed on the side of a nonadjacent conductor to suppress mode conversion and maintain signal integrity in the cases of loosely coupled and tightly coupled parallel traces. By designing the asymmetric geometry of dense differential-transmission lines by taking into account coupling with the adjacent conductor, mode conversion was successfully suppressed by decreasing the line width on the side of the non-adjacent conductor. It was also found that the asymmetric geometry can suppress mode conversion and maintain signal integrity in tightly coupled parallel traces. In loosely coupled parallel traces, on the other hand, the tightly coupled asymmetrically tapered bend we previously proposed suppresses mode conversion.

DOI： 10.1109/EMCEUROPE48519.2020.9245880

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Language：English   Publishing type：Research paper (international conference proceedings)  

We investigated impedance discontinuity detection on a wire network by applying sequence time domain reflectometry (STDR) using maximal-length sequence (M-sequence). We focused on impedance discontinuity detection under multiple reflection generated at nodes on a wire network. We first conducted a preliminary investigation of impedance discontinuity detection on a wire network with one node and confirmed that STDR resulting in cross-correlation of the observed signal with transmitted pulse train exhibits higher noise immunity than conventional TDR. We then demonstrated that STDR can distinguish the impedance discontinuity of various (resistive, inductive, and capacitive) impedance variations on a wire from the shape of the correlation response. Finally, we demonstrated that STDR can detect the location of impedance discontinuity due to small inductance and capacitance on a simple wire network with four nodes.

DOI： 10.1109/EMCEUROPE48519.2020.9245855

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Language：English   Publishing type：Research paper (international conference proceedings)  

As the conducted disturbance of a power converter changes with its load value, the relationship between the electromagnetic interference of the power converter and its load needs to be investigated. This work examines a 2-port equivalent circuit model for a DC/DC buck converter with consideration of the load effect. Factors that influence the model accuracy are also discussed. We used a synchronous buck converter operating under a continuous conduction mode condition to determine the load effect and evaluate the model. Results showed that the input port of the fixed-load model and load-variable model had good accuracy up to 70 MHz. We also predicted the load effect on input port noise and found that the input port noise of an 8.2-? load could be predicted from the other two load values (6.6 ? and 11.6 ?).

DOI： 10.1109/EMCEUROPE48519.2020.9245680

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Language：English   Publishing type：Research paper (international conference proceedings)  

Controller Area Network (CAN) is widely employed as an in-vehicle network, and is required for extremely high reliability. CAN uses five mechanisms to detect errors caused by channel noises in CAN frames. However, an adversary can reportedly falsify a CAN frame by tampering with sample points in the frame. In this paper, the effectiveness of a new falsification method that does not require sample point tampering is proposed. In the method, transient electromagnetic pulses are injected into a CAN bus by magnetic coupling that enables falsification at the target CAN node without error detection. The proposed method was examined on a CAN bus which consists of two CAN nodes. As a result, the new falsification method was effective for CAN.

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emcsi38923.2020.9191655

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emceurope.2019.8871971

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emceurope.2019.8871562

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

A method for optimally designing RL and RC snubber circuits is presented to reduce the electromagnetic interference caused by parasitic LC resonance. The Q factor of the resonance is used as the design criteria. Optimum snubber parameters are determined analytically and uniquely by using a simplified equivalent circuit of the resonant loop and deriving an analytical formula for the Q factor as a function of the snubber parameters. The optimally designed snubbers can adequately adjust the Q factor to any design target. They can also minimize the increases in the negative effects of the snubbers, i.e., overshoot and power loss. The method was applied to RL and RC snubbers to be added to a synchronous buck converter. The effects of the snubbers were reproduced by simulation program with integrated circuit emphasis ( SPICE) simulation to validate the method from the perspective of resonance damping, overshoot, and power loss. The results showed that the damping effects obtained with the optimized snubbers met the Q factor design targets. They also demonstrate that the parameters are optimum in terms of suppressing overshoot and power loss. These results indicate that the method is suitable for optimizing RL and RC snubbers to damp parasitic LC resonance.

DOI： 10.1109/TEMC.2018.2841424

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

When two transmission lines with different imbalance factor are connected, mode conversion occurs at that interface point. The aim of this paper is to suppress mode conversion by improving the shielding of Ethernet cable connector or RJ45 connector of male and female types. By focusing on it, we improved the shielding of the connector by filling gaps at the edge of the connector shield with copper foil tape and the gap between the underside of the female type connector and the printed circuit board, with solder. In this way, the improved shielding around the connector makes the imbalance factor of the connector section close to that of the cable section, and results in the suppression of mode conversion. Based on this idea, it was experimentally confirmed that the shield-improved male type connector shows better reduction of mode conversion than the shield-improved female type connector. Moreover, more reduction in mode conversion was observed when implement the improved shielding of male and female type connectors together.

DOI： 10.1109/IC4ME247184.2019.9036533

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Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：The Japan Institute of Electronics Packaging  

<p>In order to reduce electromagnetic interference at low cost, we propose a method to estimate the intensity of the electromagnetic emission for each IC. In this method, the intensity is estimated based on the ratio of noise source levels obtained by the temporal change in EM emissions when the switching currents generated in potential noise sources are intentionally modulated. In this paper, we applied the proposed method to a printed circuit board with multiple ICs and estimated the intensity of electromagnetic emission originating from individual ICs. Moreover, the accuracy of the estimation was evaluated by comparison with measurements made when the IC was individually driven. The results indicated that the emission intensity can be estimated with high accuracy when all the emissions caused by each IC are in phase.</p>

DOI： 10.5104/jiep.22.218

CiNii Article

CiNii Books

J-GLOBAL

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：Japan Society for Software Science and Technology  

<p>The authors developed a practicum in the cryptographic technology, an indispensable technology to guarantee information security in the upcoming IoT era. The practicum is composed of a lecture in a part of algebra and discrete mathematics that founds modern cryptography, hardware implementation of cryptographic algorithms, and the side-channel attack on cryptographic hardware. It aimed not only that students learned textbook knowledge of cryptographic algorithms but also they developed their knowledge of implementing cryptographic algorithms considering the threat of the side-channel attack through their experience implementing the algorithms on a commercial hardware and attacking them. The practicum was offered to the third- and fourth-year students, and most of them achieved the required goal of the practicum. They also realized improving their practical skills in the cryptographic technology according to their responses to the questionnaire.</p>

DOI： 10.11309/jssst.36.30

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

DOI： 10.1109/EMCEurope.2018.8485011

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/emceurope.2018.8485052

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

The asymmetry, or imbalance, of a differential-transmission-line pair over a meshed ground plane depending on their position leads to the differential skew. This study is focused on the angle between the differential-transmission-line pair and the meshed ground to investigate the angle dependence of differential skew. In a full-wave simulation after preliminary evaluation by a simple model, it is found that the differential skew does not depend on the position of the differential transmission lines to the pattern of the meshed ground and keeps a comparatively small value at the rotation angle around 30°.

DOI： 10.1109/ISEMC.2018.8394024

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

Signal-to-noise ratio (SNR) of side-channel traces leaked from cryptographic ICs can be a candidate of system-designer-friendly design index in security evaluation against the side-channel attack (SCA). A method to calculate SNR of side-channel traces from measured side-channel traces was proposed for the scenario of the byte-by-byte attack on AES cryptographic circuits. The proposed method was a simple extension of an SNR calculation method for the brute force attack scenario proposed in a previous study. Measured SNRs according to the methods were validated by comparison with analytical formulas. Results suggested that the proposed method could provide SNRs of side-channel traces accurately.

DOI： 10.1109/ISEMC.2018.8393880

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

In high speed signal transmissions, glass cloth of the dielectric in printed circuit boards can cause a differential skew. It has been reported that the differential skew is mitigated when the angle between the differential transmission lines and the thread of the glass cloth is around 10°. However, the angle dependence between 10° and 45° and the optimum angle have not yet been investigated. This study focuses on the angle between the trace of the differential transmission lines and the thread of the glass cloth to investigate the angle dependence of the differential skew. We conducted a preliminary evaluation by analytical estimation of the phase delay difference in the differential transmission lines using our simple glass-cloth model. In a full-wave simulation, it was confirmed that the optimum angle between the threads of the glass cloth and the traces of the differential transmission lines is around 40°.

DOI： 10.23919/ICEP.2018.8374316

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Language：Japanese  

DOI： 10.14923/transcomj.2017PEP0001

J-GLOBAL

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Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical Engineers of Japan  

Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors
(1) leakage is reduced by making Hamming distance (HD) at registers constant, (2)leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

DOI： 10.1541/ieejfms.136.365

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Pairing-based cryptography has realized a lot of innovative cryptographic applications such as attribute-based cryptography and semi homomorphic encryption. Pairing is a bilinear map constructed on a torsion group structure that is defined on a special class of elliptic curves, namely pairing-friendly curve. Pairing-friendly curves are roughly classified into supersingular and non supersingular curves. In these years, non supersingular pairing-friendly curves have been focused on from a security reason. Although non supersingular pairing-friendly curves have an ability to bridge various security levels with various parameter settings, most of software and hardware implementations tightly restrict them to achieve calculation efficiencies and avoid implementation difficulties. This paper shows an FPGA implementation that supports various parameter settings of pairings on non supersingular pairing-friendly curves for which Montgomery reduction, cyclic vector multiplication algorithm, projective coordinates, and Tate pairing have been combinatorially applied. Then, some experimental results with resource usages are shown.

DOI： 10.1587/transinf.2015ICP0018

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A connector model expressed as an inductance is proposed for use in a previously reported common-mode antenna model. The common-mode antenna model is an equivalent model for estimating only common-mode radiation from a printed circuit board (PCB) more quickly and with less computational resources than a calculation method that fully divides the entire structure of the PCB into elemental cells, such as narrow signal traces and thin dielectric layers. Although the common-mode antenna model can estimate the amount of radiation on the basis of the pin configuration of the connector between two PCBs, the calculation results do not show the peak frequency shift in the radiation spectrum when there is a change in the pin configuration. A previous study suggested that the frequency shift depends on the total inductance of the connector, which led to the development of the connector model reported here, which takes into account the effective inductance of the connector. The common-mode antenna model with the developed connector model accurately simulates the peak frequency shift caused by a change in the connector pin configuration. The results agree well with measured spectra (error of 3 dB).

DOI： 10.1587/transcom.2015EBP3269

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical Engineers of Japan  

In the modal-equivalent circuit derived from the view of the mode-decomposition technique, mode-conversion sources are placed at the interface where the imbalance factor of the transmission lines changes. In addition, the amount of the mode-conversion sources is proportional to not only the difference in the imbalance factor but also the magnitudes of the normal-mode voltage and the common-mode current at the same position. In this paper, therefore, the suppression of mode conversion from normal mode to common mode is experimentally examined by installing a bypass capacitor to power distribution network. The bypass capacitor helps reduce the normal-mode voltage in the vicinity of a connector on a test board where mode conversion occurs so that the common-mode current flowing a power-line cable and the electric field far from the test board are decreased. In fact, the mode conversion was most suppressed when the bypass capacitor is placed closest to the connector on the test board. Also, it was found that the mode conversion was suppressed by the capacitor installed to the power-line cable in the vicinity of the connector.

DOI： 10.1541/ieejfms.136.25

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

DOI： 10.1587/transcom.E98.B.1188

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Publishing type：Research paper (international conference proceedings)  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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Language：Japanese   Publisher：The Japan Institute of Electronics Packaging  

DOI： 10.11486/ejisso.28.0_63

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

DOI： 10.1109/TEMC.2013.2250505

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Authorship：Lead author,　Corresponding author   Language：Japanese  

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Authorship：Corresponding author   Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Electromagnetics Academy  

Printed circuit boards (PCBs) sometimes have a separated power or ground plane. Differential mode having been propagated along the microstrip line is divided into multiple modes when the differential mode arrives at the intersection of the signal line and the slit. They are differential mode that reflects backward and runs through, slot line mode and parallel plane mode. In order to evaluate excitation of undesirable electromagnetic modes, "transmission factor" is defined as a power ratio of excited mode to incident mode and is expressed in a matrix form like S matrix. The transmission factor is obtained by the electromagnetic calculation near the slit, since it is determined only by the structure of the intersection between the signal line and the slit.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：INST PURE APPLIED PHYSICS  

A new algorithm to estimate lidar ratios of aerosol layers with a monochromatic Mic-scattering lidar profile is proposed. The algorithm employs both the forward,and the backward solutions of the monochromatic single-scattering lidar equation. The lidar ratios are estimated through an iterative procedure to match the two solutions by correcting a lidar ratio assigned at the beginning of the procedure. The algorithm has been applied to simulated lidar profiles and a measured one from the literature. In testing of the simulated profiles, the estimation errors of the lidar ratios were investigated for four boundary conditions-clear to turbid conditions-by scanning boundary values and extinction coefficients of an aerosol layer. This investigation indicated that the algorithm estimates the lidar ratio with sufficient accuracy under clear boundary conditions even with inaccurate boundary values, but requires correct boundary values under turbid boundary conditions. The algorithm was successfully applied to the measured lidar profile of a thin aerosol layer. The obtained lidar ratio was reasonably plausible. This suggests that an enhanced form of this algorithm using the forward and the backward solutions would be able to determine the lidar ratios and boundary values from only a lidar profile measured under arbitrary atmospheric conditions.

DOI： 10.1143/JJAP.43.6513

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Blackwell Publishing Ltd  

We coordinated a ground-based network that has been in use since 1997 to observe Asian dust during springtime. Huge Asian dust events that occurred in the middle of April 1998 were captured by this network. In this paper we present the organization of the network
a description of the instruments, including the lidar, sky radiometer, and optical particle counter
and the results of the observation, and offer discussions regarding the transport mechanism of Asian dust in east Asia using an on-line tracer model. We discussed the time series of the surface concentration and the height distribution of the dust. A cutoff cyclone generated during the dust episode was responsible for trapping and sedimentation during the transportation of the Asian dust, particularly in the southern parts of China and Japan. Horizontal dust images derived from NOAA/AVHRR clearly revealed the structure of the vortex. The lidar network observation confirmed the general pattern of dust height distribution in this event
the height of the major dust layer was about 3 km over Japan but was higher (4 to 5 km) in Seoul and Hefei. A thin dust layer in the upper troposphere was also commonly observed in Hefei and Japan. Evidence of the coexistence of dust and cirrus was shown by the polarization lidar. The lidar network observation of Asian dust and satellite remote sensing provide key information for the study of the transport mechanism of Asian dust. Further extension of the lidar network toward the interior of the continent and the Pacific Rim would reveal the greater global mechanism of the transportation. Copyright 2001 by the American Geophysical Union.

DOI： 10.1029/2000JD900554

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A new inversion inhomogeneous atmosphere (IA) method that is more stable than Fernald’s method for two-component (molecule and aerosol) scattering analysis of polarized Mie lidar signals is proposed and examined. The backscattering coefficient and the extinction-to-backscattering ratio (EBR) can be calculated for specified regions at which the depolarization ratio is less than that of molecule without further assumptions. The inversion procedure can be extended to both inward stepwise and outward stepwise integration algorithms. Simulation results indicate that a higher precision was achieved with the IA method than with Fernald’s method in terms of error and random noise in estimating boundary value and EBR. Experimental results were also better with the IA method than with Fernald’s method. © 2001 Optical Society of America.

DOI： 10.1364/JOSAA.18.000392

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：SPIE-INT SOC OPTICAL ENGINEERING  

We have organized a network campaign for the observation of Asian dust in the spring of 1997 and 1998 in Japan. Through the communication with electric mail, we have successfully observed Kosa events by lidar, sunphotometer, and particle counter, etc. These data must be useful to analyze the transport mechanism of Asian dust and validate the satellite observations.

DOI： 10.1117/12.319584

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical Engineers of Japan  

In the modal-equivalent circuit derived from the view of the mode-decomposition technique, mode-conversion sources are placed at the interface where the imbalance factor of the transmission lines changes. In addition, the amount of the mode-conversion sources is proportional to not only the difference in the imbalance factor but also the magnitudes of the normal-mode voltage and the common-mode current at the same position. In this paper, therefore, the suppression of mode conversion from normal mode to common mode is experimentally examined by installing a bypass capacitor to power distribution network. The bypass capacitor helps reduce the normal-mode voltage in the vicinity of a connector on a test board where mode conversion occurs so that the common-mode current flowing a power-line cable and the electric field far from the test board are decreased. In fact, the mode conversion was most suppressed when the bypass capacitor is placed closest to the connector on the test board. Also, it was found that the mode conversion was suppressed by the capacitor installed to the power-line cable in the vicinity of the connector.

DOI： 10.1541/ieejfms.136.25

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electrical Engineers of Japan  

Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors
(1) leakage is reduced by making Hamming distance (HD) at registers constant, (2)leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

DOI： 10.1541/ieejfms.136.365

Language：Japanese   Publishing type：Research paper (scientific journal)  

DOI： 10.1541/ieejfms.136.25

Authorship：Lead author   Language：Japanese   Publishing type：Article, review, commentary, editorial, etc. (scientific journal)   Publisher：The Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.25.439

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Authorship：Lead author   Language：Japanese   Publishing type：Article, review, commentary, editorial, etc. (scientific journal)   Publisher：The Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.25.327

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Language：Japanese  

CiNii Books

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper, summary (international conference)  

Authorship：Corresponding author   Language：English   Publishing type：Research paper, summary (international conference)  

Authorship：Corresponding author   Language：English   Publishing type：Research paper, summary (international conference)  

Authorship：Corresponding author   Language：English   Publishing type：Research paper, summary (international conference)  

Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper, summary (international conference)  

Authorship：Corresponding author   Language：English   Publishing type：Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

Pseudo-random binary sequence (PRBS) was applied to identify dominant noise sources of electromagnetic interference (EMI) radiated from a printed circuit board (PCB) including line driver ICs. The ICs were controlled in activation of output according to a set of PRBSs that varied amplitude of switching current generated in the ICs and also changes the strength of EMI. Correlation coefficients between the temporal variation of conducted EMI strength and PRBS were examined. Results showed that PRBS has a potential to identify dominant noise sources of EMI.

DOI： 10.1109/ICCE-China.2017.7991087

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Language：English   Publishing type：Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

The miniaturization of unit cells in planar electromagnetic bandgap (EBG) structures has been difficult because the stopband frequency depends on the unit-cell size. To solve this problem, we developed an EBG structure that uses two power planes (dual power plane: DPP) with the addition of a capacitive coupling element. This enables us to easily enlarge the capacitance formed in the unit cell and achieve miniaturization with a stopband frequency of interest. Using full-wave simulation, we tested a 2-mm-square (4-mm2) unit cell of the DPP-EBG structure and measured a stopband frequency around 2.4 GHz.

DOI： 10.1109/APEMC.2017.7975472

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Language：English   Publishing type：Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

Improving the countermeasures against side-channel attacks (SCAs) increases the cost of both designing the countermeasures and evaluating SCA resistance. This may force cryptographic ICs to remain vulnerable. The increased cost is due to an indispensable procedure where a large number of side-channel traces need to be analyzed in order to evaluate the SCA resistance. In this work, a low-cost method to design and evaluate countermeasures using the signal-to-noise ratio (SNR) of side-channel traces as design and evaluation criteria is proposed. The method combines two existing methods: A prediction method of correlation coefficients between side-channel traces and a power model based on the SNR of the side-channel traces, and an estimation method of the number of traces needed to disclose the secret key based on the correlation coefficients. We construct a method to measure the SNR of side-channel traces and validate it for the design and evaluation criteria. In our method, the SNR is first calculated from signal and noise variances extracted from side-channel traces by increasing the number of averaging in side-channel trace measurements, and then the correlation coefficients and the number of traces for key-disclose are estimated on the basis of the calculated SNR. We confirmed that the estimated correlation coefficient and the number of traces for key-disclose were in good agreement with the corresponding measured ones. This result demonstrates that the proposed method can accurately measure the SNR of side-channel traces.

DOI： 10.1109/APEMC.2017.7975433

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Authorship：Corresponding author   Language：English   Publishing type：Research paper, summary (international conference)  

Language：English   Publishing type：Article, review, commentary, editorial, etc. (international conference proceedings)  

J-GLOBAL

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Language：English   Publishing type：Article, review, commentary, editorial, etc. (international conference proceedings)  

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Language：English   Publisher：IEEE  

In this paper, the authors apply two modular exponentiation algorithms such as left-to-right binary method and Montgomery powering ladder algorithm on Raspberry Pi and evaluate their security against Side-channel attack.

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Language：English   Publisher：IEEE  

To overcome the intra EMC problems in wireless communications, electromagnetic bandgap (EBG) structures can be used to effectively reduce power-bus noise. We previously proposed a vialess open-stub EBG structure. However, it still has the intrinsic disadvantage of a narrow stopband because it uses the open-stub's resonance. Thus, this paper aims to optimize the structural parameters of the vialess open-stub EBG structure to sufficiently suppress power-bus noise in a wider stopband. The structural parameters to determine the noise-reduction performance of the vialess open-stub EBG structure are the branch width rob, the stub width w(s), and the unit-cell length alpha. Rectangular power buses were designed as test vehicles through the analytical approach and used to evaluate the stopband expansion and the noise suppression in the stopband in a full wave simulation. The transmission characteristics showed that, after w(b), W-s, and a are optimized, the stopband is expanded from 0.61 GHz (2.23-2.84 GHz) to 1.56 GHz (2.20-3.76 GHz). In addition, an optimized structure was made that reduced the amount of noise by approximately 10 dB.

DOI： 10.1109/ICSJ.2016.7801273

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Language：English   Publisher：IEEE  

The bend in a pair of differential transmission lines on printed circuit boards causes a path difference, which leads to mode conversion due to the phase difference. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion. In this paper, we propose a design methodology of our tightly coupled asymmetrically tapered bend that limits the bend structure within the area of the original classic bend for high-density mounting. We also evaluated the 45-degree-angle bend formed based on our design methodology and found that the methodology helps improve or maintain its transmission characteristics compared to those of the classic bend.

DOI： 10.1109/APEMC.2016.7522769

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Language：English   Publisher：IOP PUBLISHING LTD  

The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.011502

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Language：English   Publisher：IEEE  

Electromagnetic immunity analysis as well as electromagnetic emission analysis is significant for EMC design. In this paper, we apply a modal equivalent-circuit model with mode-conversion sources to electromagnetic immunity analysis in a simple cable interconnection system. The analysis can treat mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis and has been validated in electromagnetic emission analysis. The approach takes an advantage in less calculation sources and helps get design considerations compared with full-wave simulation. In this paper, common-mode excitation by a current probe in a simple cable interconnection system is investigated for model validation. As a result, it is demonstrated that the circuit analysis with the modal-equivalent circuit model agrees well with the measurement results.

DOI： 10.1109/APEMC.2015.7175388

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Language：English   Publisher：IEEE  

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

DOI： 10.1109/ISEMC.2015.7256163

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Language：English   Publisher：IEEE  

This paper describes a proposed planar electromagnetic bandgap (EBG) structure whose unit cell size is miniaturized through the use of interdigital electrodes (IDEs). For planar EBG structures in general, it is difficult to miniaturize the cell size independently of stopband frequency because the stopband frequency depends on the cell size. For the proposed structure, however, the cell size can be miniaturized because the IDEs help enlarge the capacitance between adjacent unit cells and utilize a resonator formed in the unit cells. Because the resonator's resonant frequency determines the stopband frequency of an EBG structure with IDEs, the cell size can be miniaturized independently of the stopband frequency. In the work described in this paper, the proposed EBG structure's efficacy in reducing power bus noise was examined and evaluated through full-wave simulation and measurement in the wireless communication band. It was found that an IDE-EBG structure with a small (25 mm(2)) unit cell is a valid means for achieving power bus noise reduction.

DOI： 10.1109/EDAPS.2015.7383703

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Language：English   Publisher：IEEE  

This paper formulates mode conversions of transmission and reflection from differential mode to common mode in differential transmission lines with bend discontinuity using a very simple model. The formulae tell us that the mode conversion is caused by not only the path difference in the bend but also the difference between the characteristic impedance and port impedance. The formulae were validated by full-wave simulation under the assumption that effect of the bend region is small and results showed that path difference reduction and impedance matching at the input and output ports are significant in suppressing mode conversion. This suggests that the tightly coupled asymmetrically tapered bend proposed by the authors should be effective for suppressing mode conversion.

DOI： 10.1109/EDAPS.2015.7383689

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Language：Japanese   Publisher：Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.18.344

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Language：English   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

DOI： 10.1109/ISEMC.2014.6899067

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Language：English   Publisher：IEEE  

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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Language：English   Publisher：IEEE  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace too close to the return edge on a printed circuit board. In our previous study, a guard trace with a periodic structure was proposed not only to reduce common-mode radiation but also to maintain signal integrity and was found to be effective. In the current work, the shape of the periodic structure and the termination at both edges to improve the features was investigated through full-wave simulation and measurement from the viewpoint of transmission coefficient as well as far-field radiation. Results show that the smaller the widths of the narrow portion, the further the periodic structure helps reduce common-mode radiation and maintain signal integrity. Also shown is that the periodic guard trace with both ends connected to the return plane is an appropriate structure.

DOI： 10.1109/EDAPS.2014.7030811

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Language：English   Publisher：IEEE  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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Language：English   Publisher：IEEE  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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Language：English   Publisher：IEEE  

A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

DOI： 10.1109/EMCEurope.2014.6931007

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Language：English   Publisher：IEEE  

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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Language：English   Publisher：IEEE  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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Language：English   Publisher：IEEE  

For investigating mode conversion in four-conductor transmission systems we have developed a modal-equivalent-circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in three-conductor transmission systems. The modal equivalent circuit consists of three modal equivalent circuits of normal mode, primary-common mode, and secondary-common mode. In this paper, the influence of mode conversion by the pigtail termination of a shielded-twisted-pair (STP) cable was analyzed using the modal equivalent circuit and mixed-mode S parameters with respect to normal mode and primary- common mode. As a result, it was found that mode conversion depends on the imbalance factor and that the modal equivalent circuit helps to explain mode conversion that occurs in terminating STP cables with pigtail.

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The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

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For treating mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis, we have proposed a modal equivalent-circuit model with mode-conversion sources. The approach takes an advantage in less calculation sources and countermeasure consideration compared with full-wave simulation. A mode-decomposition technique was applied with an imbalance factor, that is, the current division factor in our study, of the transmission line. In the modal circuit analysis we proposed, mode conversion is expressed by the controlled sources of which magnitude is proportional to the difference between the current division factors of the adjacent transmission lines. In this paper, we focused on the modal transfer power and derived the mathematical expressions of the mode conversion using the modal characteristic impedance as well as the current division factor. For validating the derived equations, in addition, the comparison with full-wave simulation was carried out and a good agreement was confirmed.

DOI： 10.1109/EDAPS.2013.6724455

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An equivalent circuit model was evaluated in simulating data-dependent power voltage variations of a field-programmable gate array (FPGA). The equivalent circuit model was Linear Equivalent Circuit and Current Source (LECCS) model representing dynamic switching current inside the FPGA with an equivalent current source. The current source was supposed to depend on input data for the FPGA on which a cryptographic circuit was implemented. Model identification was based on the procedure of LECCS model identification from on-board measurements and the current source was identified for all values of input data used in this work. The identified current source was investigated in accordance with the operation process of the cryptographic circuit and found an excellent correlation to the operation process. The identified LECCS model was combined with an equivalent circuit of the power distribution network for the FPGA core circuit to simulate power voltage variations for the 1,000 input texts. The simulated variation waveforms were compared to the corresponding measured ones to evaluate the LECCS model. Results indicated that the simulated and measured power variations matched excellently for all input data with high cross-correlation coefficients from 0.7 to 0.9. LECCS model is, therefore, able to predict the data-dependent power voltage variation by combining a PDN equivalent circuit.

DOI： 10.1109/EMCCompo.2013.6735196

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The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

DOI： 10.1109/ISEMC.2013.6670526

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Noise suppression and power integrity are two requirements for power/ground layers of printed circuit boards. To accomplish the requirements, we proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. To evaluate the proposed EBG structure, we have so far measured the electric characteristics of both driving-point impedance and transmission coefficient. Although these evaluation indices are helpful, the evaluation using an actual device is also indispensable. In this paper, we evaluated the suppression of noise propagation through power bus by the proposed EBG structure in wireless communication module. The proposed structure provided sufficient result of the effective maintenance of communication quality by suppressing the propagation of electromagnetic noise. © 2013 IEEE.

DOI： 10.1109/EDAPS.2013.6724428

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We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

DOI： 10.1109/APEMC.2012.6237943

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We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Delta h). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Delta h becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity.

DOI： 10.1109/ISEMC.2012.6351682

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Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication.

DOI： 10.1109/ISEMC.2012.6351661

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Side-channel attacks are a kind of cryptanalytic attacks by means of the electric current in the range of radio frequency (RF) leaking out from a cryptographic integrated circuit (IC) and/or the electromagnetic radiation generated by the RF power current. The RF power current is caused by simultaneous switching activities of logic gates during an encryption process operated in the cryptographic IC. The RF power current is a major cause of the electromagnetic interference (EMI). To decrease the RF power current at PCB level can lead to decrease designing costs. As a preparation of applying LECCS models to a cryptographic IC for estimating the RF power current occurred during an encryption process, the model parameters were identified from measurements in this paper. The LECCS models were composed of a current source that expressed the RF power current occurred in the cryptographic circuit and a passive network. The current source identified grown in amplitude 200 ns after the beginning of the encryption process. This agreed to the beginning of the target round. In frequency domain, current spectra were seen at 24 MHz and its harmonics. The authors obtained waveforms of the RF power current from analog circuit simulations with the LECCS model identified, and validated the cryptographic device in security against the side-channel attacks by means of the correlation power analysis (CPA) method. Results of CPA with the simulated waveforms were consistent to CPA results with measured waveforms. These results means that model parameters were identified correctly, and suggests that the LECCS model is effective for validation of cryptographic devices with respect to side-channel attacks.

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A lot of improvements and optimizations for the hardware implementation of AES algorithm have been reported. These reports often use, instead of arithmetic operations in the AES original, those in its isomorphic tower field and. This paper focuses on which provides higher-speed arithmetic operations than. In the case of adopting, not only high-speed arithmetic operations in but also high-speed basis conversion matrices from the to should be used. Thus, this paper improves arithmetic operations in with Redundantly Represented Basis (RRB), and provides basis conversion matrices with More Miscellaneously Mixed Bases (MMMB). © Springer-Verlag Berlin Heidelberg 2012.

DOI： 10.1007/978-3-642-34117-5-4

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In grounding an STP cable, mode conversion occurs depending on how to ground it. For investigating the mode conversion in a four-conductor transmission-line system that consists of three conductors and the system ground such as the STP cable above the system ground, as shown in Fig. I. we have developed modal equivalent circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in a three-conductor transmission-line system. The modal equivalent circuit consists of three modal equivalent circuits of normal mode (Fig. 2), primary common mode (Fig. 3), and secondary common mode(Fig. 4). In this paper, mode conversion between normal mode and primary common mode was evaluated using mixed-mode S parameters and the measured data validated the modal equivalent circuit. As a result, it was found that mode conversion depends on the imbalance factor and it was examined how to ground for suppressing mode conversion.

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We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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In IC package modeling of electrical properties, to compare model parameters extracted from results of electromagnetic calculations to those obtained from measurements is an important method for validation of the model. Only direct probing methods for special package, however, had been reported in literature. There is no method for actual packages molded with resin and mounted on printed circuit board. This paper proposes an extraction method of self-inductance of actual IC packages. Four test packages consisted of interposer and bonding wires were employed for validation of the method. Self-inductances of the four packages were extracted from measured impedance parameters obtained by a two ports measurement at board level. The test package contained a THRU line instead of IC-chip. By subtracting inductance of the THRU line from inductance between the two ports of measurement, the package inductance was obtained. As a result, the self-inductance were obtained with absolute errors between -0.8 and -0.2 nH in measurement, between -0.9 〜 -0.6 nH in electromagnetic calculations.

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To suppress the parallel resonance between power/ground planes on printed circuit boards, electromagnetic bandgap (EBG) structure can be applied. The open-stub EBG structure with two stubs in a unit cell is expected to miniaturize the cell size, expand the stopband and form multi-stopbands. In addition to, compare it with mushroom-type EBG structure and open-stub EBG structure with one stub through equivalent-circuit analysis, we established the design methodology to realize both stopbands of 2.4 GHz and 5.2 GHz. As a result, different lengths with two stubs led separate stopbands of 2.4 GHz and 5.2 GHz. Furthermore, we evaluated the difference of spiral stub length between the equivalent circuit model using characteristic parameters and electromagnetic simulation that requires the physical sizes.

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Power/ground layers of Printed Circuit Board (PCB) require two conditions of noise suppression and power integrity (PI). We proposed the application of Electromagnetic Bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for EMI and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate PI characteristics for assuming a real power-supply circuit. Through the evaluation, the proposed structure provided sufficient results. Also almost same characteristics was provided by the test board with only ferrite film.

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At the interface where two transmission lines with different current division factors are connected, there occurs mode conversion. Focusing on a transmission system where a microstrip line on printed circuit board with a transmitter or a receiver is connected to a two-wire line above the system ground, the modal equivalent-circuit model with mode-conversion sources was developed. The model was validated by comparing common mode current and normal-mode voltage between measurement and circuit simulation. As a result, both spectra have a good agreement, which indicates that mode conversion is expressed using the proposed mode-conversion sources. According to the model, two approaches were carried out to reduce normal-mode voltage in common-mode resonance: reduction in the difference of current division factors and reduction in common-mode current. It was found that both approaches can suppress mode conversion as expected by the model.

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Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs). We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for noise-suppression and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit. Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results.

DOI： 10.1109/EDAPS.2011.6213804

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One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules.

DOI： 10.1109/ISEMC.2011.6038441

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In the transmission system where a transmitter and receiver are connected with a cable at a certain distance above the system ground, a mode equivalent-circuit model is proposed to estimate mode current flowing along the system. The simple model is based on mode-decomposition technique and places mode-conversion voltage source and current source at the interface between the transmitter/receiver and the cable where the current division factors are different. In this study, a simple cable interconnection system without dielectric was used to estimate the common-mode current flowing along the system. The circuit simulation using the proposed model showed a good agreement with the circuit simulation regarding as coupled transmission lines. In addition, the mode-current spectrum is found to be close to that obtained from full-wave analysis. Some discrepancy was observed as the distance from the system ground gets larger.

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High-frequency current caused by simultaneous switching of digital gates can be increased with decoupling capacitors, because equivalent series inductance (ESL) of the decoupling capacitors makes resonance with parasitic capacitance on power distribution network trace. In this report, we discussed the location of decoupling inductors as a countermeasure and to reduce the high frequency power current by a circuit simulation. We employed a four-layered printed circuit board as a device under test. The board included an oscillation circuit with a versatile inverter IC and a power distribution network. The board was modeled with a linear equivalent circuit and a current source (LECCS) for the circuit simulations of the RF powe current and power bounce. Results of the circuit simulations showed that reduction of the RF power current was larger with a decoupling inductor placed between the decoupling capacitor and the parasitic capacitance than out side the parasitic capacitance, though a peak current could be occur due to a resonance the parasitic capacitance contributed. The RF power current was reduced at all frequencies even when the decoupling inductor was placed outside the parasitic capacitance. In addition, in order to investigate influence on power integrity (PI) performance of the IC, potential difference between power terminals of chip was calculated. The simulation results showed that the decoupling inductors caused trivial deterioration in P1 performance of the IC.

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A Linear equivalent circuit model of inverter was proposed for applying to designing EMC filters to reduce the conducted emission from electrical appliances with switched-mode power supplys as inverters and converters. We employed a microwave oven as the equipment under test(EUT)and measured the conducted emission voltage at mains port with a line impedance stabilizing network(LISN). Measured disturbances contained both the differential and common modes and we determined the proposed model to have a circuitry structure composed of differential- and common-mode blocks. We, then, described a simple method to determine model parameters from measurements and decided the parameters with the method. With the proposed model, the conducted emission voltage of the EUT was estimated through circuitry simulation and compared to measurement. The comparison showed that the model predicted performance of the EMI filter in reduction of the conducted emission in practical accuracies at frequencies in which model parameters determined had been reasonable.

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In the transmission system where a transmitter and receiver are connected with a cable at a certain distance above the system ground, a common-mode equivalent-circuit model is proposed to estimate common-mode current flowing along the system. The simple model is based on the imbalance difference model that tells that a common-mode electromotive force occurs at an interface between the transmitter/receiver and the cable because their different imbalance factors generates common-mode current. In this study, a simple cable interconnection system between transmitter and receiver pairs was set up to examine an estimation of the common-mode current flowing along the system by using the model. In addition, an evaluation parameter of transfer admittance, given by the ratio of the common-mode current to the normal-mode voltage, was introduced. The measurement and circuit simulation were carried out changing conditions such as grounding, the total length of the system, the distance from the system ground, and the imbalance parameter. The measured and the simulated results agreed well each other and hence the validity of the model was found.

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Slit pattern formed on return plane of printed circuit boards behaves like a passive element. A defected ground structure (DGS) is one of them. The characteristics of DGS easily varies with the slit pattern so that it is expected for various applications. Since a design method has not been developed, however, we need to establish the method to design a slit pattern. Some equivalent circuit models have been used but they consist of lumped elements and require full-wave simulation. In addition, value of the lumped elements have no relation to a physical parameters. So it is not useful for filter designing. In this report, we proposed equivalent circuit model with transmission line model for DGS with filter function. Transmission characteristic was calculated by both full-wave simulator and circuit simulator with the proposed equivalent circuit model and the first stop-band width calculated by circuit simulator was in agreement with full-wave simulator.

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The noise suppression effect after interposing a ferrite film of several microns in thickness between the power and ground planes is discussed in this paper. In particular, we focused on the combination of a planar electromagnetic bandgap structure with a ferrite film deposited by using spin spray ferrite plating at a low temperature. In this paper, the stopband characteristics are discussed through the use of both simulation and measurement results. First, a full-wave electromagnetic simulation revealed that a test board with a dielectric as thin as a few hundreds of microns has the stopband characteristics of the frequency shift towards the lower frequencies (miniaturization effect) and stopband expansion with the removal of the passband, which was not observed in the case of a thick-dielectric test board. The simulation results also demonstrated that these improvements mainly resulted from the complex permeability of the ferrite film. Next, we found that the measurements are very similar to the simulation results.

DOI： 10.1109/APEMC.2010.5475608

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The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator.

DOI： 10.1109/ISEMC.2010.5711287

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An IC macro model for power current analysis, called linear equivalent circuit and current source (LECCS) model, is applied to a bypass circuit design. In the bypass circuit design, since requirements to improve electromagnetic interference (EMI) and power integrity (PI) performances are becoming more and more important, improving methods are considered using the LECCS model. The LECCS model, consisting of a linear equivalent circuit and current sources, the former is closely related to EMI performance and the latter is connected to PI performance. Therefore, each idea for better performance is different. Actually examples of bypass circuits based on the idea are shown, and it is verified that the circuits work out by using a SPICE model.

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An IC macro model for power current analysis, called linear equivalent circuit and current source (LECCS) model, is applied to a bypass circuit design. In the bypass circuit design, since requirements to improve electromagnetic interference (EMI) and power integrity (PI) performances are becoming more and more important, improving methods are considered using the LECCS model. The LECCS model, consisting of a linear equivalent circuit and current sources, the former is closely related to EMI performance and the latter is connected to PI performance. Therefore, each idea for better performance is different. Actually examples of bypass circuits based on the idea are shown, and it is verified that the circuits work out by using a SPICE model.

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In the field of designing printed circuit boards (PCBs), EMC macro-models become increasingly useful to verify EMI performance of PCB with integrated circuits (ICs). This report discussed on estimations of RF currents due to the IC switching by using an IC EMC macro-model, LECCS-I/O, which had been developed to simulate RF power currents of ICs. We focused on not only the RF power current but also the output current of a CMOS I/O gate, since the EMI is caused by RF currents on both power distribution networks and signal lines. We constructed a LECCS-I/O model, with two current sources from measurements and verified the RF currents at power and output pins, comparing to another LECCS-I/O model with a single current source. Results showed that the both models estimate the power current with errors less than 5dB compared to measurements up to 500MHz. Considering the output current, the two-sources model also predicted accurately up to 500MHz, while the single-source model increased errors.

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Applying the electromagnetic bandgap (EBG) structure to power/ground planes of printed circuit boards (PCBs) helps prevent electromagnetic waves from propagating between them at frequencies of interest. We experimentally demonstrated that interposing noise suppression sheet (NSS) into power bus of PCBs is effective for not only miniaturizing the EBG structure but also expanding the stopband towards higher frequencies. This paper clarifies the mechanism of the phenomenon that appears when applying the NSS to the power bus. To distinguish the effects due to permittivity and permeability of the NSS, the S-parameter measurement with the strong magnetic field applied was carried out. The measurement results showed the stopband shift towards lower frequencies results from the effect of the anisotoropic permittivity of the NSS on the electric field around the slit of the EBG pattern. The phenomenon was validated by the full-wave simulation by Microwave Studio. Also, an effective approach of applying the NSS to the EBG pattern was experimentally investigated.

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EMI measurement over 1GHz must be operated in a free-space, open area test site. The validation method of free-space condition is called "Site Voltage Standing-wave Ratio" method, which is standardized by CISPR 16-1-4. The standard defines a new procedure for validation of EMC test sites by the ratio of maximum and minimum of transmitted voltages measured at the only 6 locations within a range of 400mm length. The small number of measurement points can cause larger uncertainty. Although the standard requires the measurement at a frequency interval of 50MHz or less, the measurement is usually performed at the largest frequency interval of 50MHz. In this paper, we propose a new approach to reduce the measurement uncertainty with a narrower frequency interval. The approach was validated by measurement as well as simulation. Also the approach was found to reduce the uncertainty caused by the location error in the measurement setup.

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We have proposed an EMC macro model, LECCS, to achieve fast simulations of RF power currents in IC/LSIs. The model consists of linear equivalent circuits with internal equivalent current sources. In this report, we discussed on the LECCS-core model of a 16-bit microcontroller with multiple power pins. RF power currents were measured with a model-evaluation board that is different from model-construction boards in terms of power traces. The measured currents were compared to simulated ones with the LECCS-core model and agreed within 4dB of error. The LECCS model was confirmed when in a condition that decoupling capacitors were removed. Power currents were still well simulated at each power pins as well as at a junction point where power lines meet in such decoupling conditions. We presented that the model simulates the RF power currents in good accuracy.

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In this paper, we apply a connector model with an inductance to the common-mode antenna model. The common-mode antenna model is able to estimate common-mode radiation from a printed circuit board (PCB) fast and with low calculation cost. The previous report described that the model estimated radiation from PCBs with interconnections, depending on pin configurations of the connector. However, the calculation did not follow the frequency shift depending on pin configuration. The shift seems to result from the effective inductance of connector pins. Therefore, we developed the model considering the inductance. It was found that the modified common-mode antenna model with the connector inductance followed the frequency shift of radiation spectrum. As a result, the radiation spectrum obtained from the modified common-mode antenna model has good agreement with the measured spectrum within an error of 2dB.

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This paper describes an electromagnetic interference (EMI) simulation of radiated emissions caused by simultaneous switching noise in an irregular power/ground plane structure. For quick simulation of the radiated emissions from the power-bus edges, we used a series of analytical approaches: power-bus resonance characterization by a fast algorithm based on a cavity-mode model and a segmentation method and radiation calculation using equivalent magnetic current based on the field equivalent principle. The analytically based radiation calculation is achieved within a few minutes on a single personal computer and agrees with the actual measurements. Furthermore, this paper demonstrates an EMI simulation with and without decoupling capacitors by using a linear macro model of an integrated circuit as a noise source. We found a fair agreement between the simulation and measured results.

DOI： 10.1109/APEMC.2008.4559902

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Language：English   Publisher：IEEE  

We investigated the effects of noise suppression by interposing magnetic materials between the power and ground planes of a printed circuit board and focused on RF transmission through and radiation from the power bus. To reduce power bus resonance and radiation, we used a commercial noise suppression sheet, which is commonly used to suppress RF noise generated from electronic devices. We also examined a thin Ni-Zn ferrite film for practical use in the future. We found that power bus resonance and radiation could be mitigated owing to the imaginary part of complex permeability of magnetic materials. The thin ferrite film with a planar electromagnetic bandgap (EBG) structure helped suppress transmission and radiation in the EBG passband.

DOI： 10.1109/APEMC.2008.4559938

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Language：English   Publisher：IEEE  

We have proposed a common-mode antenna model that is designed specifically for estimating common-mode radiation from printed circuit boards (PCBs) very quickly. The model is composed of an antenna that has the same geometry as the adjacent ground plane of the PCB and an excitation source based on an imbalance difference model. The excitation source is provided by the product of Delta h and V-N, where Delta h is the difference in current division factors related to the cross-sectional structure of the transmission line, and VN is the voltage between the signal line and return plane of the transmission line. Here, we describe an experimental validation of the common-mode excitation carried out by measuring the reduction in radiation due to a guard trace placed close to a signal line with a narrow return plane. As a result, it was found that the total common-mode excitation can be given by a superposition of two excitation sources. The results also suggest that when designing the PCB, the guard trace should be grounded at the interface between different ground-plane widths to suppress noise.

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Language：English   Publisher：IEEE  

In this paper, the common-mode antenna model, which can estimate the amount of common-mode radiation quickly and accurately, was applied to a board-to-board interconnection structure with a connector. The inductor model is introduced as the connector model for improving accuracy of the common-mode antenna model. By using the inductance, which was calculated with the commercial electromagnetic field simulator, the radiated emissions estimated by the model agreed with the measurement results within an error of 3 dB around the peak emission levels.

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Language：English   Publisher：IEEE  

The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.

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Language：English   Publisher：IEEE  

An EMC macro-model of a 16-bit microcontroller with multiple-power-supply pins has been proposed for estimating the conducted EMI from a power-supply network. The macro-model, called the linear equivalent circuit and current sources (LECCS) model, is composed of multiple circuit blocks and multiple current sources corresponding to the composition of the chip circuits in the microcontroller, i.e., a current source for a circuit block. A current source statistically expresses the total RF current occurring in the corresponding circuit block. We confirmed that the proposed model could correctly estimate the RF power-supply currents under different decoupling conditions up to 300 MHz. We also found that a linear circuit of the regulator between the I/O and core circuit blocks could express the RF coupling between the two blocks.

DOI： 10.1109/EDAPS.2008.4736018

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

High frequency currents flowing in power supply networks of an IC/LSI has been estimated by an EMC macro model. The high frequency currents due to the simultaneous switching noise of IC/LSI involving large amount of CMOS transistor is modeled with a linear equivalent circuit and current sources. The linear equivalent circuit decreased its accuracy in impedance due to parasitic capacitances causing anti-resonances in the power supply networks. This paper shows with results of experimental and numerical analysis that the parasitic capacitances on the package and printed circuit board cause the anti-resonance. The power supply network impedance were obtained experimentally by use of three evaluation boards with different parasitic capacitances. The parasitic capacitances of the boards were calculated numerically by high-frequency electromagnetic analysis software Sonnet. Impedance simulations by considering the parasitic capacitance shows that an appropriate connection of parasitic capacitances to the LECCS model can expand an available frequency range of the model beyond 1 GHz.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

A common-mode antenna model proposed by the authors is able to predict common-mode radiation from printed circuit boards (PCBs). The model consists of a common-mode excitation source and segmented antenna elements. This repeat discusses the superposition of common-mode sources, the superposition helps to calculate the radiated emissions due to the common-mode excitation in a PCB containing several MSLs. For the evalution, several PCBs with a MSL bent at a right angle were designed and fabricated. Through the experiments and numerical simulation with FDTD method, it was found that the superposition of excitation sources is available to build the common-mode antenna model.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

The amount of radiated emission from the connector between the motherboard and the daughterboard depends on the number of ground pins. This paper discusses the prediction of the amount of radiated emission from printed circuit boards with a connector using the common-mode antenna model proposed by the authors. the effect of reflection of an unmatched interface such as the connector-board was taken into account by using the measurement result of normal mode voltage in simulation. Common-mode emission is reduced by decreasing imbalance between the conn ector and the board.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publisher：AMER METEOROLOGICAL SOC  

A Coulter Multisizer, which is based on the electrical sensing zone (ESZ) or the Coulter principle, was used to measure the size distribution of Asian dust. Coulter Multisizer analysis provides high-resolution size measurements of water-insoluble aerosol particles (WIPs) and the number concentration at each size bin. Aerosol filter sampling was conducted at four sites in Japan during spring 2003. The measured volume size distributions fit fairly well with a lognormal distribution. The results show that the WIP size distributions of the same Asian dust air mass varied at each sampling site and the volume mode diameter at the sites reduced from west to east. The derived volume mode diameter ranged from 1.4 to 2.2 mu m and was comparatively smaller than those in previous studies on Asian dust. This can be explained by the possible internal mixing of Asian dust with other components and by the breaking of particles and dispersion of aggregations by ultrasonification during extraction. The analysis method was improved by washing the aerosol particles collected on a filter using a magnetic stirrer, instead of an ultrasonic cleaner. As a result, the WIP size distribution can be measured in the range of 1-10 mu m. The measured mode diameters were 2.6-3.1 and 4.3-5.6 mu m in 2 Asian dust phenomena at Kofu, Japan, in 2004. It is demonstrated that the Coulter Multisizer method can furnish detailed information regarding the spatial and temporal variations in the mineral dust size distribution.

DOI： 10.1175/JTECH1965.1

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Language：English   Publisher：IEEE  

In order to estimate. the amount of common-mode radiation from a printed circuit board with low calculation cost, a common-mode antenna model has been developed. This paper demonstrates the application of the model to a board interconnection via a connector that is known to be a possible source of common-mode radiation. The radiated emissions estimated by the model agreed with the measurements for practical use.

DOI： 10.1109/ELMAGC.2007.4413451

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Language：English   Publisher：IEEE  

This paper describes fast calculation of radiated emissions from an arbitrarily shaped printed circuit board (PCB). The radiated emissions from the PCB edge are calculated by taking into account magnetic surface current based on the field equivalent principle. The electric field at the PCB edge is provided by a fast algorithm the authors have proposed for power-bus resonance in the PCB. The calculation of radiated emission was completed within a few minutes and in, good agreement with Finite Difference Time Domain (FDTD) calculation. In addition, an EMI simulation was demonstrated by using a linear macro model of IC/LSI. The calculation results were found to be in good agreement with the measurements.

DOI： 10.1109/ELMAGC.2007.4413479

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Electromagnetic bandgap (EBG) structures in a pair of parallel planes are quite effective for suppressing simultaneous switching noise, but they are too large to be applied to compact electronic devices. To miniaturize the EBG structures, we investigated an approach to interpose a high-permeability magnetic metal sheet between the parallel planes. The experimental results show that high permeability of the sheet shifts the stopband towards lower frequencies. This suggests that such sheets contribute to the miniaturization of the EBG structures. In addition, it is demonstrated that the imaginary part of the permeability can expand the stopband.

DOI： 10.1109/ISEMC.2007.19

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Language：English   Publisher：ETH FOUNDATION ZURICH  

A motherboard-daughterboard structure with a connector is known to have another source of common-mode radiated emissions, and the emissions depend on the connector's signal/ground pin configuration. In order to estimate the amount of radiated emissions from the structure, a common-mode antenna model is described. The model consists of an excitation source and an antenna element, and it calculates radiated emissions from PCBs not only quickly but accurately for practical use. In modeling the board interconnection via a connector, we added two common-mode excitation sources at each end of the connector. The electromagnetic emissions estimated by the model agreed with the measurements within an error of 6 dB around peak emission levels between 300 and 600 MHz.

DOI： 10.1109/EMCZUR.2007.4388207

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This report discusses impedance determination of a linear equivalent circuit (LEC) in an EMC macro model, LECCS I/O. The 2-port LECCS I/O model the authors had proposed based on 2-port measurement by a vector network analyzer (VNA) was found to be affected by an external circuit connected to the input terminals of CMOS gates. To remove the defect, this report investigated a 3-port LECCS I/O model with 3-port VNA. The 3-port model includes the input circuit of CMOS gates and the three ports of the model mean the power-supply terminal, the output terminal, and the input terminal to the ground terminal. The proposed 3-port model with 3-port VNA was used for power-ground impedance simulation by changing the impedances of external input and output circuits. As a result, the impedance simulation was in good agreement with measurements in higher frequency range compared with the previous 2-port model with 2-port VNA.

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Language：English   Publisher：IEEE  

Is proposed an approach to know magnitudes of parasitic electromagnetic modes excited by the micro-strip line passing over a slit in the return plane. A part of the power having been carried along, the microstrip-line is transferred to the coplanar-line modes along the slot, and the cylindrical. mode in between the pair of re. turn and ground planes. Magnitudes of those modes are expressed by the ratio of powers of the excited electromagnetic mode to the original microstrip line mode, discarding information of phase. Calculation was done with FDTD in the limited domain., around the cross-point in a moderate time of calculation. This approach contributes to the efficient designing of PCB of commercial electronic devices.

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Language：English   Publisher：Faculty of Engineering, Okayama University  

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Authorship：Lead author   Language：English   Publishing type：Article, review, commentary, editorial, etc. (bulletin of university, research institution)   Publisher：Faculty of Engineering, Okayama University  

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A Mie lidar system was built at Okayama University in 1998. The system is featured by the ability of discriminating depolarization of received signals with a spatial resolution of 15m. Examinations were conducted on the received range-normalized signal and the depolarization ratio from Asian dust. Intense Asian dust occurred in springs of 1998-2000. Vertical distribution of Asian dust was found to be inhomogeneous contrary to the homogeneity assumption employed in preceding works. Multiple scattering in the layers of Asian dust also observed. Complicated structure of Asian dust wrapped by liquid or water droplets were also conjectured from the sudden changes of depolarization ratio in Asian dust layers.

DOI： 10.1117/12.417092

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Language：English   Publisher：Faculty of Engineering, Okayama University  

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Event date： 2022.10.22

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Event date： 2022.7.19

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Event date： 2022.7.14

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Event date： 2022.4.15

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Event date： 2022.3.15 - 2022.3.18

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Event date： 2022.1.18 - 2022.1.21

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Event date： 2021.12.17

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Event date： 2021.12.13 - 2021.12.14

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Event date： 2021.11.24 - 2021.11.30

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Event date： 2021.10.23

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Event date： 2021.10.23

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Event date： 2021.9.14 - 2021.9.17

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Event date： 2021.9.14 - 2021.9.17

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Event date： 2021.6.15

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Event date： 2021.4.16

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Event date： 2021.3.9 - 2021.3.12

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Event date： 2020.12.11

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Event date： 2020.10.26

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Event date： 2020.1.28 - 2020.1.31

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Event date： 2020.1.17

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Event date： 2020

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Event date： 2019.12.6

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Event date： 2019.7.19

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Event date： 2019.5.10

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Event date： 2019.3.19 - 2019.3.22

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Event date： 2019.3.19 - 2019.3.22

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Event date： 2019.1.22 - 2019.1.25

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Event date： 2018.11.22 - 2018.11.23

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Event date： 2018.3.6 - 2018.3.8

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Event date： 2018.1.23 - 2018.1.26

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Event date： 2018.1.23 - 2018.1.26

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Event date： 2018.1.18 - 2018.1.19

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Event date： 2015.5.15

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Event date： 2015.1.22

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Electromagnetic bandgap (EBG) formed by a periodic structure (EBG structure) has been studied for reducing power-bus noise of printed circuit boards. The EBG structure obtains a large amount of noise suppression and is available for separating simultaneous switching noise generated in digital circuits and small rf signal in analog circuits on mixed-signal boards. Many kinds of EBG structures have been so far proposed and can be roughly classified into two types with and without vias. We have focused on Planar EBG structures without vias because they consist of only two layers and cost-effective due to no vias. In contrast, open-stub EBG structure, which is one of EBG structures with vias, is easy to miniaturize its cell size independently of suppression frequency. We considered that the open-stub EBG structure was specialized for the EBG structures with vias. In this report, however, a planer EBG structure with open stub is proposed by inventing a new structure. The effect of power-bus noise reduction is examined by full-wave simulation and validated in the 2.4 GHz band.

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Event date： 2012.12.14

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In this study, EMC-macro modeling was examined to develop a method to evaluate cryptographic systems before fabrication. A EMC-macro model of a cryptographic FPGA in which an AES algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of FPGA. The model was implemented into a commercial analog circuit simulator and side-channel traces due to the SSN current was estimated under three different PDN configurations under which a decoupling circuit was inserted into the PDN as a countermeasure. Estimated side-channel traces were analyzed statistically by the correlation power analysis (CPA) method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.

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Event date： 2012.8.28

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Event date： 2012.6.15

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A reduction design of conducted disturbance from power converter circuits is becoming more important as electronic devices are requiring much more power efficiency. Conducted disturbance must meet domestic and international regulations. In this paper, a linear equivalent circuit model on the basis of a EMC macro-model of IC/LSI, LECCS model, is investigated to predict the conducted disturbance of power converter circuits. The dual-port LISN (DP-LISN) constructed to provide the model is also reported. In the study, an commercial table-top induction heater is used as the equipment under test. Conducted disturbance voltages were measured with 10 different load pairs of the DP-LISN. Model parameters were then determined by the least square method with the conducted disturbance voltages measured. We simulated conducted disturbance voltages for evaluation by use of the linear equivalent circuit model as an evaluation of the model. As comparing simulated and measured disturbance voltages, the spectrum of the conducted disturbance voltages agreed with each other in their envelopes.

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Event date： 2012.3.6

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Event date： 2012.3.6

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Event date： 2012.3.6

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Event date： 2012.3.6

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Event date： 2012.1.26

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It is of importance for designers to possess accurate inductances of IC packages in power integrity(PI) and electromagnetic compatibility designs. The authors had proposed a simple method to measure inductance of IC package that is mounted on a practical printed circuit board. They investigated the method in terms of accuracy here. In the proposed method, a transmission line is embedded in an IC package interested, and two port S parameters of a network composed of a targeted package structure, the transmission line, and the corresponding symmetric package structure is measured. The package inductance is calculated from the measured S parameters and properties of the transmission line obtained beforehand. The proposed method was applied to four test IC packages, and their inductances were measured. The measurement was demonstrated on a commercial electromagnetic simulator, HFSS. The package inductances were also obtained by analyzing the test package directly for comparison to the results of the proposed method. They agreed with the maximum error of 0.9 nH. To understand a cause of the error, the authors investigated effects of dummy-objects that were used to place measuring ports in the HFSS calculation. The dummy-object caused errors less than 0.06 nH, which means it seldom cause significant errors.

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Event date： 2011.11.25

Language：Japanese  

We focus on the expression by using modal equivalent-circuit model. The goal of this study is to clarify the mechanism of the phenomena caused by mode conversion and then find effective measures. The simple model is based on mode-decomposition technique and places mode-conversion sources at the interface where the current division factors of the transmission lines are different. In this study, a simple cable interconnection system with a node and common-mode excitation by a current probe were investigated to evaluate the validity of this study. As a result, both cases agreed well between measurement and circuit simulation with the modal-equivalent circuit model.

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Event date： 2010

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Event date： 2009.3.4

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Event date： 2009

Language：Japanese  

A fast algorithm based on a full cavity-mode resonator model of rectangular power-bus structures is able to quickly obtain the power-bus resonance characteristics in multilayer printed circuit boards (PCBs). Furthermore, the approach can provide the resonance characteristics in PCBs with a slit using a slit model expressing electromagnetic coupling across the gap of the slit. However, the model does not express the slit width, which can cause the degradation in accuracy of resonance analysis. In this paper, a slit segment was studied to express the gap of the single slit coupling and analyze the power-bus resonances. The slit segment was given from an equivalent circuit based on a coupled microstrip line. As a result, it was found that the slit segment can provide the power-bus resonance characteristics as accurate as or more accurate than the conventional slit model.

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Event date： 2003

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Event date： 2002

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