Updated on 2022/10/01

写真a

 
IOKIBE Kengo
 
Organization
Faculty of Natural Science and Technology Assistant Professor
Position
Assistant Professor
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Degree

  • Doctor of Philosophy ( Okayama University )

Research Interests

  • Electromagnetic compatibility

  • Infromation security

  • Applied laser sensing

  • 環境電磁工学

  • 情報セキュリティ

  • レーザ応用計測

Research Areas

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Communication and network engineering

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Measurement engineering

  • Informatics / Information security  / Cryptographic hardware

Education

  • Okayama University   自然科学研究科   知能開発科学専攻

    - 2005

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    Country: Japan

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  • Okayama University    

    - 2005

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  • Okayama University   工学部   電気電子工学科

    - 1997

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    Country: Japan

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  • Okayama University    

    - 1997

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Research History

  • - 岡山大学自然科学研究科 助教

    2005

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  • - Assistant Professor,Graduate School of Natural Science and Technology,Okayama University

    2005

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Professional Memberships

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Committee Memberships

  • エレクトロニクス実装学会   電磁特性技術委員会 委員  

    2012   

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    Committee type:Academic society

    エレクトロニクス実装学会

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Papers

  • Mode-Conversion Reduction Using Tightly Coupled Asymmetrically Tapered Bend for High-Density Differential Wiring Reviewed

    Chenyu Wang, Kengo Iokibe, and Yoshitaka Toyota

    IEICE Transactions on Communications   E104-B ( 3 )   304 - 311   2021.3

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    Language:English   Publishing type:Research paper (scientific journal)  

  • Evaluation of Side-channel Leakage Simulation by Using EMC Macro-model of Cryptographic Devices Reviewed

    Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, and Yohei Hori

    IEICE Transactions on Communications   E104-B ( 2 )   178 - 186   2021.2

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  • Suppression of Mode Conversion at Ethernet Connector by Using Modal-Equivalent Circuit Model Based on Imbalance Matching Reviewed

    Md. Ashraful Islam, Kengo Iokibe, and Yoshitaka Toyota

    IEEJ Transactions on Fundamentals and Materials   140 ( 12 )   586 - 592   2020.12

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    Language:English   Publishing type:Research paper (scientific journal)  

  • Mitigating Differential Skew by Rotating Meshed Ground for High-Density Layout in Flexible Printed Circuits Reviewed

    Chenyu Wang, Kengo Iokibe, and Yoshitaka Toyota

    IEICE Electronics Express   17 ( 10 )   1 - 6   2020.5

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    Language:English   Publishing type:Research paper (scientific journal)  

  • A Method for Optimally Designing Snubber Circuits for Buck Convertor Circuits to Damp LC Resonance Reviewed

    Y. Yano, N. Kawata, K. Iokibe, Y. Toyota

    IEEE Trans. on Electromagn. Compat.   61 ( 4 )   1217 - 1225   2019.8

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  • ノイズ源振幅変調と相関解析に基づくノイズ源IC毎の電磁妨害波強度推定 Reviewed

    吉野慎平, 五百旗頭健吾, 矢野佑典, 豊田啓孝

    22 ( 3 )   218 - 225   2019.5

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)  

  • 差動配線とメッシュグラウンドのなす角に着目した差動スキュー低減 Reviewed

    王晨宇, 五百旗頭健吾, 豊田啓孝

    J102-B ( 3 )   228 - 236   2019.3

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    Language:Japanese   Publishing type:Research paper (scientific journal)  

  • 市販マイコンモジュールを利用した暗号ハードウェアセキュリティ演習の開発 Reviewed

    五百旗頭健吾, 上竹嘉紀, 手嶋俊彰, 眞田晃宏, 野上保之

    36 ( 1 )   30 - 36   2019.2

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    Authorship:Lead author   Language:Japanese   Publishing type:Research paper (scientific journal)  

  • 差動伝送線路への周期構造導入によるクロストーク抑制 Reviewed

    竹田大晃, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会論文誌 B   J101-B ( 3 )   212 - 219   2018

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    Language:Japanese   Publishing type:Research paper (scientific journal)  

    DOI: 10.14923/transcomj.2017PEP0001

  • Crosstalk Suppression by Introducing Periodic Structure into Differential Transmission Lines Reviewed

    Hiroaki Takeda, Kengo Iokibe, Yoshitaka Toyota

    IEICE Transactions on Communications   J101-B ( 3 )   212 - 219   2018

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.14923/transcomj.2017PEP0001

  • FPGA Implementation of Various Elliptic Curve Pairings over Odd Characteristic Field with Non Supersingular Curves Reviewed

    Yasuyuki Nogami, Hiroto Kagotani, Kengo Iokibe, Hiroyuki Miyatake, Takashi Narita

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E99D ( 4 )   805 - 815   2016.4

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    DOI: 10.1587/transinf.2015ICP0018

  • Connector Model for Use in Common-Mode Antenna Model Used to Estimate Radiation from Printed Circuit Boards with Board-to-Board Connector Reviewed

    Yuri Wakaduki, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Osami Wada

    IEICE TRANSACTIONS ON COMMUNICATIONS   E99B ( 3 )   695 - 702   2016.3

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A connector model expressed as an inductance is proposed for use in a previously reported common-mode antenna model. The common-mode antenna model is an equivalent model for estimating only common-mode radiation from a printed circuit board (PCB) more quickly and with less computational resources than a calculation method that fully divides the entire structure of the PCB into elemental cells, such as narrow signal traces and thin dielectric layers. Although the common-mode antenna model can estimate the amount of radiation on the basis of the pin configuration of the connector between two PCBs, the calculation results do not show the peak frequency shift in the radiation spectrum when there is a change in the pin configuration. A previous study suggested that the frequency shift depends on the total inductance of the connector, which led to the development of the connector model reported here, which takes into account the effective inductance of the connector. The common-mode antenna model with the developed connector model accurately simulates the peak frequency shift caused by a change in the connector pin configuration. The results agree well with measured spectra (error of 3 dB).

    DOI: 10.1587/transcom.2015EBP3269

  • 暗号回路におけるサイドチャネル情報漏洩挙動の内部電流源による分析 Reviewed

    五百旗頭健吾, 田井伸拓, 籠谷裕人, 大西紘之, 豊田啓孝, 渡辺哲史

    電気学会論文誌A   A 136 ( 6 )   365 - 371   2016

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    Authorship:Lead author, Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)  

    DOI: 10.1541/ieejfms.136.365

  • Suppression of Mode Conversion by Using Tightly Coupled Asymmetrically Tapered Bend in Differential Lines Reviewed

    Yoshitaka Toyota, Shohei Kan, Kengo Iokibe

    IEICE TRANSACTIONS ON COMMUNICATIONS   E98B ( 7 )   1188 - 1195   2015.7

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

    DOI: 10.1587/transcom.E98.B.1188

  • Effect of Mg loading on the high-frequency tunability of Ba0.8Sr0.2TiO3 ceramics Reviewed

    Takashi Teranishi, Tsuyoshi Sogabe, Hidetaka Hayashi, Akira Kishimoto, Kengo Iokibe, Yoshitaka Toyota

    JAPANESE JOURNAL OF APPLIED PHYSICS   54 ( 1 )   11502-1-011502-6   2015.1

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IOP PUBLISHING LTD  

    The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

    DOI: 10.7567/JJAP.54.011502

  • ディジタルIC電源供給回路へのRLスナバ適用による伝導性電磁雑音低減及び電源品質改善 Reviewed

    五百旗頭健吾, 山縣亮介, 豊田啓孝

    電子情報通信学会論文誌B   J97-B ( 7 )   497 - 506   2014

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    Authorship:Lead author, Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)  

  • Equivalent circuit modeling of cryptographic integrated circuit for information security design Reviewed

    Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota

    IEEE Transactions on Electromagnetic Compatibility   55 ( 3 )   581 - 588   2013

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    In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

    DOI: 10.1109/TEMC.2013.2250505

  • モード等価回路を用いた非一様媒質中伝搬の回路シミュレーションとその適用範囲 Reviewed

    瀬島孝太, 豊田啓孝, 五百旗頭健吾, 古賀隆治, 渡辺哲史

    電子情報通信学会論文誌. B, 通信   J96 ( 4 )   389 - 397   2013

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  • Simulation and Requirements of Modal-Equivalent-Circuit Model in Propagation through Inhomogeneous Media Reviewed

    K. Sejima, Y. Toyota, K. Iokibe, L. R. Koga, T. Watanabe

    IEICE Transactions on Communications (Japanese Edition)   J96 ( 4 )   389 - 397   2013

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  • PI/SI解析精度向上を目的としたIBIS及びLECCS-core組合せICマクロモデル Reviewed

    岡典正, 五百旗頭健吾, 豊田啓孝, 古賀隆治

    電子情報通信学会論文誌C   J93-C ( 11 )   433 - 444   2010.11

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  • 多電源ピンICのLECCS-coreモデルによる電源電流予測精度の検証 Reviewed

    五百旗頭健吾, 東亮太, 津田剛宏, 市川浩司, 中村克己, 豊田啓孝, 古賀隆治

    電子情報通信学会論文誌C   J93-C ( 11 )   516 - 520   2010.11

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  • トランジスタの静特性に基づくドライバ回路のEMIマクロモデル Reviewed

    岡典正, 五百旗頭健吾, 豊田啓孝, 古賀隆治

    電子情報通信学会論文誌B   J92-B ( 1 )   287 - 295   2009.1

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  • プリント回路基板の電源/グラウンドプレーンに形成する不要電磁波伝搬抑制のためのプレーナEBG構造の小型化 Reviewed

    豊田啓孝, A. E. Engin, M. Swaminathan, 五百旗頭健吾, 古賀隆治

    電子情報通信学会論文誌B   J90-B ( 11 )   1135 - 1142   2007.11

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  • High-Resolution Measurement of Size Distribution of Asian Dust Using a Coulter Multisizer Reviewed

    H. Kobayashi, K. Arao, T. Murayama, K. Iokibe, R. Koga, M. Shiobara

    J. Atmospheric and Oceanic Tech   24   194 - 205   2007

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  • Ground-based network observation of Asian dust events of April 1998 in east Asia Reviewed

    (1) T. Murayama, N. Sugimoto, I. Uno, K. Kinoshita, K. Aoki, N. Hagiwara, Z. Liu, I. Matsui, T. Sakai, T. Shibata, K. Arao, B.-J. Sohn, J.-G. Won, S.-C. Yoon, T. Li, J. Zhou, H. Hu, M. Abo, K. Iokibe, R. Koga, Y. Iwasaka

    J. Geophys. Res.   106 ( D16 )   18345 - 18359   2001

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  • A Bidirectional Iteration Algorithm for Determining Lidar Ratios and its Use to Evaluate Boundary Values in the Lidar Inversion Reviewed

    K. Iokibe, Y. Itoh, Y. Toyota, O. Wada, R. Koga

    Japanese Journal of Applied Physics   43 ( 9A )   6513 - 6519   2001

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  • Stable inversion method for a polarized-lidar:analysis and simulation Reviewed

    H. Wei, R. Koga, K. Iokibe, O. Wada, Y. Toyota

    J.Optical Society of America A   18 ( 2 )   392 - 398   2001

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  • An Approach to Predicting Conducted Noise from DC-DC Converter Accounting for Switching Fluctuation

    Shuqi Zhang, Kengo Iokibe, Yoshitaka Toyota

    2021 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)   2021.9

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/apemc49932.2021.9596844

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  • A Study for Low Calculation Cost Side-Channel Resistance Prediction Based on Transfer Impedance of Leakage Path

    Kengo Iokibe, Masaki Himuro, Yoshitaka Toyota

    2021 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)   2021.9

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/apemc49932.2021.9597127

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  • Practical Design Methodology of Mode-Conversion-Free Tightly Coupled Asymmetrically Tapered Bend for High-Density Differential Wiring Reviewed

    WANG Chenyu, IOKIBE Kengo, TOYOTA Yoshitaka

    IEICE Transactions on Communications   104 ( 3 )   304 - 311   2021.3

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.</p>

    DOI: 10.1587/transcom.2020EBP3056

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  • Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices Reviewed

    YANO Yusuke, IOKIBE Kengo, TESHIMA Toshiaki, TOYOTA Yoshitaka, KATASHITA Toshihiro, HORI Yohei

    IEICE Transactions on Communications   104 ( 2 )   178 - 186   2021.2

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>Side-channel (SC) leakage from a cryptographic device chip is simulated as the dynamic current flowing out of the chip. When evaluating the simulated current, an evaluation by comparison with an actual measurement is essential; however, it is difficult to compare them directly. This is because a measured waveform is typically the output voltage of probe placed at the observation position outside the chip, and the actual dynamic current is modified by several transfer impedances. Therefore, in this paper, the probe voltage is converted into the dynamic current by using an EMC macro-model of a cryptographic device being evaluated. This paper shows that both the amplitude and the SC analysis (correlation power analysis and measurements to disclosure) results of the simulated dynamic current were evaluated appropriately by using the EMC macro-model. An evaluation confirms that the shape of the simulated current matches the measured one; moreover, the SC analysis results agreed with the measured ones well. On the basis of the results, it is confirmed that a register-transfer level (RTL) simulation of the dynamic current gives a reasonable estimation of SC traces.</p>

    DOI: 10.1587/transcom.2020EBP3015

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  • Suppression of Mode Conversion at Ethernet Connector by using Modal-Equivalent Circuit Model based on Imbalance Matching Reviewed

    Islam Md. Ashraful, Iokibe Kengo, Toyota Yoshitaka

    IEEJ Transactions on Fundamentals and Materials   140 ( 12 )   586 - 592   2020.12

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electrical Engineers of Japan  

    <p>When a shielded-twisted-pair (STP) cable is connected with a printed circuit board (PCB) via an Ethernet (RJ45) connector, mode conversion between primary- and secondary-common modes occurs at the connector section due to their structural difference that causes the difference in the imbalance factor of the transmission line. In this paper, we investigate the suppression of the mode conversion at the connector section by using a modal-equivalent circuit model based on imbalance matching. We focus on improving the PCB pattern below the shielded Ethernet connector by placing a copper layer on the PCB surface, and the inadequate shielding at the connector section by soldering and wrapping with copper tape. The application of this improvement based on imbalance matching at the connector section makes the imbalance factor of the connector section closer to that of the cable section and results in the suppression of the mode conversion. Based on the concept of imbalance matching, we confirmed the effect of the shield-improved connector with an improved PCB pattern on the suppression of the mode conversion at the connector section through circuit simulation and measurement, and it was validated that the circuit simulation results obtained from the modal-equivalent circuit model agree well with the measurement results.</p>

    DOI: 10.1541/ieejfms.140.586

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  • A Study on Evaluation Board Requirements for Assessing Vulnerability of Cryptographic Modules to Side-Channel Attacks

    Kengo Iokibe, Tomonobu Kan, Yoshitaka Toyota

    2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)   2020.7

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/emcsi38923.2020.9191655

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  • Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits Reviewed

    Wang Chenyu, Iokibe Kengo, Toyota Yoshitaka

    IEICE Electronics Express   17 ( 10 )   20200101 - 20200101   2020.5

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>Asymmetry of differential transmission lines over a meshed ground plane causes differential skew, which leads to signal integrity issues. We measured to evaluate how the angle between the differential transmission lines and meshed ground (the rotation angle) affected differential skew. We also investigated the effect of the lines' position on characteristic impedance and the feasibility of high-density layout of the differential transmission lines, including the bend structure. We found that the differential skew and characteristic impedance are not significantly affected by the position of the differential transmission lines and meshed ground when the rotation angle is set to 30°, a relatively small value. Measurements showed that our design is effective.</p>

    DOI: 10.1587/elex.17.20200101

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  • Design of Vialess Open-stub EBG Structure by Using Preference Set-based Design Method

    Yoshitaka Toyota, Sho Kanao, Kengo Iokibe

    2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE   2019.9

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/emceurope.2019.8871971

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  • Modifying Noise Source Amplitude Modulation Technique to Estimate Magnitude and Phase of Emissions from Individual Integrated Circuits

    Kengo Iokibe, Shimpei Yoshino, Yusuke Yano, Yoshitaka Toyota

    2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE   2019.9

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/emceurope.2019.8871562

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  • A Method for Optimally Designing Snubber Circuits for Buck Converter Circuits to Damp LC Resonance Reviewed

    Yusuke Yano, Naoki Kawata, Kengo Iokibe, Yoshitaka Toyota

    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY   61 ( 4 )   1217 - 1225   2019.8

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

    A method for optimally designing RL and RC snubber circuits is presented to reduce the electromagnetic interference caused by parasitic LC resonance. The Q factor of the resonance is used as the design criteria. Optimum snubber parameters are determined analytically and uniquely by using a simplified equivalent circuit of the resonant loop and deriving an analytical formula for the Q factor as a function of the snubber parameters. The optimally designed snubbers can adequately adjust the Q factor to any design target. They can also minimize the increases in the negative effects of the snubbers, i.e., overshoot and power loss. The method was applied to RL and RC snubbers to be added to a synchronous buck converter. The effects of the snubbers were reproduced by simulation program with integrated circuit emphasis ( SPICE) simulation to validate the method from the perspective of resonance damping, overshoot, and power loss. The results showed that the damping effects obtained with the optimized snubbers met the Q factor design targets. They also demonstrate that the parameters are optimum in terms of suppressing overshoot and power loss. These results indicate that the method is suitable for optimizing RL and RC snubbers to damp parasitic LC resonance.

    DOI: 10.1109/TEMC.2018.2841424

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  • Intensity Estimation of Electromagnetic Emission from Individual ICs Based on Noise Source Amplitude Modulation and Correlation Analysis Reviewed

    Yoshino Shimpei, Iokibe Kengo, Yano Yusuke, Toyota Yoshitaka

    Journal of The Japan Institute of Electronics Packaging   22 ( 3 )   218 - 225   2019.5

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)   Publisher:The Japan Institute of Electronics Packaging  

    <p>In order to reduce electromagnetic interference at low cost, we propose a method to estimate the intensity of the electromagnetic emission for each IC. In this method, the intensity is estimated based on the ratio of noise source levels obtained by the temporal change in EM emissions when the switching currents generated in potential noise sources are intentionally modulated. In this paper, we applied the proposed method to a printed circuit board with multiple ICs and estimated the intensity of electromagnetic emission originating from individual ICs. Moreover, the accuracy of the estimation was evaluated by comparison with measurements made when the IC was individually driven. The results indicated that the emission intensity can be estimated with high accuracy when all the emissions caused by each IC are in phase.</p>

    DOI: 10.5104/jiep.22.218

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  • Development of Practicum in Cryptographic Hardware Security Using Commercial Microcontroller Module. Reviewed

    IOKIBE Kengo, UETAKE Yoshinori, TESHIMA Toshiaki, SANADA Akihiro, NOGAMI Yasuyuki

    Computer Software   36 ( 1 )   30 - 36   2019.2

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    Language:Japanese   Publishing type:Research paper (scientific journal)   Publisher:Japan Society for Software Science and Technology  

    <p>The authors developed a practicum in the cryptographic technology, an indispensable technology to guarantee information security in the upcoming IoT era. The practicum is composed of a lecture in a part of algebra and discrete mathematics that founds modern cryptography, hardware implementation of cryptographic algorithms, and the side-channel attack on cryptographic hardware. It aimed not only that students learned textbook knowledge of cryptographic algorithms but also they developed their knowledge of implementing cryptographic algorithms considering the threat of the side-channel attack through their experience implementing the algorithms on a commercial hardware and attacking them. The practicum was offered to the third- and fourth-year students, and most of them achieved the required goal of the practicum. They also realized improving their practical skills in the cryptographic technology according to their responses to the questionnaire.</p>

    DOI: 10.11309/jssst.36.30

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  • Identification of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis

    Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

    IEEE International Symposium on Electromagnetic Compatibility   2018-August   439 - 444   2018.10

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    To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

    DOI: 10.1109/EMCEurope.2018.8485011

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  • Crosstalk Suppression by Introducing Periodic Structure into Differential Transmission Lines Reviewed

    Hiroaki Takeda, Kengo Iokibe, Yoshitaka Toyota

    IEICE Transactions on Communications   J101-B ( 3 )   212 - 219   2018.3

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  • Identification of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis

    Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

    2018 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE)   439 - 444   2018

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    To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

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  • Analysis of side-channel information leaking behavior in cryptographic circuit using internal current source Reviewed

    Kengo Iokibe, Nobuhiro Tai, Hiroto Kagotani, Hiroyuki Onishi, Yoshitaka Toyota, Tetsushi Watanabe

    IEEJ Transactions on Fundamentals and Materials   136 ( 6 )   365 - 371   2016.6

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    Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors
    (1) leakage is reduced by making Hamming distance (HD) at registers constant, (2)leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

    DOI: 10.1541/ieejfms.136.365

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  • FPGA Implementation of Various Elliptic Curve Pairings over Odd Characteristic Field with Non Supersingular Curves Reviewed

    Yasuyuki Nogami, Hiroto Kagotani, Kengo Iokibe, Hiroyuki Miyatake, Takashi Narita

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E99D ( 4 )   805 - 815   2016.4

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    Pairing-based cryptography has realized a lot of innovative cryptographic applications such as attribute-based cryptography and semi homomorphic encryption. Pairing is a bilinear map constructed on a torsion group structure that is defined on a special class of elliptic curves, namely pairing-friendly curve. Pairing-friendly curves are roughly classified into supersingular and non supersingular curves. In these years, non supersingular pairing-friendly curves have been focused on from a security reason. Although non supersingular pairing-friendly curves have an ability to bridge various security levels with various parameter settings, most of software and hardware implementations tightly restrict them to achieve calculation efficiencies and avoid implementation difficulties. This paper shows an FPGA implementation that supports various parameter settings of pairings on non supersingular pairing-friendly curves for which Montgomery reduction, cyclic vector multiplication algorithm, projective coordinates, and Tate pairing have been combinatorially applied. Then, some experimental results with resource usages are shown.

    DOI: 10.1587/transinf.2015ICP0018

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  • ディジタルICの電源供給回路におけるオンボードRLスナバの実用的な実装位置 Reviewed

    五百旗頭健吾, 豊田啓孝

    電子情報通信学会論文誌 B   J99-B ( 3 )   174 - 181   2016.3

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  • Connector Model for Use in Common-Mode Antenna Model Used to Estimate Radiation from Printed Circuit Boards with Board-to-Board Connector Reviewed

    Yuri Wakaduki, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Osami Wada

    IEICE TRANSACTIONS ON COMMUNICATIONS   E99B ( 3 )   695 - 702   2016.3

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    A connector model expressed as an inductance is proposed for use in a previously reported common-mode antenna model. The common-mode antenna model is an equivalent model for estimating only common-mode radiation from a printed circuit board (PCB) more quickly and with less computational resources than a calculation method that fully divides the entire structure of the PCB into elemental cells, such as narrow signal traces and thin dielectric layers. Although the common-mode antenna model can estimate the amount of radiation on the basis of the pin configuration of the connector between two PCBs, the calculation results do not show the peak frequency shift in the radiation spectrum when there is a change in the pin configuration. A previous study suggested that the frequency shift depends on the total inductance of the connector, which led to the development of the connector model reported here, which takes into account the effective inductance of the connector. The common-mode antenna model with the developed connector model accurately simulates the peak frequency shift caused by a change in the connector pin configuration. The results agree well with measured spectra (error of 3 dB).

    DOI: 10.1587/transcom.2015EBP3269

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  • Suppression of mode conversion by installing bypass capacitor to power distribution network Reviewed

    Yoshitaka Toyota, Toshiki Mikura, Kengo Iokibe

    IEEJ Transactions on Fundamentals and Materials   136 ( 1 )   25 - 32   2016.1

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    In the modal-equivalent circuit derived from the view of the mode-decomposition technique, mode-conversion sources are placed at the interface where the imbalance factor of the transmission lines changes. In addition, the amount of the mode-conversion sources is proportional to not only the difference in the imbalance factor but also the magnitudes of the normal-mode voltage and the common-mode current at the same position. In this paper, therefore, the suppression of mode conversion from normal mode to common mode is experimentally examined by installing a bypass capacitor to power distribution network. The bypass capacitor helps reduce the normal-mode voltage in the vicinity of a connector on a test board where mode conversion occurs so that the common-mode current flowing a power-line cable and the electric field far from the test board are decreased. In fact, the mode conversion was most suppressed when the bypass capacitor is placed closest to the connector on the test board. Also, it was found that the mode conversion was suppressed by the capacitor installed to the power-line cable in the vicinity of the connector.

    DOI: 10.1541/ieejfms.136.25

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  • Suppression of Mode Conversion by Using Tightly Coupled Asymmetrically Tapered Bend in Differential Lines Reviewed

    Yoshitaka Toyota, Shohei Kan, Kengo Iokibe

    IEICE TRANSACTIONS ON COMMUNICATIONS   E98B ( 7 )   1188 - 1195   2015.7

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    In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

    DOI: 10.1587/transcom.E98.B.1188

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  • Analysis on equivalent current source of AES-128 circuit for HD power model verification

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    IEEE International Symposium on Electromagnetic Compatibility   2014-December   302 - 305   2014.12

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    We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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  • ディジタルIC電源供給回路へのRLスナバ適用による伝導性電磁雑音低減及び電源品質改善 Reviewed

    五百旗頭健吾, 山縣亮介, 豊田啓孝

    電子情報通信学会論文誌B   J97-B ( 7 )   497 - 506   2014

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  • Equivalent circuit modeling of cryptographic integrated circuit for information security design

    Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota

    IEEE Transactions on Electromagnetic Compatibility   55 ( 3 )   581 - 588   2013

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    In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

    DOI: 10.1109/TEMC.2013.2250505

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  • モード等価回路を用いた非一様媒質中伝搬の回路シミュレーションとその適用範囲 Reviewed

    瀬島孝太, 豊田啓孝, 五百旗頭健吾, 古賀隆治, 渡辺哲史

    電子情報通信学会論文誌. B, 通信   J96 ( 4 )   389 - 397   2013

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  • 多電源ピンICのLECCS-coreモデルによる電源電流予測精度の検証 Reviewed

    五百旗頭健吾, 東亮太, 津田剛宏, 市川浩司, 中村克己, 豊田啓孝, 古賀隆治

    電子情報通信学会論文誌C   J93-C ( 11 )   516 - 520   2010

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  • トランジスタの静特性に基づくドライバ回路のEMIマクロモデル Reviewed

    岡典正, 五百旗頭健吾, 豊田啓孝, 古賀隆治

    電子情報通信学会論文誌B   J92-B ( 1 )   287 - 295   2009

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  • プリント回路基板の電源/グラウンドプレーンに形成する不要電磁波伝搬抑制のためのプレーナEBG構造の小型化 Reviewed

    豊田 啓孝, エンゲン アリフ エゲ, スワミナッサン マダハバン, 五百旗頭 健吾, 健, 古賀 隆治

    電子情報通信学会論文誌B   vol. J90-B no. 11 ( 11 )   1135 - 1142   2007

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  • A bidirectional iteration algorithm for determining lidar ratios and its use to evaluate boundary values in the lidar inversion Reviewed

    K Iokibe, Y Itoh, Y Toyota, O Wada, R Koga

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   43 ( 9A )   6513 - 6519   2004.9

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    A new algorithm to estimate lidar ratios of aerosol layers with a monochromatic Mic-scattering lidar profile is proposed. The algorithm employs both the forward,and the backward solutions of the monochromatic single-scattering lidar equation. The lidar ratios are estimated through an iterative procedure to match the two solutions by correcting a lidar ratio assigned at the beginning of the procedure. The algorithm has been applied to simulated lidar profiles and a measured one from the literature. In testing of the simulated profiles, the estimation errors of the lidar ratios were investigated for four boundary conditions-clear to turbid conditions-by scanning boundary values and extinction coefficients of an aerosol layer. This investigation indicated that the algorithm estimates the lidar ratio with sufficient accuracy under clear boundary conditions even with inaccurate boundary values, but requires correct boundary values under turbid boundary conditions. The algorithm was successfully applied to the measured lidar profile of a thin aerosol layer. The obtained lidar ratio was reasonably plausible. This suggests that an enhanced form of this algorithm using the forward and the backward solutions would be able to determine the lidar ratios and boundary values from only a lidar profile measured under arbitrary atmospheric conditions.

    DOI: 10.1143/JJAP.43.6513

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  • Stable inversion method for a polarized-lidar:analysis and simulation Reviewed

    He Wei, Ryuji Koga, Kengo Iokibe, Osami Wada, Yoshitaka Toyota

    J. Opt. Soc. Am. A, Opt. Image Sci. Vis.   2001

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  • Suppression of mode conversion by installing bypass capacitor to power distribution network Reviewed

    Yoshitaka Toyota, Toshiki Mikura, Kengo Iokibe

    IEEJ Transactions on Fundamentals and Materials   136 ( 1 )   25 - 32   2016.1

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    Language:Japanese   Publishing type:Research paper (scientific journal)   Publisher:Institute of Electrical Engineers of Japan  

    In the modal-equivalent circuit derived from the view of the mode-decomposition technique, mode-conversion sources are placed at the interface where the imbalance factor of the transmission lines changes. In addition, the amount of the mode-conversion sources is proportional to not only the difference in the imbalance factor but also the magnitudes of the normal-mode voltage and the common-mode current at the same position. In this paper, therefore, the suppression of mode conversion from normal mode to common mode is experimentally examined by installing a bypass capacitor to power distribution network. The bypass capacitor helps reduce the normal-mode voltage in the vicinity of a connector on a test board where mode conversion occurs so that the common-mode current flowing a power-line cable and the electric field far from the test board are decreased. In fact, the mode conversion was most suppressed when the bypass capacitor is placed closest to the connector on the test board. Also, it was found that the mode conversion was suppressed by the capacitor installed to the power-line cable in the vicinity of the connector.

    DOI: 10.1541/ieejfms.136.25

  • ディジタルICの電源供給回路におけるオンボードRLスナバの実用的な実装位置 Reviewed

    五百旗頭健吾, 豊田啓孝

    電子情報通信学会論文誌 B   J99-B ( 3 )   174 - 181   2016

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  • Analysis of side-channel information leaking behavior in cryptographic circuit using internal current source Reviewed

    Kengo Iokibe, Nobuhiro Tai, Hiroto Kagotani, Hiroyuki Onishi, Yoshitaka Toyota, Tetsushi Watanabe

    IEEJ Transactions on Fundamentals and Materials   136 ( 6 )   365 - 371   2016

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    Authorship:Lead author, Corresponding author   Language:Japanese   Publishing type:Research paper (scientific journal)   Publisher:Institute of Electrical Engineers of Japan  

    Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors
    (1) leakage is reduced by making Hamming distance (HD) at registers constant, (2)leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

    DOI: 10.1541/ieejfms.136.365

  • 電源系配線へのバイパスコンデンサ実装によるモード変換量低減 Reviewed

    豊田啓孝, 三倉駿紀, 五百旗頭健吾

    電気学会論文誌A   A 136 ( 1 )   25 - 32   2016

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    DOI: 10.1541/ieejfms.136.25

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  • Efficient Estimation of Noise Suppression Amount in Power Bus with Decoupling Capacitors Using Lossy Resonator Filters Reviewed

    Sho Kanao, Kengo Iokibe, Yoshitaka Toyota

    2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021   323   2021.7

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    To estimate the amount of noise suppressed by lossy resonator filters (LRFs) in a power bus with a decoupling capacitor, we used an equivalent circuit model considering the effect of the capacitor to know the suppression mechanism using the LRF. The discrepancy between the model and a full-wave simulation was approximately 2 dB.

    DOI: 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559213

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  • Noise-Source Parameter Identification Considering Switching Fluctuation of DC-DC Converter Reviewed

    Shuqi Zhang, Taishi Uematsu, Kengo Iokibe, Yoshitaka Toyota

    2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021   186   2021.7

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    This paper proposes noise-source parameter identification of the noise-source equivalent-circuit model for predicting conducted noise while considering the switching fluctuation of a DC/DC converter. We decomposed measured conducted noise into ripple noise, turn-on spike noise, and turn- off spike noise to prevent the accuracy degradation in the parameter identification. The predicted conducted noise spectra show the error with the measurement was within 3 dB up to 200 MHz, which is more accurate than that in our previous study.

    DOI: 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559182

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  • Parameter Identification of Noise-source Equivalent-circuit Model Focusing on Turn-on/Turn-off Timing of DC/DC Converter and Evaluation of Conducted Disturbance Measurement

    2020 ( 57 )   49 - 54   2020.12

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  • An Approach for Attacking Speck on Microcontroller with Correlation Power Analysis Reviewed

    Jianjie Tang, Kengo Iokibe, Takuya Kusaka, Yasuyuki Nogami

    Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020   368 - 372   2020.11

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    In recent years, some lightweight cipher algorithms for IoT devices have been proposed. These algorithms can be applied to a variety of IoT devices without occupying too much memory and power consumption, and compared to traditional ciphers, such as AES, these algorithms have higher efficiency. The Speck algorithm is a lightweight block cipher, proposed by the NSA in June 2013, and it is specifically optimized for IoT microcontrollers. A few previous studies have shown that the Speck algorithm can be attacked through power analysis. Based on Arduino Uno as the implementation platform of the Speck 128/128 algorithm, in this paper, we propose a method to attack the Speck 128/128 algorithm. Our experiment results have shown that when the attack point in the last round of Speck 128/128 XOR operation, the round key can be successfully recovered by the Correlation Power Analysis attack.

    DOI: 10.1109/CANDARW51189.2020.00076

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  • Suppression of Mode Conversion Due to Asymmetric Geometry of Dense Parallel Traces in Differential-Transmission Lines Reviewed

    Tomoya Takeuchi, Kengo Iokibe, Yoshitaka Toyota

    Proceedings of the 2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020   2020.9

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    Symmetry is important for differential-transmission lines, but the dense parallel traces easily break the symmetry due to coupling with the adjacent conductor, leading to mode conversion. We propose an asymmetric geometry of differential-transmission lines placed on the side of a nonadjacent conductor to suppress mode conversion and maintain signal integrity in the cases of loosely coupled and tightly coupled parallel traces. By designing the asymmetric geometry of dense differential-transmission lines by taking into account coupling with the adjacent conductor, mode conversion was successfully suppressed by decreasing the line width on the side of the non-adjacent conductor. It was also found that the asymmetric geometry can suppress mode conversion and maintain signal integrity in tightly coupled parallel traces. In loosely coupled parallel traces, on the other hand, the tightly coupled asymmetrically tapered bend we previously proposed suppresses mode conversion.

    DOI: 10.1109/EMCEUROPE48519.2020.9245880

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  • Preliminary Investigation of Impedance Discontinuity Detection on Wire Network Using Sequence Time Domain Reflectometry Reviewed

    Daiki Kameyama, Kengo Iokibe, Yoshitaka Toyota

    Proceedings of the 2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020   2020.9

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    We investigated impedance discontinuity detection on a wire network by applying sequence time domain reflectometry (STDR) using maximal-length sequence (M-sequence). We focused on impedance discontinuity detection under multiple reflection generated at nodes on a wire network. We first conducted a preliminary investigation of impedance discontinuity detection on a wire network with one node and confirmed that STDR resulting in cross-correlation of the observed signal with transmitted pulse train exhibits higher noise immunity than conventional TDR. We then demonstrated that STDR can distinguish the impedance discontinuity of various (resistive, inductive, and capacitive) impedance variations on a wire from the shape of the correlation response. Finally, we demonstrated that STDR can detect the location of impedance discontinuity due to small inductance and capacitance on a simple wire network with four nodes.

    DOI: 10.1109/EMCEUROPE48519.2020.9245855

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  • Two-port Noise Source Equivalent Circuit Model for DC/DC Buck Converter with Consideration of Load Effect Reviewed

    Shuqi Zhang, Taishi Uematsu, Kengo Iokibe, Yoshitaka Toyota

    Proceedings of the 2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC EUROPE 2020   2020.9

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    As the conducted disturbance of a power converter changes with its load value, the relationship between the electromagnetic interference of the power converter and its load needs to be investigated. This work examines a 2-port equivalent circuit model for a DC/DC buck converter with consideration of the load effect. Factors that influence the model accuracy are also discussed. We used a synchronous buck converter operating under a continuous conduction mode condition to determine the load effect and evaluate the model. Results showed that the input port of the fixed-load model and load-variable model had good accuracy up to 70 MHz. We also predicted the load effect on input port noise and found that the input port noise of an 8.2-? load could be predicted from the other two load values (6.6 ? and 11.6 ?).

    DOI: 10.1109/EMCEUROPE48519.2020.9245680

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  • A Study on Evaluation Board Requirements for Assessing Vulnerability of Cryptographic Modules to Side-Channel Attacks Reviewed International journal

    Kengo Iokibe, Tomonobu Kan, Yoshitaka Toyota

    2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)   528 - 531   2020.8

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  • Electrical Falsification of CAN Data by Magnetic Coupling

    Hiroto Ogura, Ryunosuke Isshiki, Kengo Iokibe, Yuta Kodera, Takuya Kusaka, Yasuyuki Nogami

    ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications   348 - 353   2020.7

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    Controller Area Network (CAN) is widely employed as an in-vehicle network, and is required for extremely high reliability. CAN uses five mechanisms to detect errors caused by channel noises in CAN frames. However, an adversary can reportedly falsify a CAN frame by tampering with sample points in the frame. In this paper, the effectiveness of a new falsification method that does not require sample point tampering is proposed. In the method, transient electromagnetic pulses are injected into a CAN bus by magnetic coupling that enables falsification at the target CAN node without error detection. The proposed method was examined on a CAN bus which consists of two CAN nodes. As a result, the new falsification method was effective for CAN.

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  • A Study for Predicting Power Side-Channel Attack Countermeasure Effect by PDN Decoupling Based on Transfer Impedance

    五百旗頭健吾, 矢野佑典, 豊田啓孝

    電子情報通信学会技術研究報告   119 ( 387(EMCJ2019 81-91)(Web) )   2020

  • Parameter Identification of Noise-source Equivalent-circuit Model Focusing on Turn-on/Turn-off Timing of DC/DC Converter and Evaluation of Conducted Disturbance Measurement

    上松大志, ZHANG Shuqi, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告(Web)   120 ( 282(EMCJ2020 55-63) )   2020

  • Simple Model of Connector to Estimate Current Division Factor for Common-mode Radiation Simulation

    豊田啓孝, 金尾奨, 佐田野勝水, 五百旗頭健吾

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM)   34th   2020

  • Modifying Noise Source Amplitude Modulation Technique to Estimate Magnitude and Phase of Emissions from Individual Integrated Circuits Reviewed International journal

    Kengo Iokibe, Shimpei Yoshino, Yusuke Yano, and Yoshitaka Toyota

    2019 International Symposium on Electromagnetic Compatibility (EMC Europe 2019)   774 - 777   2019.9

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  • Experimental Identification of Relationship between Leakage Trace SNR and Correlation Coefficient in Differential Power Analysis Reviewed International journal

    Yusuke Yano, Toshiaki Teshima, Kengo Iokibe, and Yoshitaka Toyota

    2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sapporo(EMC Sapporo & APEMC 2019), FriAM1C.4   797 - 800   2019.6

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  • Preliminary Study on Modeling of Noise Current and Electromagnetic Radiation for EMI Evaluation of Movable Device with Brush Motors

    上本篤志, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告   119 ( 134(EMD2019 11-16) )   2019

  • Design of Differential Transmission Lines with Periodic Structure for Crosstalk Suppression by Preference Set-based Design Method (電磁環境 マグネティックス合同研究会 EMC一般(EMC Joint Workshop, 2018, Daejon))

    Takeda Hiroaki, Iokibe Kengo, Toyota Yoshitaka

    電気学会研究会資料. MAG = The papers of technical meeting on magnetics, IEE Japan   2018 ( 120 )   11 - 15   2018.11

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  • Investigation of CAN transceiver and controller response to electromagnetic disturbance by using current injection probe (電磁環境 マグネティックス合同研究会 EMC一般(EMC Joint Workshop, 2018, Daejon))

    一色 竜之介, 五百旗頭 健吾, 日下 卓也, 亀川 哲志, 野上 保之

    電気学会研究会資料. EMC = The papers of technical meeting on electromagnetic compatibility, IEE Japan   2018 ( 48 )   23 - 28   2018.11

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  • Determination of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis Reviewed

    Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

    2018 International Symposium on Electromagnetic Compatibility (EMC Europe 2018)   439 - 444   2018.8

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  • Determination of Dominant ICs for Electromagnetic Emission by Using Noise Source Amplitude Modulation and Correlation Analysis Reviewed

    Shimpei Yoshino, Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota, Yasuyuki Nogami

    2018 International Symposium on Electromagnetic Compatibility (EMC Europe 2018)   439 - 444   2018.8

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  • Extension of signal-to-noise ratio measurement method to byte-by-byte side-channel attack Reviewed International journal

    Kengo Iokibe, Toshiaki Teshima, Yusuke Yano, Yoshitaka Toyota

    2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), WE-PM-SS-09-3   745 - 748   2018.5

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  • Intensity Estimation of Electromagnetic Radiation Originated from Individual Source Devices Based on Noise Source Amplitude Modulation and Correlation Analysis

    Proceedings of JIEP Annual Meeting   32   316 - 319   2018

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    DOI: 10.11486/ejisso.32.0_316

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  • Evaluation of Differential Skew Depending on Rotation Angle in Printed Circuit Board with Meshed Ground Plane

    WANG Chenyu, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告   117 ( 510(EMCJ2017 105-112) )   2018

  • Insertion of LC Resonator onto Cryptographic Module for Accelerated Evaluation of Side Channel Attack

    河田直樹, 矢野佑典, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告   117 ( 384(EMCJ2017 88-104) )   2018

  • Miniaturization of Planar EBG Structure with Dual Power Planes-Introduction of Thin Line into the Unit Cell for Increase in Inductance-

    LIN Xingxiaoyu, 五百旗頭健吾, 豊田啓孝, 金子俊之

    電子情報通信学会技術研究報告   117 ( 384(EMCJ2017 88-104) )   2018

  • Determination of High Priority Countermeasures to Reduce Electromagnetic Interference by Using Noise Source Amplitude Modulation and Evaluation of its Effect

    吉野慎平, 石田千晶, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告   117 ( 384(EMCJ2017 88-104) )   2018

  • Study on Signal-to-Noise Ratio Simulation of Side-Channel Traces Leaked from AES Circuit using EDA tool

    手嶋俊彰, 矢野佑典, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告   118 ( 273(ICD2018 39-47) )   2018

  • Application of PRBS for dominant source identification electromagnetic interference caused by digital integrated circuits

    Chiaki Ishida, Kengo Iokibe, Yoshitaka Toyota

    2017 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2017   245 - 246   2017.7

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    Pseudo-random binary sequence (PRBS) was applied to identify dominant noise sources of electromagnetic interference (EMI) radiated from a printed circuit board (PCB) including line driver ICs. The ICs were controlled in activation of output according to a set of PRBSs that varied amplitude of switching current generated in the ICs and also changes the strength of EMI. Correlation coefficients between the temporal variation of conducted EMI strength and PRBS were examined. Results showed that PRBS has a potential to identify dominant noise sources of EMI.

    DOI: 10.1109/ICCE-China.2017.7991087

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  • Miniaturization of planar EBG structure using dual power planes

    Xingxiaoyu Lin, Yoshitaka Toyota, Kengo Iokibe, Toshiyuki Kaneko

    2017 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2017   241 - 243   2017.7

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    The miniaturization of unit cells in planar electromagnetic bandgap (EBG) structures has been difficult because the stopband frequency depends on the unit-cell size. To solve this problem, we developed an EBG structure that uses two power planes (dual power plane: DPP) with the addition of a capacitive coupling element. This enables us to easily enlarge the capacitance formed in the unit cell and achieve miniaturization with a stopband frequency of interest. Using full-wave simulation, we tested a 2-mm-square (4-mm2) unit cell of the DPP-EBG structure and measured a stopband frequency around 2.4 GHz.

    DOI: 10.1109/APEMC.2017.7975472

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  • Signal-to-noise ratio measurements of side-channel traces for establishing low-cost countermeasure design

    Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota, Toshiaki Teshima

    2017 Asia-Pacific International Symposium on Electromagnetic Compatibility, APEMC 2017   93 - 95   2017.7

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    Improving the countermeasures against side-channel attacks (SCAs) increases the cost of both designing the countermeasures and evaluating SCA resistance. This may force cryptographic ICs to remain vulnerable. The increased cost is due to an indispensable procedure where a large number of side-channel traces need to be analyzed in order to evaluate the SCA resistance. In this work, a low-cost method to design and evaluate countermeasures using the signal-to-noise ratio (SNR) of side-channel traces as design and evaluation criteria is proposed. The method combines two existing methods: A prediction method of correlation coefficients between side-channel traces and a power model based on the SNR of the side-channel traces, and an estimation method of the number of traces needed to disclose the secret key based on the correlation coefficients. We construct a method to measure the SNR of side-channel traces and validate it for the design and evaluation criteria. In our method, the SNR is first calculated from signal and noise variances extracted from side-channel traces by increasing the number of averaging in side-channel trace measurements, and then the correlation coefficients and the number of traces for key-disclose are estimated on the basis of the calculated SNR. We confirmed that the estimated correlation coefficient and the number of traces for key-disclose were in good agreement with the corresponding measured ones. This result demonstrates that the proposed method can accurately measure the SNR of side-channel traces.

    DOI: 10.1109/APEMC.2017.7975433

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  • Signal-to-Noise Ratio Measurements of Side-Channel Traces for Establishing Low-Cost Countermeasure Design Reviewed International journal

    Y. Yano, T. Teshima, K. Iokibe, Y. Toyota

    2017 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC 2017), WE-PM-7-2   93 - 95   2017.5

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  • Parameter Identification of Noise-source Linear Equivalent Circuit of DC-DC Converter and Its Evaluation

    Yuhei Osaki, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota

    Proceedings of 2017 Asia-Pacific International Symposium on Electromagnetic Compatibility   217 - 217   2017

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  • Crosstalk Reduction by Introducing Periodic Structure into Dense Differential Pairs

    Hiroaki Takeda, Kengo Iokibe, Yoshitaka Toyota

    Proceedings of 2017 Asia-Pacific International Symposium on Electromagnetic Compatibility   353 - 353   2017

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  • Security Analysis of Raspberry Pi Against Side-Channel Attack with RSA Cryptography Reviewed

    Sanada, Akihiro, Nogami, Yasuyuki, Iokibe, Kengo, Khandaker, Md. Al-Amin

    2017 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW)   2017

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    In this paper, the authors apply two modular exponentiation algorithms such as left-to-right binary method and Montgomery powering ladder algorithm on Raspberry Pi and evaluate their security against Side-channel attack.

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  • 振幅変調したスイッチング電流とEMI測定の相関係数に基づくノイズ源推定~電源ノイズ測定による原理検証~

    石田千晶, 五百旗頭健吾, 豊田啓孝

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM)   31st   2017

  • Crosstalk Suppression in Differential Transmission Lines with Periodic Structure

    竹田大晃, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告   117 ( 1(EMCJ2017 1-6) )   2017

  • Improvement of Noise Source Amplitude Modulation Method to Identify Source Devices of Electromagnetic Interference

    石田千晶, 吉野慎平, 小川千晶, 五百旗頭健吾, 豊田啓孝, 野上保之

    電子情報通信学会技術研究報告   117 ( 319(EMCJ2017 64-75) )   2017

  • Attempt for Determining Cryptographic Circuit Blocks Leaking Side-Channel Information Based on Internal Current Source : Examination with FPGA Implementation of AES Circuits

    116 ( 255 )   79 - 84   2016.10

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  • Miniaturization of a Planar EBG Structure by Using Double Power Plane

    116 ( 223 )   41 - 45   2016.9

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  • B-4-41 Optimization Method of On-board RL Snubber Parameters in Common Power Distribution Networks

    Kawata Naoki, Yano Yuusuke, Iokibe Kengo, Toyota Yoshitaka

    Proceedings of the IEICE General Conference   2016 ( 1 )   361 - 361   2016.3

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  • B-4-61 A Study on Signal-to-Noise Ratio of Side-Channel Traces for Evaluation of Attacking Cost of Cryptographic Modules

    Yano Yusuke, Iokibe Kengo, Toyota Yoshitaka

    Proceedings of the IEICE General Conference   2016 ( 1 )   381 - 381   2016.3

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  • Modeling of Current Probe and Simulation with Modal Equivalent Circuit in Common-mode Current Injection to Cable

    115 ( 427 )   65 - 70   2016.1

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  • Optimal Design of Vialess Open-stub EBG structure for Power-bus Noise Reduction

    Kohtaro Okimoto, Kengo Iokibe, Yoshitaka Toyota, Koichi Kondo, Shigeyoshi Yoshida, Toshiyuki Kaneko

    2016 IEEE CPMT SYMPOSIUM JAPAN (ICSJ)   243 - 246   2016

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    To overcome the intra EMC problems in wireless communications, electromagnetic bandgap (EBG) structures can be used to effectively reduce power-bus noise. We previously proposed a vialess open-stub EBG structure. However, it still has the intrinsic disadvantage of a narrow stopband because it uses the open-stub's resonance. Thus, this paper aims to optimize the structural parameters of the vialess open-stub EBG structure to sufficiently suppress power-bus noise in a wider stopband. The structural parameters to determine the noise-reduction performance of the vialess open-stub EBG structure are the branch width rob, the stub width w(s), and the unit-cell length alpha. Rectangular power buses were designed as test vehicles through the analytical approach and used to evaluate the stopband expansion and the noise suppression in the stopband in a full wave simulation. The transmission characteristics showed that, after w(b), W-s, and a are optimized, the stopband is expanded from 0.61 GHz (2.23-2.84 GHz) to 1.56 GHz (2.20-3.76 GHz). In addition, an optimized structure was made that reduced the amount of noise by approximately 10 dB.

    DOI: 10.1109/ICSJ.2016.7801273

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  • Evaluation of Information Leakage caused by Hardware Trojans Implementable in IC Peripheral Circuits

    Kengo Iokibe, Yoshitaka Toyota

    Proceedings of 2016 Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity   701   2016

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  • Design Methodology of Tightly Coupled Asymmetrically Tapered Bend for High-density Mounting in Differential Transmission Lines

    Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota

    2016 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)   463 - 465   2016

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    The bend in a pair of differential transmission lines on printed circuit boards causes a path difference, which leads to mode conversion due to the phase difference. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion. In this paper, we propose a design methodology of our tightly coupled asymmetrically tapered bend that limits the bend structure within the area of the original classic bend for high-density mounting. We also evaluated the 45-degree-angle bend formed based on our design methodology and found that the methodology helps improve or maintain its transmission characteristics compared to those of the classic bend.

    DOI: 10.1109/APEMC.2016.7522769

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  • Modal-equivalent Circuit with Injection Probe Models for Electromagnetic Immunity Analysis

    Koji Kumegawa, Kengo Iokibe, Yoshitaka Toyota

    2016 URSI Asia-Pacific Radio Science Conference (AP-RASC 2016), S-E1-3   130 - 133   2016

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  • A Study of Linear Equivalent Circuit Modeling for Conducted Disturbance Estimation of Power Converter Circuit

    Yusuke Yano, Hiroki Geshi, Kengo Iokibe, Tetsushi Watanabe, Yoshitaka Toyota, trial Technology Center of Okayama Pre

    2016 URSI Asia-Pacific Radio Science Conference (AP-RASC 2016), S-E1-5   138 - 141   2016

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  • Security Deterioration of Advanced Encryption Standard Circuit by Fluctuations of Side-Channel Traces in Fault Analysis Attack

    Shinsuke Horinouchi, Kengo Iokibe, Hiroto Kagotani, Tetsushi Watanabe, Yoshitaka Toyota, trial Technology Center of Okayama Pre

    2016 URSI Asia-Pacific Radio Science Conference (AP-RASC 2016), S-E5-5   1284 - 1287   2016

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  • Reduction in Common-mode Noise Generation by Placing Capacitors at Mode-conversion Positions in Power Distribution Network

    115 ( 29 )   7 - 12   2015.5

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  • A Vialess Open-stub EBG Structure for Power-bus Noise Reduction

    YAMASHITA Yuki, TOYOTA Yoshitaka, IOKIBE Kengo, KONDO Koichi, YOSHIDA Shigeyoshi, KANEKO Toshiyuki

    IEICE technical report. Electromagnetic compatibility   114 ( 398 )   57 - 62   2015.1

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    Electromagnetic bandgap (EBG) formed by a periodic structure (EBG structure) has been studied for reducing power-bus noise of printed circuit boards. The EBG structure obtains a large amount of noise suppression and is available for separating simultaneous switching noise generated in digital circuits and small rf signal in analog circuits on mixed-signal boards. Many kinds of EBG structures have been so far proposed and can be roughly classified into two types with and without vias. We have focused on Planar EBG structures without vias because they consist of only two layers and cost-effective due to no vias. In contrast, open-stub EBG structure, which is one of EBG structures with vias, is easy to miniaturize its cell size independently of suppression frequency. We considered that the open-stub EBG structure was specialized for the EBG structures with vias. In this report, however, a planer EBG structure with open stub is proposed by inventing a new structure. The effect of power-bus noise reduction is examined by full-wave simulation and validated in the 2.4 GHz band.

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  • Effect of Mg loading on the high-frequency tunability of Ba0.8Sr0.2TiO3 ceramics

    Takashi Teranishi, Tsuyoshi Sogabe, Hidetaka Hayashi, Akira Kishimoto, Kengo Iokibe, Yoshitaka Toyota

    JAPANESE JOURNAL OF APPLIED PHYSICS   54 ( 1 )   11502-1-011502-6   2015.1

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    The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

    DOI: 10.7567/JJAP.54.011502

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  • Security Simulation against Side-Channel Attacks on Advanced Encryption Standard Circuits Based on Equivalent Circuit Model

    Kengo Iokibe, Kazuhiro Maeshima, Tetsushi Watanabe, Yoshitaka Toyota

    2015 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   224 - 229   2015

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    An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

    DOI: 10.1109/ISEMC.2015.7256163

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  • Dependence of Power Distribution Network Impedance on Circuits Implemented in Field Programmable Gate Array

    Nobuhiro Tai, Kengo Iokibe, Yoshitaka Toyota, Tetsushi Watanabe, trial Technology Center of Okayama Pre

    Eighth 2015 Korea-Japan Joint Conference on EMT/EMC/BE (KJJC-2015), P-09, Sendai, Japan   85 - 86   2015

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  • Conducted Disturbance Estimation of Power Converter Circuits Based on Linear Equivalent Circuit Model for EMI Filter Design

    Hiroki Geshi, Kengo Iokibe, Yoshitaka Toyota, Tetsushi Watanabe, trial Technology Center of Okayama Pre

    Eighth 2015 Korea-Japan Joint Conference on EMT/EMC/BE (KJJC-2015), P-11, Sendai, Japan   89 - 90   2015

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  • Miniaturization of a Planar EBG Structure Using Interdigital Electrodes

    Yuki Yamashita, Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida, Toshiyuki Kaneko

    2015 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM   39 - 42   2015

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    This paper describes a proposed planar electromagnetic bandgap (EBG) structure whose unit cell size is miniaturized through the use of interdigital electrodes (IDEs). For planar EBG structures in general, it is difficult to miniaturize the cell size independently of stopband frequency because the stopband frequency depends on the cell size. For the proposed structure, however, the cell size can be miniaturized because the IDEs help enlarge the capacitance between adjacent unit cells and utilize a resonator formed in the unit cells. Because the resonator's resonant frequency determines the stopband frequency of an EBG structure with IDEs, the cell size can be miniaturized independently of the stopband frequency. In the work described in this paper, the proposed EBG structure's efficacy in reducing power bus noise was examined and evaluated through full-wave simulation and measurement in the wireless communication band. It was found that an IDE-EBG structure with a small (25 mm(2)) unit cell is a valid means for achieving power bus noise reduction.

    DOI: 10.1109/EDAPS.2015.7383703

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  • Formulation of Mode Conversion in Differential Transmission Lines with Bend Discontinuity

    Keita Takariki, Kengo Iokibe, Yoshitaka Toyota

    2015 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM   152 - 155   2015

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    This paper formulates mode conversions of transmission and reflection from differential mode to common mode in differential transmission lines with bend discontinuity using a very simple model. The formulae tell us that the mode conversion is caused by not only the path difference in the bend but also the difference between the characteristic impedance and port impedance. The formulae were validated by full-wave simulation under the assumption that effect of the bend region is small and results showed that path difference reduction and impedance matching at the input and output ports are significant in suppressing mode conversion. This suggests that the tightly coupled asymmetrically tapered bend proposed by the authors should be effective for suppressing mode conversion.

    DOI: 10.1109/EDAPS.2015.7383689

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  • Reduction methods of power supply noise due to power distribution network resonance in ICs

    Kengo Iokibe, Yoshitaka Toyota

    Journal of Japan Institute of Electronics Packaging   18 ( 5 )   344 - 347   2015

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    DOI: 10.5104/jiep.18.344

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  • 電磁セキュリティに関する暗号機器の安全性評価の現状と課題

    五百旗頭健吾

    電磁環境工学情報EMC   331   24 - 33   2015

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  • Electromagnetic Immunity Analysis Using Modal-equivalent Circuit in Cable Interconnection System

    Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga

    2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)   716 - 719   2015

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    Electromagnetic immunity analysis as well as electromagnetic emission analysis is significant for EMC design. In this paper, we apply a modal equivalent-circuit model with mode-conversion sources to electromagnetic immunity analysis in a simple cable interconnection system. The analysis can treat mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis and has been validated in electromagnetic emission analysis. The approach takes an advantage in less calculation sources and helps get design considerations compared with full-wave simulation. In this paper, common-mode excitation by a current probe in a simple cable interconnection system is investigated for model validation. As a result, it is demonstrated that the circuit analysis with the modal-equivalent circuit model agrees well with the measurement results.

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  • Investigation in burst pulse injection method for fault based cryptanalysis Reviewed

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    IEEE International Symposium on Electromagnetic Compatibility   2014- ( September )   743 - 747   2014.9

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    This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

    DOI: 10.1109/ISEMC.2014.6899067

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  • Guard Trace with Periodic Structure Taking Signal Integrity into Account

    Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

    2014 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING & SYSTEMS SYMPOSIUM (EDAPS)   45 - 48   2014

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    The guard trace is effective for suppressing common-mode generation caused by placing a signal trace too close to the return edge on a printed circuit board. In our previous study, a guard trace with a periodic structure was proposed not only to reduce common-mode radiation but also to maintain signal integrity and was found to be effective. In the current work, the shape of the periodic structure and the termination at both edges to improve the features was investigated through full-wave simulation and measurement from the viewpoint of transmission coefficient as well as far-field radiation. Results show that the smaller the widths of the narrow portion, the further the periodic structure helps reduce common-mode radiation and maintain signal integrity. Also shown is that the periodic guard trace with both ends connected to the return plane is an appropriate structure.

    DOI: 10.1109/EDAPS.2014.7030811

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  • Analysis on Equivalent Current Source of AES-128 Circuit for HD Power Model Verification

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuvuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO)   302 - 305   2014

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    We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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  • Guard Trace with Periodic Structure for Reducing Common-mode Radiation and Maintaining Signal Integrity

    Yuho Terai, Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO)   545 - 548   2014

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    The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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  • Ferrite-covered Open Stub as Lossy Resonator Filter for Suppressing Noise Propagation in Power Bus

    Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC EUROPE)   765 - 769   2014

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    A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

    DOI: 10.1109/EMCEurope.2014.6931007

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  • Modal Equivalent Circuit of Bend Discontinuity in Differential Transmission Lines

    Yoshitaka Toyota, Shohei Kan, Kengo Iokibe

    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO)   117 - 120   2014

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    The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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  • Suppression of Mode Conversion by Decreasing Path Difference by using an Asymmetrically Tapered Bend in Differential Transmission Lines

    Shohei Kan, Yoshitaka Toyota, Kengo Iokibe, Tetsushi Watanabe

    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO)   129 - 132   2014

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    A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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  • 外来電磁パルスに対するセキュリティ評価手法の確立-パルス注入タイミングと発生するフォルトの関係-

    渡辺哲史, 五百旗頭健吾

    岡山県工業技術センター報告   ( 40 )   2014

  • Investigation in Burst Pulse Injection Method for Fault Based Cryptanalysis Reviewed

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   743 - 747   2014

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    This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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  • Investigation on Aes Circuites in Information-Leaking-Behavior by Means of Internal Equivalent Current Source

    田井伸拓, 五百旗頭健吾, 籠谷裕人, 大西紘之, 前島一仁, 豊田啓孝, 渡辺哲史

    電子情報通信学会技術研究報告   114 ( 93(EMCJ2014 10-16) )   2014

  • Evaluation of Pigtail Termination of STP cable Using Modal Equivalent Circuit of Four-conductor Transmission Systems

    Tatsuya Nobunaga, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Tetsushi Watanabe

    PROCEEDINGS OF 2013 URSI INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC THEORY (EMTS)   222 - 225   2013

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    For investigating mode conversion in four-conductor transmission systems we have developed a modal-equivalent-circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in three-conductor transmission systems. The modal equivalent circuit consists of three modal equivalent circuits of normal mode, primary-common mode, and secondary-common mode. In this paper, the influence of mode conversion by the pigtail termination of a shielded-twisted-pair (STP) cable was analyzed using the modal equivalent circuit and mixed-mode S parameters with respect to normal mode and primary- common mode. As a result, it was found that mode conversion depends on the imbalance factor and that the modal equivalent circuit helps to explain mode conversion that occurs in terminating STP cables with pigtail.

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  • Improvement of Linear Equivalent Circuit Model to Identify Simultaneous Switching Noise Current in Cryptographic Integrated Circuits

    Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota, Tetsushi Watanabe

    2013 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   834 - 839   2013

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    The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

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  • Mode Conversion Caused by Discontinuity in Transmission Line From Viewpoint of Imbalance Factor and Modal Characteristic Impedance

    Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga

    2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS)   52 - 55   2013

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    For treating mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis, we have proposed a modal equivalent-circuit model with mode-conversion sources. The approach takes an advantage in less calculation sources and countermeasure consideration compared with full-wave simulation. A mode-decomposition technique was applied with an imbalance factor, that is, the current division factor in our study, of the transmission line. In the modal circuit analysis we proposed, mode conversion is expressed by the controlled sources of which magnitude is proportional to the difference between the current division factors of the adjacent transmission lines. In this paper, we focused on the modal transfer power and derived the mathematical expressions of the mode conversion using the modal characteristic impedance as well as the current division factor. For validating the derived equations, in addition, the comparison with full-wave simulation was carried out and a good agreement was confirmed.

    DOI: 10.1109/EDAPS.2013.6724455

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  • Estimation of Data-Dependent Power Voltage Variations of FPGA by Equivalent Circuit Modeling from On-Board Measurements

    Kengo Iokibe, Yoshitaka Toyota

    2013 9TH INTERNATIONAL WORKSHOP ON ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2013)   175 - 179   2013

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    An equivalent circuit model was evaluated in simulating data-dependent power voltage variations of a field-programmable gate array (FPGA). The equivalent circuit model was Linear Equivalent Circuit and Current Source (LECCS) model representing dynamic switching current inside the FPGA with an equivalent current source. The current source was supposed to depend on input data for the FPGA on which a cryptographic circuit was implemented. Model identification was based on the procedure of LECCS model identification from on-board measurements and the current source was identified for all values of input data used in this work. The identified current source was investigated in accordance with the operation process of the cryptographic circuit and found an excellent correlation to the operation process. The identified LECCS model was combined with an equivalent circuit of the power distribution network for the FPGA core circuit to simulate power voltage variations for the 1,000 input texts. The simulated variation waveforms were compared to the corresponding measured ones to evaluate the LECCS model. Results indicated that the simulated and measured power variations matched excellently for all input data with high cross-correlation coefficients from 0.7 to 0.9. LECCS model is, therefore, able to predict the data-dependent power voltage variation by combining a PDN equivalent circuit.

    DOI: 10.1109/EMCCompo.2013.6735196

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  • EMC技術者から見たサイドチャネル攻撃とその対策設計

    五百旗頭健吾

    電磁環境工学情報EMC   26 ( 6 )   40 - 53   2013

  • Optimization of Resistances in RL Snubbers for Power Distribution Network of Integrated Circuits

    Ryosuke Yamagata, Kengo Iokibe, Yoshitaka Toyota

    Proceedings of 2013 URSI International Symposium on Electromagnetic Theory (EMTS)   226 - 229   2013

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  • Improvement of Linear Equivalent Circuit Model to Identify Simultaneous Switching Noise Current in Cryptographic Integrated Circuits

    Kengo Iokibe, Tetsuo Amano, Kaoru Okamoto, Yoshitaka Toyota, Tetsushi Watanabe

    2013 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   834 - 839   2013

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    The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

    DOI: 10.1109/ISEMC.2013.6670526

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  • Suppression of Power-bus Resonance by Lossy Resonator Filter Consisting of Open Stub and Magnetic Thin Film

    Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

    2013 International Symposium on Electromagnetic Compatibility (EMC Europe 2013)   943 - 948   2013

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  • RF Noise Suppression by Lossy Filters in Power Distribution Network

    Yoshitaka Toyota, Kengo Iokibe

    IEEE CPMT Symposium Japan (ICSJ 2013)   2013

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  • Effect of EBG structure and ferrite film on power/ground layers for performance maintenance and noise suppression in wireless communication

    Kenta Ishimura, Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

    EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium   217 - 220   2013

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    Noise suppression and power integrity are two requirements for power/ground layers of printed circuit boards. To accomplish the requirements, we proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. To evaluate the proposed EBG structure, we have so far measured the electric characteristics of both driving-point impedance and transmission coefficient. Although these evaluation indices are helpful, the evaluation using an actual device is also indispensable. In this paper, we evaluated the suppression of noise propagation through power bus by the proposed EBG structure in wireless communication module. The proposed structure provided sufficient result of the effective maintenance of communication quality by suppressing the propagation of electromagnetic noise. © 2013 IEEE.

    DOI: 10.1109/EDAPS.2013.6724428

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  • Electromagnetic Simulation of Printed Circuit Board Adjacent to Conductor Using Equivalent Model Focusing on Common-mode

    Yuli Wakaduki, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Tetsushi Watanabe

    13th International Symposium on Electronics Packaging (ICEP2013)   707 - 712   2013

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  • 外来電磁波に対するセキュリティ評価手法の確立-フォルト発生条件の検討-

    渡辺哲史, 五百旗頭健吾

    岡山県工業技術センター報告   ( 39 )   2013

  • Simulation and Requirements of Modal-Equivalent-Circuit Model in Propagation through Inhomogeneous Media

    K. Sejima, Y. Toyota, K. Iokibe, L. R. Koga, T. Watanabe

    IEICE Transactions on Communications (Japanese Edition)   J96 ( 4 )   389 - 397   2013

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  • 等価回路モデルを用いたボードレベルでのサイドチャネル攻撃シミュレーション

    五百旗頭健吾, 豊田啓孝

    電子情報通信学会大会講演論文集(CD-ROM)   2013   2013

  • サイドチャネル攻撃予測のための暗号FPGAの等価電流源同定

    五百旗頭健吾, 岡本薫, 天野哲夫, 豊田啓孝, 渡辺哲史

    電子情報通信学会大会講演論文集   2013   2013

  • Modal Equivalent Circuit with Mode-Conversion Sources for Investigating Cable Interconnection with Different Imbalance Factors

    Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga

    2012 Korea-Japan EMT/EMC/BE Joint Conference (KJJC-2012), EMC-2P-4, Seoul, Korea   287 - 290   2012

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  • Insertion of Parallel RL Circuits into Power Distribution Network for Simultaneous Switching Current Reduction and Power Integrity

    Kengo Iokibe, Yusuke Yano, Yoshitaka Toyota

    2012 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)   417 - 420   2012

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    We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

    DOI: 10.1109/APEMC.2012.6237943

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  • Experimental Model Validation of Mode-conversion Sources Introduced to Modal Equivalent Circuit

    Kota Sejima, Yoshitaka Toyota, Kengo Iokibe, Liuji R. Koga, Tetsushi Watanabe

    2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   492 - 497   2012

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    We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Delta h). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Delta h becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity.

    DOI: 10.1109/ISEMC.2012.6351682

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  • Equivalent Current Source of Side-channel Signal for Countermeasure Design with Analog Circuit Simulator

    Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

    2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   806 - 811   2012

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    Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication.

    DOI: 10.1109/ISEMC.2012.6351661

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  • Identification of Equivalent Current Source of Cryptographic Circuit Based on Impedance and Current Measurements at Board Level

    Kaoru Okamoto, Tetsuo Amano, Kengo Iokibe, Yoshitaka Toyota

    2012 PROCEEDINGS OF SICE ANNUAL CONFERENCE (SICE)   73 - 78   2012

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    Side-channel attacks are a kind of cryptanalytic attacks by means of the electric current in the range of radio frequency (RF) leaking out from a cryptographic integrated circuit (IC) and/or the electromagnetic radiation generated by the RF power current. The RF power current is caused by simultaneous switching activities of logic gates during an encryption process operated in the cryptographic IC. The RF power current is a major cause of the electromagnetic interference (EMI). To decrease the RF power current at PCB level can lead to decrease designing costs. As a preparation of applying LECCS models to a cryptographic IC for estimating the RF power current occurred during an encryption process, the model parameters were identified from measurements in this paper. The LECCS models were composed of a current source that expressed the RF power current occurred in the cryptographic circuit and a passive network. The current source identified grown in amplitude 200 ns after the beginning of the encryption process. This agreed to the beginning of the target round. In frequency domain, current spectra were seen at 24 MHz and its harmonics. The authors obtained waveforms of the RF power current from analog circuit simulations with the LECCS model identified, and validated the cryptographic device in security against the side-channel attacks by means of the correlation power analysis (CPA) method. Results of CPA with the simulated waveforms were consistent to CPA results with measured waveforms. These results means that model parameters were identified correctly, and suggests that the LECCS model is effective for validation of cryptographic devices with respect to side-channel attacks.

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  • Very short critical path implementation of AES with direct logic gates

    Kenta Nekado, Yasuyuki Nogami, Kengo Iokibe

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   7631   51 - 68   2012

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    A lot of improvements and optimizations for the hardware implementation of AES algorithm have been reported. These reports often use, instead of arithmetic operations in the AES original, those in its isomorphic tower field and. This paper focuses on which provides higher-speed arithmetic operations than. In the case of adopting, not only high-speed arithmetic operations in but also high-speed basis conversion matrices from the to should be used. Thus, this paper improves arithmetic operations in with Redundantly Represented Basis (RRB), and provides basis conversion matrices with More Miscellaneously Mixed Bases (MMMB). © Springer-Verlag Berlin Heidelberg 2012.

    DOI: 10.1007/978-3-642-34117-5-4

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  • Lossy Resonators for Suppressing Power-bus Resonance of Printed Circuit Board

    Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe

    5th Pan-Pacific EMC Joint Meeting (PPEMC'12), Tokyo, Japan   65 - 68   2012

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  • Optimal Resistance Determination Method for RL Damper Circuits in Power Distribution Network of ICs Reviewed

    Ryosuke Yamagata, Kengo Iokibe, Yoshitaka Toyota

    2012 6TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS (CEEM' 2012)   222 - 225   2012

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    We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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  • Evaluation of Relationship between STP-cable Grounding and Mode Conversion Taking into Account Imbalance Factor Reviewed

    Tatsuya Nobunaga, Yoshitaka Toyota, Kengo Iokibe, Liuji Koga, Tetsushi Watanabe

    2012 6TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS (CEEM' 2012)   119 - 119   2012

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    In grounding an STP cable, mode conversion occurs depending on how to ground it. For investigating the mode conversion in a four-conductor transmission-line system that consists of three conductors and the system ground such as the STP cable above the system ground, as shown in Fig. I. we have developed modal equivalent circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in a three-conductor transmission-line system. The modal equivalent circuit consists of three modal equivalent circuits of normal mode (Fig. 2), primary common mode (Fig. 3), and secondary common mode(Fig. 4). In this paper, mode conversion between normal mode and primary common mode was evaluated using mixed-mode S parameters and the measured data validated the modal equivalent circuit. As a result, it was found that mode conversion depends on the imbalance factor and it was examined how to ground for suppressing mode conversion.

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  • Measurement of Self-Inductance of IC Package with THRU Pattern Embedded Instead of Chip

    TANIMICHI Ayumi, IOKIBE Kengo, TOYOTA Yoshitaka

    IEICE technical report   111 ( 131 )   31 - 36   2011.7

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    In IC package modeling of electrical properties, to compare model parameters extracted from results of electromagnetic calculations to those obtained from measurements is an important method for validation of the model. Only direct probing methods for special package, however, had been reported in literature. There is no method for actual packages molded with resin and mounted on printed circuit board. This paper proposes an extraction method of self-inductance of actual IC packages. Four test packages consisted of interposer and bonding wires were employed for validation of the method. Self-inductances of the four packages were extracted from measured impedance parameters obtained by a two ports measurement at board level. The test package contained a THRU line instead of IC-chip. By subtracting inductance of the THRU line from inductance between the two ports of measurement, the package inductance was obtained. As a result, the self-inductance were obtained with absolute errors between -0.8 and -0.2 nH in measurement, between -0.9 〜 -0.6 nH in electromagnetic calculations.

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  • Control and design of stopband by applying two stubs to open-stub EBG structure

    NAGAO Atsushi, TOYOTA Yoshitaka, IOKIBE Kengo

    IEICE technical report   111 ( 131 )   91 - 96   2011.7

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    To suppress the parallel resonance between power/ground planes on printed circuit boards, electromagnetic bandgap (EBG) structure can be applied. The open-stub EBG structure with two stubs in a unit cell is expected to miniaturize the cell size, expand the stopband and form multi-stopbands. In addition to, compare it with mushroom-type EBG structure and open-stub EBG structure with one stub through equivalent-circuit analysis, we established the design methodology to realize both stopbands of 2.4 GHz and 5.2 GHz. As a result, different lengths with two stubs led separate stopbands of 2.4 GHz and 5.2 GHz. Furthermore, we evaluated the difference of spiral stub length between the equivalent circuit model using characteristic parameters and electromagnetic simulation that requires the physical sizes.

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  • Evaluation of Power/Ground Layers with EBG structure and Ferrite Film for Noise Suppression and Power-Integrity Improvement

    MAHMOOD Farhan Zaheed, TOYOTA Yoshitaka, IOKIBE Kengo, KONDO Koichi, YOSHIDA Shigeyoshi

    IEICE technical report   111 ( 66 )   75 - 80   2011.5

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    Power/ground layers of Printed Circuit Board (PCB) require two conditions of noise suppression and power integrity (PI). We proposed the application of Electromagnetic Bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for EMI and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate PI characteristics for assuming a real power-supply circuit. Through the evaluation, the proposed structure provided sufficient results. Also almost same characteristics was provided by the test board with only ferrite film.

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  • Mode-equivalent Modeling and Identification of System with Cable Interconnection between Transmitter and Receiver Pairs (Part 2)

    SEJIMA Kota, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Liuji R., WATANABE Tetsushi

    IEICE technical report   111 ( 66 )   93 - 98   2011.5

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    At the interface where two transmission lines with different current division factors are connected, there occurs mode conversion. Focusing on a transmission system where a microstrip line on printed circuit board with a transmitter or a receiver is connected to a two-wire line above the system ground, the modal equivalent-circuit model with mode-conversion sources was developed. The model was validated by comparing common mode current and normal-mode voltage between measurement and circuit simulation. As a result, both spectra have a good agreement, which indicates that mode conversion is expressed using the proposed mode-conversion sources. According to the model, two approaches were carried out to reduce normal-mode voltage in common-mode resonance: reduction in the difference of current division factors and reduction in common-mode current. It was found that both approaches can suppress mode conversion as expected by the model.

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  • B-4-39 On-Board Decoupling to Improve Tolerance of Cryptographic Board against Side-Channel Attacks

    Iokibe Kengo, Toyota Yoshitaka

    Proceedings of the IEICE General Conference   2011 ( 1 )   352 - 352   2011.2

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  • Mode-equivalent Modelling of System Consisting of Transmission Lines with Different Imbalance Factors

    Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Tetsushi Watanabe

    2011 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC2011)   676 - 679   2011

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  • On-Board Decoupling of Cryptographic FPGA to Improve Tolerance to Side-Channel Attacks

    Kengo Iokibe, Tetsuo Amano, Yoshitaka Toyota

    2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   925 - 930   2011

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    One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules.

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  • Power/Ground Layers with EBG Structure and Ferrite Film for Noise Suppression and Power Integrity Improvement

    Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe, Koichi Kondo, Shigeyoshi Yoshida

    2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS)   2011

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    Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs). We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for noise-suppression and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit. Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results.

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  • B-4-40 Control of Stopband by Applying Two Stubs to Open-stub EBG Structure

    Nagao Atsushi, Toyota Yoshitaka, Iokibe Kengo, Koga Liuji R.

    Proceedings of the IEICE General Conference   353 - 353   2011

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  • Mode-equivalent Modeling and Identification of System with Cable Interconnection between Transmitter and Receiver Pairs

    TOYOTA Yoshitaka, WATANABE Tetsushi, IOKIBE Kengo, KOGA Ryuji

    IEICE technical report   110 ( 300 )   33 - 38   2010.11

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    In the transmission system where a transmitter and receiver are connected with a cable at a certain distance above the system ground, a mode equivalent-circuit model is proposed to estimate mode current flowing along the system. The simple model is based on mode-decomposition technique and places mode-conversion voltage source and current source at the interface between the transmitter/receiver and the cable where the current division factors are different. In this study, a simple cable interconnection system without dielectric was used to estimate the common-mode current flowing along the system. The circuit simulation using the proposed model showed a good agreement with the circuit simulation regarding as coupled transmission lines. In addition, the mode-current spectrum is found to be close to that obtained from full-wave analysis. Some discrepancy was observed as the distance from the system ground gets larger.

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  • A Combined IC Macro Model of IBIS and LECCS-Core Models for PI/SI Analyses

    OKA Norimasa, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji

    The IEICE transactions on electronics C   93 ( 11 )   433 - 444   2010.11

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  • BI-2-3 Validation of Parasitic Couplings and Combination with IBIS for PI/SI Calculation in LECCS Model

    Iokibe Kengo, Toyota Yoshitaka, Koga Ryuji, Oka Norimasa

    Proceedings of the Society Conference of IEICE   2010 ( 1 )   "SS - 81"-"SS-82"   2010.8

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  • Effective Position of Decoupling Inductor Taking Parasitic Capacitances on Power Distribution Network Traces into Account

    YANO Yusuke, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji

    IEICE technical report   110 ( 125 )   39 - 44   2010.7

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    High-frequency current caused by simultaneous switching of digital gates can be increased with decoupling capacitors, because equivalent series inductance (ESL) of the decoupling capacitors makes resonance with parasitic capacitance on power distribution network trace. In this report, we discussed the location of decoupling inductors as a countermeasure and to reduce the high frequency power current by a circuit simulation. We employed a four-layered printed circuit board as a device under test. The board included an oscillation circuit with a versatile inverter IC and a power distribution network. The board was modeled with a linear equivalent circuit and a current source (LECCS) for the circuit simulations of the RF powe current and power bounce. Results of the circuit simulations showed that reduction of the RF power current was larger with a decoupling inductor placed between the decoupling capacitor and the parasitic capacitance than out side the parasitic capacitance, though a peak current could be occur due to a resonance the parasitic capacitance contributed. The RF power current was reduced at all frequencies even when the decoupling inductor was placed outside the parasitic capacitance. In addition, in order to investigate influence on power integrity (PI) performance of the IC, potential difference between power terminals of chip was calculated. The simulation results showed that the decoupling inductors caused trivial deterioration in P1 performance of the IC.

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  • Linear Equivalent Circuit Model of Inverter in Microwave Oven for EMI Filter Design

    IOKIBE Kengo, WATANABE Tetsushi, SAKIYAMA Kazuyuki, SAITO Yoshiyuki, TOYOTA Yoshitaka, KOGA Ryuji

    IEICE technical report   110 ( 84 )   25 - 30   2010.6

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    A Linear equivalent circuit model of inverter was proposed for applying to designing EMC filters to reduce the conducted emission from electrical appliances with switched-mode power supplys as inverters and converters. We employed a microwave oven as the equipment under test(EUT)and measured the conducted emission voltage at mains port with a line impedance stabilizing network(LISN). Measured disturbances contained both the differential and common modes and we determined the proposed model to have a circuitry structure composed of differential- and common-mode blocks. We, then, described a simple method to determine model parameters from measurements and decided the parameters with the method. With the proposed model, the conducted emission voltage of the EUT was estimated through circuitry simulation and compared to measurement. The comparison showed that the model predicted performance of the EMI filter in reduction of the conducted emission in practical accuracies at frequencies in which model parameters determined had been reasonable.

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  • Modeling and Identification of Common-mode System in Cable Interconnection between Transmitter and Receiver Pairs

    MORIMITSU Kazuya, SONG Nannan, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji

    IEICE technical report   110 ( 17 )   19 - 24   2010.4

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    In the transmission system where a transmitter and receiver are connected with a cable at a certain distance above the system ground, a common-mode equivalent-circuit model is proposed to estimate common-mode current flowing along the system. The simple model is based on the imbalance difference model that tells that a common-mode electromotive force occurs at an interface between the transmitter/receiver and the cable because their different imbalance factors generates common-mode current. In this study, a simple cable interconnection system between transmitter and receiver pairs was set up to examine an estimation of the common-mode current flowing along the system by using the model. In addition, an evaluation parameter of transfer admittance, given by the ratio of the common-mode current to the normal-mode voltage, was introduced. The measurement and circuit simulation were carried out changing conditions such as grounding, the total length of the system, the distance from the system ground, and the imbalance parameter. The measured and the simulated results agreed well each other and hence the validity of the model was found.

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  • B-4-5 Accuracy Evaluation of Combined IBIS and LECCS Macro Models by SPICE Simulations for PI and SI Performances

    OKA Norimasa, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji

    Proceedings of the IEICE General Conference   2010 ( 1 )   355 - 355   2010.3

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  • Development of a Equivalent Circuit Model with Transmission Line Model for Designing Filter Formed on Printed Circuit Boards

    MATSUMOTO Keisuke, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji

    IEICE technical report   109 ( 370 )   81 - 86   2010.1

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    Slit pattern formed on return plane of printed circuit boards behaves like a passive element. A defected ground structure (DGS) is one of them. The characteristics of DGS easily varies with the slit pattern so that it is expected for various applications. Since a design method has not been developed, however, we need to establish the method to design a slit pattern. Some equivalent circuit models have been used but they consist of lumped elements and require full-wave simulation. In addition, value of the lumped elements have no relation to a physical parameters. So it is not useful for filter designing. In this report, we proposed equivalent circuit model with transmission line model for DGS with filter function. Transmission characteristic was calculated by both full-wave simulator and circuit simulator with the proposed equivalent circuit model and the first stop-band width calculated by circuit simulator was in agreement with full-wave simulator.

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  • Stopband Characteristics of Planar-type Electromagnetic Bandgap Structure with Ferrite Film

    Yoshitaka Toyota, Koichi Kondo, Shigeyoshi Yoshida, Kengo Iokibe, Ryuji Koga

    2010 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY & TECHNICAL EXHIBITION ON EMC RF/MICROWAVE MEASUREMENTS & INSTRUMENTATION   664 - 667   2010

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    The noise suppression effect after interposing a ferrite film of several microns in thickness between the power and ground planes is discussed in this paper. In particular, we focused on the combination of a planar electromagnetic bandgap structure with a ferrite film deposited by using spin spray ferrite plating at a low temperature. In this paper, the stopband characteristics are discussed through the use of both simulation and measurement results. First, a full-wave electromagnetic simulation revealed that a test board with a dielectric as thin as a few hundreds of microns has the stopband characteristics of the frequency shift towards the lower frequencies (miniaturization effect) and stopband expansion with the removal of the passband, which was not observed in the case of a thick-dielectric test board. The simulation results also demonstrated that these improvements mainly resulted from the complex permeability of the ferrite film. Next, we found that the measurements are very similar to the simulation results.

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  • Development of Equivalent Circuit Model with Transmission Line Model for Designing Filters Formed on Printed Circuit Boards

    Keisuke Matsumoto, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga

    2010 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC 2010)   289 - 294   2010

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    The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator.

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  • Application of IC Macro Model (LECCS) to Bypass Circuit Design for Improving EMI/PI Performance

    OKA Norimasa, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji

    IEICE technical report   109 ( 241 )   141 - 146   2009.10

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    An IC macro model for power current analysis, called linear equivalent circuit and current source (LECCS) model, is applied to a bypass circuit design. In the bypass circuit design, since requirements to improve electromagnetic interference (EMI) and power integrity (PI) performances are becoming more and more important, improving methods are considered using the LECCS model. The LECCS model, consisting of a linear equivalent circuit and current sources, the former is closely related to EMI performance and the latter is connected to PI performance. Therefore, each idea for better performance is different. Actually examples of bypass circuits based on the idea are shown, and it is verified that the circuits work out by using a SPICE model.

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  • Application of IC Macro Model (LECCS) to Bypass Circuit Design for Improving EMI/PI Performance

    OKA Norimasa, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji

    IEICE technical report   109 ( 242 )   141 - 146   2009.10

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    An IC macro model for power current analysis, called linear equivalent circuit and current source (LECCS) model, is applied to a bypass circuit design. In the bypass circuit design, since requirements to improve electromagnetic interference (EMI) and power integrity (PI) performances are becoming more and more important, improving methods are considered using the LECCS model. The LECCS model, consisting of a linear equivalent circuit and current sources, the former is closely related to EMI performance and the latter is connected to PI performance. Therefore, each idea for better performance is different. Actually examples of bypass circuits based on the idea are shown, and it is verified that the circuits work out by using a SPICE model.

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  • B-4-56 An Equivalent Circuit Model for Designing of Band-Elimination Filter Formed on Return Plane of Printed Circuit Board

    Matsumoto Keisuke, Toyota Yoshitaka, Iokibe Kengo, Koga Ryuji

    Proceedings of the Society Conference of IEICE   2009 ( 1 )   339 - 339   2009.9

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  • Examination of EMC Macro Model LECCS-I/O with Two Current Sources Simulating Power and Output Currents of CMOS Inverter IC

    TASAKA Tomoya, OKA Norimasa, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji

    IEICE technical report   109 ( 185 )   1 - 6   2009.8

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    In the field of designing printed circuit boards (PCBs), EMC macro-models become increasingly useful to verify EMI performance of PCB with integrated circuits (ICs). This report discussed on estimations of RF currents due to the IC switching by using an IC EMC macro-model, LECCS-I/O, which had been developed to simulate RF power currents of ICs. We focused on not only the RF power current but also the output current of a CMOS I/O gate, since the EMI is caused by RF currents on both power distribution networks and signal lines. We constructed a LECCS-I/O model, with two current sources from measurements and verified the RF currents at power and output pins, comparing to another LECCS-I/O model with a single current source. Results showed that the both models estimate the power current with errors less than 5dB compared to measurements up to 500MHz. Considering the output current, the two-sources model also predicted accurately up to 500MHz, while the single-source model increased errors.

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  • Effect of Reducing Electromagnetic Noise between Power/Ground Planes with an EBG Pattern on Applying Noise Suppression Sheets

    YANO Seiji, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji, KONDO Koichi, YOSHIDA Shigeyoshi

    IEICE technical report   109 ( 18 )   7 - 12   2009.4

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    Applying the electromagnetic bandgap (EBG) structure to power/ground planes of printed circuit boards (PCBs) helps prevent electromagnetic waves from propagating between them at frequencies of interest. We experimentally demonstrated that interposing noise suppression sheet (NSS) into power bus of PCBs is effective for not only miniaturizing the EBG structure but also expanding the stopband towards higher frequencies. This paper clarifies the mechanism of the phenomenon that appears when applying the NSS to the power bus. To distinguish the effects due to permittivity and permeability of the NSS, the S-parameter measurement with the strong magnetic field applied was carried out. The measurement results showed the stopband shift towards lower frequencies results from the effect of the anisotoropic permittivity of the NSS on the electric field around the slit of the EBG pattern. The phenomenon was validated by the full-wave simulation by Microwave Studio. Also, an effective approach of applying the NSS to the EBG pattern was experimentally investigated.

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  • Effect of Frequency Step on Uncertainty of Measurement by Site VSWR Method

    WATANABE Tetsushi, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji

    IEICE technical report   109 ( 18 )   1 - 6   2009.4

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    EMI measurement over 1GHz must be operated in a free-space, open area test site. The validation method of free-space condition is called "Site Voltage Standing-wave Ratio" method, which is standardized by CISPR 16-1-4. The standard defines a new procedure for validation of EMC test sites by the ratio of maximum and minimum of transmitted voltages measured at the only 6 locations within a range of 400mm length. The small number of measurement points can cause larger uncertainty. Although the standard requires the measurement at a frequency interval of 50MHz or less, the measurement is usually performed at the largest frequency interval of 50MHz. In this paper, we propose a new approach to reduce the measurement uncertainty with a narrower frequency interval. The approach was validated by measurement as well as simulation. Also the approach was found to reduce the uncertainty caused by the location error in the measurement setup.

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  • B-4-55 Application of Common-Mode Antenna Model to Actual Printed Circuit Boards : On Antenna Elements

    FUKUMASU Keisuke, WATANABE Tetsushi, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji

    Proceedings of the IEICE General Conference   2009 ( 1 )   398 - 398   2009.3

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  • CP-2-3 Development and Application of High-Speed EMI Simulators for Supporting EMC Design

    Toyota Yoshitaka, Koga Ryuji, Iokibe Kengo, Wada Osami

    Proceedings of the IEICE General Conference   2009 ( 1 )   SS - 4-SS-5   2009

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  • Examination of power-ground resonance for IBIS model with non-ideal power supply

    OKA N.

    Int. Symp. Electromagn. Compat. Kyoto, July 2009   583 - 586   2009

  • Reduction of EMI from Differential Signaling System Using Asymmetric Guard Trace

    Tohlu Matsushima, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Osami Wada

    International Conference on Electronics Packaging 2009 (ICEP2009)   718 - 723   2009

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  • Combination of IBIS and LECCS-core models for SI analysis under non-ideal power supply conditions

    OKA N.

    Korea-Japan Joint Conference on AP/EMC/EMT, May 2009   159 - 162   2009

  • Calculation of Common-Mode Radiation from Differential Signaling System Using Imbalance Difference Model

    Tohlu Matsushima, Keisuke Fukumasu, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Osami Wada

    2009 Korea-Japan Joint Conference on AP/EMC/EMT (KJJC-AP/EMC/EMT 2009)   187 - 190   2009

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  • Estimation of Radiated Emissions from Multilayered Printed Circuit Board by Common-Mode Antenna Model Reviewed

    Yuli Wakaduki, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga

    CEEM: 2009 5TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS   242 - +   2009

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  • De-embedding of Board Parasitics with T-parameters for S-parameter Measurements of Integrated Circuits on PCB-Examinations in One-port Measurements Reviewed

    Kazuki Maeda, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga

    CEEM: 2009 5TH ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS   246 - 249   2009

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  • Evaluation of Multiple Power-Supply Pin LECCS-core Model with Different Pattern Design Boards

    HIGASHI Ryota, IOKIBE Kengo, TSUDA Takahiro, ICHIKAWA Kouji, NAKAMURA Katsumi, TOYOTA Yoshitaka, KOGA Ryuji

    IEICE technical report   108 ( 132 )   43 - 48   2008.7

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    We have proposed an EMC macro model, LECCS, to achieve fast simulations of RF power currents in IC/LSIs. The model consists of linear equivalent circuits with internal equivalent current sources. In this report, we discussed on the LECCS-core model of a 16-bit microcontroller with multiple power pins. RF power currents were measured with a model-evaluation board that is different from model-construction boards in terms of power traces. The measured currents were compared to simulated ones with the LECCS-core model and agreed within 4dB of error. The LECCS model was confirmed when in a condition that decoupling capacitors were removed. Power currents were still well simulated at each power pins as well as at a junction point where power lines meet in such decoupling conditions. We presented that the model simulates the RF power currents in good accuracy.

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  • Estimation of Electromagnetic Emissions from PCBs with a Connector through the Common-Mode Antenna Model (Part 2) : Model Improvement by Considering Connector Inductance

    WAKADUKI Yuri, TORIGOE Makoto, WATANABE Tetsushi, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji

    IEICE technical report   108 ( 132 )   37 - 42   2008.7

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    In this paper, we apply a connector model with an inductance to the common-mode antenna model. The common-mode antenna model is able to estimate common-mode radiation from a printed circuit board (PCB) fast and with low calculation cost. The previous report described that the model estimated radiation from PCBs with interconnections, depending on pin configurations of the connector. However, the calculation did not follow the frequency shift depending on pin configuration. The shift seems to result from the effective inductance of connector pins. Therefore, we developed the model considering the inductance. It was found that the modified common-mode antenna model with the connector inductance followed the frequency shift of radiation spectrum. As a result, the radiation spectrum obtained from the modified common-mode antenna model has good agreement with the measured spectrum within an error of 2dB.

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  • B-4-37 Experimental Verification of Electromotive Force of Common-mode Defined in Imbalance Difference Mechanism

    Matsushima Tohlu, Watanabe Tetsushi, Toyota Yoshitaka, Iokibe Kengo, Koga Ryuji, Wada Osami

    Proceedings of the IEICE General Conference   2008 ( 1 )   346 - 346   2008.3

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  • EMI simulation based on cavity-mode model for power-bus radiation calculation of power/ground planes with IC/LSI

    Yoshitaka Toyota, Masahiro Nishida, Kengo Iokibe, Ryuji Koga, Osami Wada

    2008 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 19TH INTERNATIONAL ZURICH SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1 AND 2   423 - +   2008

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    This paper describes an electromagnetic interference (EMI) simulation of radiated emissions caused by simultaneous switching noise in an irregular power/ground plane structure. For quick simulation of the radiated emissions from the power-bus edges, we used a series of analytical approaches: power-bus resonance characterization by a fast algorithm based on a cavity-mode model and a segmentation method and radiation calculation using equivalent magnetic current based on the field equivalent principle. The analytically based radiation calculation is achieved within a few minutes on a single personal computer and agrees with the actual measurements. Furthermore, this paper demonstrates an EMI simulation with and without decoupling capacitors by using a linear macro model of an integrated circuit as a noise source. We found a fair agreement between the simulation and measured results.

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  • Suppressing power bus resonance and radiation using and EBG structure

    Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Koichi Kondo, Shigeyoshi Yoshida

    2008 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 19TH INTERNATIONAL ZURICH SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1 AND 2   566 - +   2008

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    We investigated the effects of noise suppression by interposing magnetic materials between the power and ground planes of a printed circuit board and focused on RF transmission through and radiation from the power bus. To reduce power bus resonance and radiation, we used a commercial noise suppression sheet, which is commonly used to suppress RF noise generated from electronic devices. We also examined a thin Ni-Zn ferrite film for practical use in the future. We found that power bus resonance and radiation could be mitigated owing to the imaginary part of complex permeability of magnetic materials. The thin ferrite film with a planar electromagnetic bandgap (EBG) structure helped suppress transmission and radiation in the EBG passband.

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  • Macro Model of Driver Circuits for EMI Simulation

    Norimasa Oka, Kengo Iokibe, Yoshitaka Toyota, Ryuji Koga

    International Conference on Electronics Packaging (ICEP) 2008, 12C3-1, Tokyo   467 - 472   2008

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  • Determination of Grounding Location for Guard Trace to Reduce Common-mode Radiation

    Tohlu Matsushima, Tetsushi Watanabe, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Osami Wada

    International Conference on Electronics Packaging (ICEP) 2008, 11A3-1, Tokyo   124 - 129   2008

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  • Experimental Validation of Imbalance Difference Model to Estimate Common-Mode Excitation in PCBs

    Yoshitaka Toyota, Tohlu Matsushima, Kengo Iokibe, Ryuji Koga, Tetsushi Watanabe

    2008 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3   578 - +   2008

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    We have proposed a common-mode antenna model that is designed specifically for estimating common-mode radiation from printed circuit boards (PCBs) very quickly. The model is composed of an antenna that has the same geometry as the adjacent ground plane of the PCB and an excitation source based on an imbalance difference model. The excitation source is provided by the product of Delta h and V-N, where Delta h is the difference in current division factors related to the cross-sectional structure of the transmission line, and VN is the voltage between the signal line and return plane of the transmission line. Here, we describe an experimental validation of the common-mode excitation carried out by measuring the reduction in radiation due to a guard trace placed close to a signal line with a narrow return plane. As a result, it was found that the total common-mode excitation can be given by a superposition of two excitation sources. The results also suggest that when designing the PCB, the guard trace should be grounded at the interface between different ground-plane widths to suppress noise.

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  • Prediction of the Common-mode Radiated Emission from the Board to Board Interconnection through Common-mode Antenna Model

    Makoto Torigoe, Akifumi Sadatoshi, Yoshitaka Toyota, Kengo Iokibe, Ruji Koga, Tetsushi Watanabe, Osami Wada

    2008 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3   498 - +   2008

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    In this paper, the common-mode antenna model, which can estimate the amount of common-mode radiation quickly and accurately, was applied to a board-to-board interconnection structure with a connector. The inductor model is introduced as the connector model for improving accuracy of the common-mode antenna model. By using the inductance, which was calculated with the commercial electromagnetic field simulator, the radiated emissions estimated by the model agreed with the measurement results within an error of 3 dB around the peak emission levels.

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  • EMC Macro-modeling of CMOS Inverter Using LECCS-I/O Model with Additional Current Source

    Kengo Iokibe, Akihiro Ohsaki, Yoshitaka Toyota, Ryuji Koga, Osami Wada

    2008 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3   554 - +   2008

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    The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.

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  • Modeling of Microcontroller with Multiple Power Supply Pins for Conducted EMI Simulations

    Kengo Iokibe, Ryota Higashi, Takahiro Tsuda, Kouji Ichikawa, Katsumi Nakamura, Yoshitaka Toyota, Ryuji Koga

    IEEE EDAPS: 2008 ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM   135 - +   2008

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    An EMC macro-model of a 16-bit microcontroller with multiple-power-supply pins has been proposed for estimating the conducted EMI from a power-supply network. The macro-model, called the linear equivalent circuit and current sources (LECCS) model, is composed of multiple circuit blocks and multiple current sources corresponding to the composition of the chip circuits in the microcontroller, i.e., a current source for a circuit block. A current source statistically expresses the total RF current occurring in the corresponding circuit block. We confirmed that the proposed model could correctly estimate the RF power-supply currents under different decoupling conditions up to 300 MHz. We also found that a linear circuit of the regulator between the I/O and core circuit blocks could express the RF coupling between the two blocks.

    DOI: 10.1109/EDAPS.2008.4736018

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  • B-4-25 EMC macro-modeling of CMOS inverter with two equivalent current sources

    Iokibe Kengo, Osaki Akihiro, Toyota Yoshitaka, Koga Ryuji, Wada Osami

    Proceedings of the IEICE General Conference   334   334 - 334   2008

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  • B-4-30 Suppression of Power Bus Resonance and Radiation by High-Permeability Magnetic Metal Sheet Interposed between Power/Ground Planes of Printed Circuit Board

    Toyota Yoshitaka, Iokibe Kengo, Koga Ryuji, Kondo Koichi, Yoshida Shigeyoshi

    Proceedings of the IEICE General Conference   339 - 339   2008

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  • RF Modeling of Power-Distribution Noise in Integrated Circuits and Packages

    WADA Osami, PAOLETTI Umberto, IOKIBE Kengo, KOGA Ryuji

    Bulletin of Topical Symposium of the Magnetics Society of Japan   157   17 - 22   2007.12

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  • Investigation of Parasitic Capacitance to Improve EMC Macro Model LECCS around 1GHz

    TAKAHASHI A., IOKIBE K., PAOLETTI U., WADA O., TOYOTA Y., KOGA R.

    IEICE technical report   107 ( 167 )   5 - 10   2007.7

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    High frequency currents flowing in power supply networks of an IC/LSI has been estimated by an EMC macro model. The high frequency currents due to the simultaneous switching noise of IC/LSI involving large amount of CMOS transistor is modeled with a linear equivalent circuit and current sources. The linear equivalent circuit decreased its accuracy in impedance due to parasitic capacitances causing anti-resonances in the power supply networks. This paper shows with results of experimental and numerical analysis that the parasitic capacitances on the package and printed circuit board cause the anti-resonance. The power supply network impedance were obtained experimentally by use of three evaluation boards with different parasitic capacitances. The parasitic capacitances of the boards were calculated numerically by high-frequency electromagnetic analysis software Sonnet. Impedance simulations by considering the parasitic capacitance shows that an appropriate connection of parasitic capacitances to the LECCS model can expand an available frequency range of the model beyond 1 GHz.

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  • Estimation of Radiated Emissions with Common-mode Antenna Model of Printed Circuit Board : Superposition of Common-mode Excitation Sources

    FUKUMASU Keisuke, WATANABE Tetsushi, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji, WADA Osami

    IEICE technical report   107 ( 107 )   39 - 44   2007.6

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    A common-mode antenna model proposed by the authors is able to predict common-mode radiation from printed circuit boards (PCBs). The model consists of a common-mode excitation source and segmented antenna elements. This repeat discusses the superposition of common-mode sources, the superposition helps to calculate the radiated emissions due to the common-mode excitation in a PCB containing several MSLs. For the evalution, several PCBs with a MSL bent at a right angle were designed and fabricated. Through the experiments and numerical simulation with FDTD method, it was found that the superposition of excitation sources is available to build the common-mode antenna model.

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  • Estimation of Electromagnetic-emission from PCBs with a Connector through the Common-mode Antenna Model

    SADATOSHI Akifumi, SAKAI Youhei, WATANABE Tetsushi, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji, WADA Osami

    IEICE technical report   107 ( 25 )   49 - 54   2007.4

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    The amount of radiated emission from the connector between the motherboard and the daughterboard depends on the number of ground pins. This paper discusses the prediction of the amount of radiated emission from printed circuit boards with a connector using the common-mode antenna model proposed by the authors. the effect of reflection of an unmatched interface such as the connector-board was taken into account by using the measurement result of normal mode voltage in simulation. Common-mode emission is reduced by decreasing imbalance between the conn ector and the board.

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  • B-4-42 Miniaturization and Stopband Expansion of EBG Structure Formed in Power/Ground Plane Pair of PCBs Using High Permeability Materials

    Toyota Yoshitaka, Iokibe Kengo, Koga Ryuji

    Proceedings of the IEICE General Conference   2007 ( 1 )   366 - 366   2007.3

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  • High-resolution measurement of size distributions of Asian dust using a coulter multisizer

    Hiroshi Kobayashi, Kimio Arao, Toshiyuki Murayama, Kengo Iokibe, Ryuji Koga, Masataka Shiobara

    JOURNAL OF ATMOSPHERIC AND OCEANIC TECHNOLOGY   24 ( 2 )   194 - 205   2007.2

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    A Coulter Multisizer, which is based on the electrical sensing zone (ESZ) or the Coulter principle, was used to measure the size distribution of Asian dust. Coulter Multisizer analysis provides high-resolution size measurements of water-insoluble aerosol particles (WIPs) and the number concentration at each size bin. Aerosol filter sampling was conducted at four sites in Japan during spring 2003. The measured volume size distributions fit fairly well with a lognormal distribution. The results show that the WIP size distributions of the same Asian dust air mass varied at each sampling site and the volume mode diameter at the sites reduced from west to east. The derived volume mode diameter ranged from 1.4 to 2.2 mu m and was comparatively smaller than those in previous studies on Asian dust. This can be explained by the possible internal mixing of Asian dust with other components and by the breaking of particles and dispersion of aggregations by ultrasonification during extraction. The analysis method was improved by washing the aerosol particles collected on a filter using a magnetic stirrer, instead of an ultrasonic cleaner. As a result, the WIP size distribution can be measured in the range of 1-10 mu m. The measured mode diameters were 2.6-3.1 and 4.3-5.6 mu m in 2 Asian dust phenomena at Kofu, Japan, in 2004. It is demonstrated that the Coulter Multisizer method can furnish detailed information regarding the spatial and temporal variations in the mineral dust size distribution.

    DOI: 10.1175/JTECH1965.1

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  • Prediction of common-mode radiation from printed circuit boards with interconnections

    Yoshitaka Toyota, Akifumi Sadatoshi, Tetsushi Watanabe, Kengo Iokibe, Ryuji Koga, Osami Wada

    2007 4TH INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY PROCEEDING: EMC 2007   142 - +   2007

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    In order to estimate. the amount of common-mode radiation from a printed circuit board with low calculation cost, a common-mode antenna model has been developed. This paper demonstrates the application of the model to a board interconnection via a connector that is known to be a possible source of common-mode radiation. The radiated emissions estimated by the model agreed with the measurements for practical use.

    DOI: 10.1109/ELMAGC.2007.4413451

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  • Fast calculation of radiated emissions from arbitrarily shaped PCB with IC/LSI

    Masahiro Nishida, Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Osami Wada

    2007 4TH INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY PROCEEDING: EMC 2007   255 - +   2007

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    This paper describes fast calculation of radiated emissions from an arbitrarily shaped printed circuit board (PCB). The radiated emissions from the PCB edge are calculated by taking into account magnetic surface current based on the field equivalent principle. The electric field at the PCB edge is provided by a fast algorithm the authors have proposed for power-bus resonance in the PCB. The calculation of radiated emission was completed within a few minutes and in, good agreement with Finite Difference Time Domain (FDTD) calculation. In addition, an EMI simulation was demonstrated by using a linear macro model of IC/LSI. The calculation results were found to be in good agreement with the measurements.

    DOI: 10.1109/ELMAGC.2007.4413479

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  • Determination of Effective Parasitic Capacitance around IC Package for EMC modeling

    Kengo Iokibe, Atsuhiro Takahashi, Umberto Paoletti, Osami Wada, Yoshitaka Toyota, Ryuji Koga

    6th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2007), Torino   31 - 34   2007

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  • Miniaturization of electromagnetic bandgap (EBG) structures with high-permeability magnetic metal sheet

    Yoshitaka Toyota, Kengo Iokibe, Ryuji Koga, Arif Ege Engin, Tae Hong Kim, Madhavan Swaminathan

    2007 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY: WORKSHOP AND TUTORIAL NOTES, VOLS 1-3   55 - +   2007

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    Electromagnetic bandgap (EBG) structures in a pair of parallel planes are quite effective for suppressing simultaneous switching noise, but they are too large to be applied to compact electronic devices. To miniaturize the EBG structures, we investigated an approach to interpose a high-permeability magnetic metal sheet between the parallel planes. The experimental results show that high permeability of the sheet shifts the stopband towards lower frequencies. This suggests that such sheets contribute to the miniaturization of the EBG structures. In addition, it is demonstrated that the imaginary part of the permeability can expand the stopband.

    DOI: 10.1109/ISEMC.2007.19

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  • Prediction of electromagnetic emissions from PCBs with interconnections through common-mode antenna model

    Yoshitaka Toyota, Akifumi Sadatoshi, Tetsushi Watanabe, Kengo Iokibe, Ryuji Koga, Osami Wada

    EMC ZURICH-MUNICH 2007, SYMPOSIUM DIGEST   107 - +   2007

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    A motherboard-daughterboard structure with a connector is known to have another source of common-mode radiated emissions, and the emissions depend on the connector's signal/ground pin configuration. In order to estimate the amount of radiated emissions from the structure, a common-mode antenna model is described. The model consists of an excitation source and an antenna element, and it calculates radiated emissions from PCBs not only quickly but accurately for practical use. In modeling the board interconnection via a connector, we added two common-mode excitation sources at each end of the connector. The electromagnetic emissions estimated by the model agreed with the measurements within an error of 6 dB around peak emission levels between 300 and 600 MHz.

    DOI: 10.1109/EMCZUR.2007.4388207

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  • Determination of impedances in LECCS-I/O model by 3-port VNA measurement for higher frequency range

    OSAKI Akihiro, IOKIBE Kengo, TOYOTA Yoshitaka, KOGA Ryuji, WADA Osami

    IEICE technical report   106 ( 182 )   17 - 22   2006.7

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    This report discusses impedance determination of a linear equivalent circuit (LEC) in an EMC macro model, LECCS I/O. The 2-port LECCS I/O model the authors had proposed based on 2-port measurement by a vector network analyzer (VNA) was found to be affected by an external circuit connected to the input terminals of CMOS gates. To remove the defect, this report investigated a 3-port LECCS I/O model with 3-port VNA. The 3-port model includes the input circuit of CMOS gates and the three ports of the model mean the power-supply terminal, the output terminal, and the input terminal to the ground terminal. The proposed 3-port model with 3-port VNA was used for power-ground impedance simulation by changing the impedances of external input and output circuits. As a result, the impedance simulation was in good agreement with measurements in higher frequency range compared with the previous 2-port model with 2-port VNA.

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  • Translation of the electromagnetic mode-splitting along a microstrip line with a slit in the ground plane Reviewed

    Ryuji Koga, Tohlu Matsushima, Tetsushi Watanabe, Youhei Sakai, Osami Wada, Kengo Iokibe, Yoshitaka Toyota

    CEEM' 2006: ASIA-PACIFIC CONFERENCE ON ENVIRONMENTAL ELECTROMAGNETICS, VOLS 1 AND 2, PROCEEDINGS   15 - +   2006

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    Is proposed an approach to know magnitudes of parasitic electromagnetic modes excited by the micro-strip line passing over a slit in the return plane. A part of the power having been carried along, the microstrip-line is transferred to the coplanar-line modes along the slot, and the cylindrical. mode in between the pair of re. turn and ground planes. Magnitudes of those modes are expressed by the ratio of powers of the excited electromagnetic mode to the original microstrip line mode, discarding information of phase. Calculation was done with FDTD in the limited domain., around the cross-point in a moderate time of calculation. This approach contributes to the efficient designing of PCB of commercial electronic devices.

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  • EMI antenna model based on common-mode potential distribution for fast prediction of radiated emission Reviewed

    Y. Sakai, T. Watanabe, O. Wada, T. Matsushima, K. Iokibe, Y. Toyota, R. Koga

    IEEE International Symposium on Electromagnetic Compatibility   2   280 - 284   2006

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  • A Scheme to Classify Clouds with the Depolarization Ratio andBackscattering Coeffcient Measured by Lidar

    Iokibe Kengo, Toyota Yoshitaka, Wada Osami, Koga Ryuji

    Memoirs of the Faculty of Engineering, Okayama University   39 ( 1 )   93 - 101   2005.1

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  • 環境をはかる光 レーザーレーダーによる黄砂観測の自動化 LabVIEWによる観測システムの遠隔制御

    本田愁併, 五百旗頭健吾, 古賀隆治

    光アライアンス   14 ( 4 )   2003

  • Aerosol Extinction Coefficient Continuously Measured with Polarized Mie Scattering Lidar

    Kengo Iokibe, Yoshitaka Toyota, Osami Wada, Ryuji Koga

    Memoirs of the Faculty of Engineering, Okayama University   Vol.37, No.2, pp.89-97   2003

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  • Observation of Kosa with Mie Lidar at Okayama in the Spring of 2000

    Ryuji Koga, Kengo Iokibe, He Wei, Osami Wada, Yoshitaka Toyota, Naoki Kagawa

    The Proceedings of Asian Lidar Observation Network Conference 2000   2000

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  • Depolarization Properties of Asian Dust(Kosa)Measured in 1998-2000 at Okayama, Japan

    He Wei, Ryuji Koga, Kengo Iokibe, Osami Wada, Yoshitaka Toyota, Naoki Kagawa

    SPIE   2000

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  • Depolarization properties of Asian dust (KOSA) measured by LIDAR in Okayama in the spring of 1998

    He Wei, Ryuji Koga, Kengo Iokibe, Osami Wada, Yoshitaka Toyota

    Memoirs of the Faculty of Engineering, Okayama University   2000

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Presentations

  • 高密度配線で低クロストークを実現する周期構造差動線路の設計と評価

    竹内智哉, 五百旗頭健吾, 豊田啓孝

    エレクトロニクス実装学会令和3年度第2回システム設計研究会  2021.12.17 

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    Event date: 2021.12.17

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • EMI抑制を目的としたRC/RLスナバ回路の最適設計法

    五百旗頭健吾

    実装フェスタ関西2021  2021.12.14 

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    Event date: 2021.12.13 - 2021.12.14

    Language:Japanese   Presentation type:Poster presentation  

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  • 自動車の電磁的セキュリティ脅威と 車載半導体デバイスのEMC規格

    五百旗頭健吾

    第27回EMC環境フォーラム 自律走行システムに潜む電磁妨害リスクとその対策  2021.11.30 

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    Event date: 2021.11.24 - 2021.11.30

    Language:Japanese   Presentation type:Public lecture, seminar, tutorial, course, or other speech  

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  • 検出感度向上のためのM系列変調TDRにおける設定パラメータの検討-方形波パルスの場合-

    羽村花音, 亀山大樹, 五百旗頭健吾, 豊田啓孝

    2021年度(第72回)電気・情報関連学会中国支部連合大会, R21-15-08  2021.10.23 

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    Event date: 2021.10.23

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  • DC/DCコンバータのノイズ源等価回路モデルによる伝導妨害波予測の適用範囲の検討

    大原未緒, 張書奇, 五百旗頭健吾, 豊田啓孝

    2021年度(第72回)電気・情報関連学会中国支部連合大会, R21-15-06  2021.10.23 

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    Event date: 2021.10.23

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  • 損失を有する共振器型フィルタの平行平板共振抑制時における不要電磁放射の評価

    児玉秀平,金尾奨, 五百旗頭健吾,豊田啓孝

    2021年度(第72回)電気・情報関連学会中国支部連合大会, R21-15-06  2021.10.23 

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    Event date: 2021.10.23

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  • ブラシモータの温度依存性を考慮したノイズ源等価回路モデルのパラメータ同定と伝導妨害波予測

    許振鴻, 菅翔平, 五百旗頭健吾, 豊田啓孝

    2021年度(第72回)電気・情報関連学会中国支部連合大会, R21-15-06  2021.10.23 

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    Event date: 2021.10.23

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  • Abnormal Position Detection in Wire Network by Applying k-Nearest Neighbor Algorithm to Sequence Time Domain Reflectometry

    亀山大樹, 安原朝陽, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会大会講演論文集(CD-ROM)  2021.9.14 

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    Event date: 2021.9.14 - 2021.9.17

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • Parameter Identification of Noise Source Equivalent Circuit Model of Brush Motor Considering Temperature Dependence and Conducted Emission Prediction

    菅翔平, 上本篤志, XU Zhenhong, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会大会講演論文集(CD-ROM)  2021.9 

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    Event date: 2021.9.14 - 2021.9.17

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  • 手戻りのないEMC性能レビュー実現のための配線の平衡度差に着目した電磁妨害波要因分析

    金尾奨, 川島渉, 五百旗頭健吾, 高津宏明, 野村毅, 辻本隆浩, 豊田啓孝

    エレクトロニクス実装学会令和3年度第1回システム設計研究会  2021.6.15 

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    Event date: 2021.6.15

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  • Time-Frequency Domain Correlation Power Analysis for Side-Channel Attack Resistance Evaluation of Practical Modules

    日室雅貴, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告(Web)  2021.4.16 

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    Event date: 2021.4.16

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  • Evaluation of Unintentional Radiated Emissions from Unshielded Twist Pair Cable

    五十嵐俊, 宮脇大輔, 山岸傑, 桑山一郎, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会大会講演論文集(CD-ROM)  2021 

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  • Parameter Identification of Noise-source Equivalent-circuit Model Focusing on Turn-on/Turn-off Timing of DC/DC Converter and Evaluation of Conducted Disturbance Measurement

    上松大志, ZHANG Shuqi, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告(Web)  2020.12.11 

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  • Examination of Requirements for Power Side-Channel Attack Resistance Evaluation Boards of Cryptographic Integrated Circuits-Contribution of PDN Transfer Impedance to Leakage Strength-

    菅智信, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告(Web)  2020.10.26 

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    Event date: 2020.10.26

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  • Preliminary Examination of Impedance Discontinuity Detection on Wire Network by Sequence Time Domain Reflectometry

    亀山大樹, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告(Web)  2020.5 

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  • Suppression of Mode Conversion Using Asymmetric Differential-Transmission Lines for Dense Parallel Traces

    竹内智哉, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会技術研究報告(Web)  2020.5 

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  • A Study for Predicting Power Side-Channel Attack Countermeasure Effect by PDN Decoupling Based on Transfer Impedance

    五百旗頭健吾, 矢野佑典, 豊田啓孝

    電子情報通信学会技術研究報告  2020.1.24 

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    Event date: 2020.1.24

    Language:Japanese  

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  • Simple Model of Connector to Estimate Current Division Factor for Common-mode Radiation Simulation

    豊田啓孝, 金尾奨, 佐田野勝水, 五百旗頭健吾

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM)  2020 

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    Event date: 2020

    Language:Japanese  

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  • AES暗号回路へのクロックグリッチを道いた故障利用攻撃に対する安全性評価手法の検討

    原成希, 五百旗頭健吾, 豊田啓孝

    ハードウェアセキュリティ研究会, HWS2019, 東京都台東区  2019.12.6 

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    Event date: 2019.12.6

    Language:Japanese   Presentation type:Poster presentation  

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  • Preliminary Study on Modeling of Noise Current and Electromagnetic Radiation for EMI Evaluation of Movable Device with Brush Motors

    2019.7.19 

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    Event date: 2019.7.19

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • A study on application of electromagnetic interference source estimation method to power electronics circuit by noise source amplitude modulation and correlation analysis

    川島渉, 五百旗頭健吾, 豊田啓孝

    2019.7.18 

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    Event date: 2019.7.18

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • PSD手法における設計パラメータの正規化によるロバスト性の向上―ビアレス・オープンスタブ型EBG構造の場合―

    金尾奨, 五百旗頭健吾, 豊田啓孝

    電子情報通信学会環境電磁工学研究会, EMCJ2019-26, pp. 47-52, 東京都港区  2019.7.18 

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    Event date: 2019.7.18

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • Intensity and Phase Estimation of Far-Field Emission of Individual ICs by Using Noise Source Amplitude Modulation Technique

    2019.5.10 

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    Event date: 2019.5.10

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • PSD手法を用いたビアレス・オープンスタブ型EBG構造の設計

    金尾奨, 奥山友貴, 五百旗頭健吾, 豊田啓孝

    2019年電子情報通信学会総合大会, B-4-23, p. 243, 東京都新宿区  2019.3 

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    Event date: 2019.3.19 - 2019.3.22

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • 周期構造を有する隣接差動線路間のディファレンシャルモードクロストークの低減メカニズム

    王晨宇, 竹田大晃, 五百旗頭健吾, 豊田啓孝

    2019年電子情報通信学会総合大会, B-4-14, p. 234, 東京都新宿区  2019.3 

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    Event date: 2019.3.19 - 2019.3.22

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • 差分電力解析におけるサイドチャネル波形のSNRと相関係数の関係式パラメータの実験による同定

    手嶋俊彰, 五百旗頭健吾, 豊田啓孝, 矢野佑典

    暗号と情報セキュリティシンポジウム (SCIS2019), 2D3-4, 滋賀県大津市  2019.1 

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    Event date: 2019.1.22 - 2019.1.25

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • Prediction Accuracy in Conduction Disturbance Voltage of DC/DC Buck Converter Using Noise-source Equivalent-circuit Model

    2019.4.11 

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    Event date: 2019

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • Improvement of Prediction Accuracy by Improving Parameters Extraction in 2-port Noise-source Equivalent Circuit Model of DC/DC Converter

    2019.1.18 

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    Event date: 2019

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • Investigation of Reaction of Error Control of CAN Protocol in Case of Electromagnetic Disturbance Injection

    Ryunosuke Isshiki, Kengo Iokibe, Takuya Kusaka, Tetsushi Kamegawa, Yasuyuki Nogami

    2018.11.22 

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    Event date: 2018.11.22 - 2018.11.23

    Language:English   Presentation type:Oral presentation (general)  

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  • ノイズ源振幅変調と相関解析に基づく放射源デバイス毎の電磁妨害波放射強度推定

    吉野慎平, 石田千晶, 五百旗頭健吾, 豊田啓孝

    第32回エレクトロニクス実装学会春季講演大会, 8A3-3, 千葉県野田市  2018.3 

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    Event date: 2018.3.6 - 2018.3.8

    Language:Japanese   Presentation type:Oral presentation (general)  

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  • Safety Estimates of Cryptographic Modules against On-Board Side-Channel Attacks by Use of EMC Macro-Model

    IOKIBE Kengo, AMANO Tetsuo, OKAMOTO Kaoru, TOYOTA Yoshitaka, WATANABE Tetsushi

    IEICE technical report. Electromagnetic compatibility  2012.12.14  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.12.14

    Language:Japanese  

    In this study, EMC-macro modeling was examined to develop a method to evaluate cryptographic systems before fabrication. A EMC-macro model of a cryptographic FPGA in which an AES algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of FPGA. The model was implemented into a commercial analog circuit simulator and side-channel traces due to the SSN current was estimated under three different PDN configurations under which a decoupling circuit was inserted into the PDN as a countermeasure. Estimated side-channel traces were analyzed statistically by the correlation power analysis (CPA) method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication.

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  • B-4-50 Suppression of Power-bus Resonance by Quarter-wavelength Resonator with Loss

    Mahmood Farhan Zaheed, Toyota Yoshitaka, Iokibe Kengo

    Proceedings of the Society Conference of IEICE  2012.8.28  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.8.28

    Language:Japanese  

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  • Linear Equivalent Circuit Modeling of Power Converter Circuit for Conducted Disturbance Estimation : Determination of Model Parameters by Use of Dual Port LISN

    INOUE Shuhei, IOKIBE Kengo, TOYOTA Yoshitaka, WATANABE Tetsushi

    IEICE technical report. Electromagnetic compatibility  2012.6.15  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.6.15

    Language:Japanese  

    A reduction design of conducted disturbance from power converter circuits is becoming more important as electronic devices are requiring much more power efficiency. Conducted disturbance must meet domestic and international regulations. In this paper, a linear equivalent circuit model on the basis of a EMC macro-model of IC/LSI, LECCS model, is investigated to predict the conducted disturbance of power converter circuits. The dual-port LISN (DP-LISN) constructed to provide the model is also reported. In the study, an commercial table-top induction heater is used as the equipment under test. Conducted disturbance voltages were measured with 10 different load pairs of the DP-LISN. Model parameters were then determined by the least square method with the conducted disturbance voltages measured. We simulated conducted disturbance voltages for evaluation by use of the linear equivalent circuit model as an evaluation of the model. As comparing simulated and measured disturbance voltages, the spectrum of the conducted disturbance voltages agreed with each other in their envelopes.

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  • B-4-29 Identification of Equivalent Current Source of Cryptographic Circuit by Means of LECCS Modeling Method

    Okamoto Kaoru, Amano Tetsuo, Iokibe Kengo, Toyota Yoshitaka

    Proceedings of the IEICE General Conference  2012.3.6  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.3.6

    Language:Japanese  

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  • B-4-10 Linear Equivalent Circuit Modeling of Power Converter Circuit for COnducted Disturbance Reduction Design

    Ishiyama Naotaka, Inoue Shuhei, Iokibe Kengo, Toyota Yoshitaka, Watanabe Tetsushi

    Proceedings of the IEICE General Conference  2012.3.6  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.3.6

    Language:Japanese  

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  • B-4-9 Construction of Dual-Port LISN for Linear Equivalent Circuit Modeling of Power Convert Circuit

    Inoue Shuhei, Iokibe Kengo, Toyota Yoshitaka, Watanabe Tetsushi

    Proceedings of the IEICE General Conference  2012.3.6  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.3.6

    Language:Japanese  

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  • CS-6-6 Circuit Simulation with Modal Equivalent Circuit for Noise Suppression

    Toyota Yoshitaka, Iokibe Kengo, Koga Liuji R.

    Proceedings of the IEICE General Conference  2012.3.6  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.3.6

    Language:Japanese  

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  • Measurement of IC Package Inductance with Transmission Line Embedded in Package

    IOKIBE Kengo, TANIMICHI Ayumi, TOYOTA Yoshitaka

    2012.1.26  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2012.1.26

    Language:Japanese  

    It is of importance for designers to possess accurate inductances of IC packages in power integrity(PI) and electromagnetic compatibility designs. The authors had proposed a simple method to measure inductance of IC package that is mounted on a practical printed circuit board. They investigated the method in terms of accuracy here. In the proposed method, a transmission line is embedded in an IC package interested, and two port S parameters of a network composed of a targeted package structure, the transmission line, and the corresponding symmetric package structure is measured. The package inductance is calculated from the measured S parameters and properties of the transmission line obtained beforehand. The proposed method was applied to four test IC packages, and their inductances were measured. The measurement was demonstrated on a commercial electromagnetic simulator, HFSS. The package inductances were also obtained by analyzing the test package directly for comparison to the results of the proposed method. They agreed with the maximum error of 0.9 nH. To understand a cause of the error, the authors investigated effects of dummy-objects that were used to place measuring ports in the HFSS calculation. The dummy-object caused errors less than 0.06 nH, which means it seldom cause significant errors.

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  • Mode-equivalent Modeling and Identification of System with Cable Interconnection between Transmitter and Receiver Pairs (Part 3)

    TOYOTA Yoshitaka, SEJIMA Kota, IOKIBE Kengo, KOGA Liuji R., WATANABE Tetsushi

    IEICE technical report. Electromagnetic compatibility  2011.11.25  The Institute of Electronics, Information and Communication Engineers

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    Event date: 2011.11.25

    Language:Japanese  

    We focus on the expression by using modal equivalent-circuit model. The goal of this study is to clarify the mechanism of the phenomena caused by mode conversion and then find effective measures. The simple model is based on mode-decomposition technique and places mode-conversion sources at the interface where the current division factors of the transmission lines are different. In this study, a simple cable interconnection system with a node and common-mode excitation by a current probe were investigated to evaluate the validity of this study. As a result, both cases agreed well between measurement and circuit simulation with the modal-equivalent circuit model.

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  • PI/SI解析精度向上を目的としたIBIS及びLECCS-core組合せICマクロモデル

    岡典正, 五百旗頭健吾, 豊田啓孝, 古賀隆治

    電子情報通信学会論文誌C  2010 

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    Event date: 2010

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  • CP-2-3 EMC設計を支援する高速EMIシミュレータの開発とその応用(CP-2.マイクロ波教育におけるシミュレータの可能性,パネルセッション,ソサイエティ企画)

    豊田 啓孝, 古賀 隆治, 五百旗頭 健吾, 和田 修己

    電子情報通信学会総合大会講演論文集  2009.3.4 

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    Event date: 2009.3.4

    Language:Japanese  

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  • Fast Calculation of Power-Bus Resonances in Printed Circuit Boards by Segmentation Method with Single Slit Segments

    HAMAGAMI Takahiro, TOYOTA Yoshitaka, IOKIBE Kengo, KOGA Ryuji

    ITE Technical Report  2009  The Institute of Image Information and Television Engineers

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    Event date: 2009

    Language:Japanese  

    A fast algorithm based on a full cavity-mode resonator model of rectangular power-bus structures is able to quickly obtain the power-bus resonance characteristics in multilayer printed circuit boards (PCBs). Furthermore, the approach can provide the resonance characteristics in PCBs with a slit using a slit model expressing electromagnetic coupling across the gap of the slit. However, the model does not express the slit width, which can cause the degradation in accuracy of resonance analysis. In this paper, a slit segment was studied to express the gap of the single slit coupling and analyze the power-bus resonances. The slit segment was given from an equivalent circuit based on a coupled microstrip line. As a result, it was found that the slit segment can provide the power-bus resonance characteristics as accurate as or more accurate than the conventional slit model.

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  • 黄砂の観測を目的としたインターネットシステム上のレーザレーダ運用

    古賀隆治, 五百旗頭健吾, 伊藤嘉則, 白川紘之, 豊田啓孝, 和田修己

    計測自動制御学会中国支部学術講演会論文集  2003 

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    Event date: 2003

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  • 岡山・福山における偏光ライダーによる対流圏同時観測

    五百旗頭健吾, 香川直己, 豊田啓孝, 和田修己, 古賀隆治

    応用物理学会学術講演会講演予稿集  2002 

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    Event date: 2002

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  • Effect of a rectangular field-stop for the laser rader receiving telescope.

    後藤孝規, 五百旗頭健吾, 豊田啓孝, 和田修己, 古賀隆治

    電子情報通信学会技術研究報告  2002 

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    Event date: 2002

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  • AES回路から漏洩するサイドチャネル波形のSNR測定法~バイト毎のラウンド鍵解読への適用~

    暗号と情報セキュリティシンポジウム (SCIS2018), 1D2-2  2018 

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  • メッシュグラウンドを有するプリント配線基板における回転角度に対する差動スキューの評価

    電子情報通信学会環境電磁工学研究会, EMCJ2017-109, pp. 25-30  2018 

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  • 2重電源層プレーナ型EBG 構造の小型化 -単位セルにおけるインダクタンス増加のための細線導入-

    電子情報通信学会環境電磁工学研究会, EMCJ2018-95, pp. 43-48  2018 

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  • ノイズ源振幅変調による電磁妨害波ノイズ源の対策優先度決定及び対策効果の評価

    電子情報通信学会環境電磁工学研究会, EMCJ2018-96, pp. 49-54  2018 

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  • サイドチャネル攻撃耐性評価コスト削減を目的とした暗号機器へのLC共振器付加

    電子情報通信学会環境電磁工学研究会, EMCJ2018-101, pp. 77-81  2018 

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  • AES暗号回路の規模増加を抑制するサイドチャネル攻撃対策の検討~HDパワーモデルによる漏洩への対策~

    暗号と情報セキュリティシンポジウム (SCIS2018), 1D2-1  2018 

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  • クロックグリッチ掃引によるAES回路の故障利用攻撃耐性判定法

    2017年 暗号と情報セキュリティシンポジウム (SCIS 2017), 2A3-3  2017 

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  • 損失を有する共振器型フィルタの設置位置による電源層間ノイズ抑制効果の評価と考察

    平成29年度(第68回)電気・情報関連学会中国支部連合大会, R17-15-06  2017 

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  • ノイズ源振幅変調による電磁妨害波源デバイス特定法の精度改善

    電子情報通信学会環境電磁工学研究会, EMCJ2017-70, pp.35-40  2017 

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  • IoT時代における暗号機器への物理的な攻撃に対する安全設計技術

    岡山大学 知恵の見本市2017  2017 

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  • 差動線路への周期構造導入によるクロストーク抑制効果の実測による評価

    JIEP 第三回 超高速・高周波エレクトロニクス実装研究会, Vol.17, No.3, pp. 13-16  2017 

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  • プリント回路基板のガラスクロスに起因する差動スキューを低減する最適配線角度

    JIEP 第三回 超高速・高周波エレクトロニクス実装研究会, Vol.17, No.3, pp. 17-20  2017 

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  • 低コストな安全設計法実現のためのサイドチャネル波形の信号対雑音比測定法

    2017年 暗号と情報セキュリティシンポジウム (SCIS 2017), 3C3-1  2017 

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  • 振幅変調したスイッチング電流とEMI測定の相関係数に基づくノイズ源推定

    第31回エレクトロニクス実装学会春季講演大会, 8A4-5, pp. 311-314  2017 

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  • DC-DCコンバータのノイズ源等価回路の提案とパラメータ同定

    電子情報通信学会環境電磁工学研究会, EMCJ2017-6, pp. 29-34  2017 

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  • 周期構造を有する差動伝送線路におけるクロストーク抑制

    電子情報通信学会環境電磁工学研究会, EMCJ2017-4, pp. 23-28  2017 

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  • A Method of Fault Detection in Encryption Device Based on Leaked EM Information from Adder Circuit

    EMC Joint Workshop 2017, EMCJ2017-10, pp. 7-8  2017 

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  • Evaluation of Secondary Common-mode current Using Modal Equivalent Circuit in Four-conductor Transmission-line System

    EMC Joint Workshop 2017, EMCJ2017-14, pp. 15-16  2017 

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  • 耐性評価コスト削減を目的とするハミング距離確率分布が母集団と等価な選択平文の検討

    電子情報通信学会ハードウェアセキュリティ研究会  2017 

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  • RLスナバを用いた同期整流降圧コンバータにおけるLC共振抑制

    電子情報通信学会2017年ソサイエティ大会, B-4-36, p.239  2017 

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  • ノイズ源変調に基づくノイズ源推定法の精度向上

    電子情報通信学会2017年ソサイエティ大会, B-4-38, p.241  2017 

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  • IoT時代における機器認証を安全に実施するセキュリティ計算チップの開発

    MEMSセンシング&ネットワークシステム展2017  2017 

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  • ディジタルIC の電源供給回路網に付加するオンボードRLスナバの最適抵抗値決定式の導出

    第67回電気・情報関連学会中国支部連合大会, R16-09-03  2016 

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  • 内部電流源による暗号回路のサイドチャンネル情報漏洩部特定の試み ~AES回路を実装したFPGAに対する検討~

    電子情報通信学会環境電磁工学研究会, EMCJ2016-74, pp. 79-84  2016 

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  • Optimization Method of On-board RL Snubber Parameters in Common Power Distribution Networks

    2016 

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  • A Study for EMI Radiation Mechanism from Printed Board Based on Far and Near Fields Measurements

    2016 

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  • AESに対する故障利用攻撃における同期信号の変動による攻撃可能性の変化

    2016年 暗号と情報セキュリティシンポジウム(SCIS2016), 2F3-3  2016 

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  • 配線へのコモンモード電流注入における電流プローブのモデル化とモード等価回路シミュレーション

    電子情報通信学会環境電磁工学研究会, EMCJ2015-115, pp.65-70  2016 

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  • 筋電義手からのノイズ放射とその評価法の検討

    ギガビット研究会第6回ウェアラブル分科会  2016 

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  • 暗号機器におけるサイドチャネル波形のSN比と攻撃コストに関する一検討

    電子情報通信学会総合大会, B-4-61, p. 381  2016 

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  • 任意のPDN におけるオンボードRLスナバの最適値決定法

    電子情報通信学会総合大会, B-4-41, p. 361  2016 

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  • ブランチに並列なキャパシタンスに着目したプレーナ型EBG構造の小型化

    第30回エレクトロニクス実装学会春季講演大会, 24B2-4, pp. 341-344  2016 

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  • 電源層のノイズ低減のためのビアレス・オープンスタブ型EBG構造の阻止域拡大の検討

    第30回エレクトロニクス実装学会春季講演大会, 24B2-5, pp. 345-348  2016 

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  • プリント基板からのEMI発生機構に関する遠方界および近傍磁界測定に基づく考察

    第30回エレクトロニクス実装学会春季講演大会, 24B3-5, pp. 361-364  2016 

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  • くし形電極を用いたプレーナ型EBG構造の小型化

    電子情報通信学会環境電磁工学研究会, EMCJ2016-3, pp.11-16  2016 

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  • Variation of Fault Attack Possibility with Jitter in Synchronization Signal Leaked Through Side-Channel of AES Circuit

    2016 Symposium on Cryptography and Information Security  2016 

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  • Modeling of Current Probe and Simulation with Modal Equivalent Circuit in Common-mode Current Injection to Cable

    2016 

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  • A Study on Signal-to-Noise Ratio of Side-Channel Traces for Evaluation of Attacking Cost of Cryptographic Modules

    2016 

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  • 電力変換回路の伝導妨害波予測を目的とした線形等価回路モデルの検討―モデル同定におけるトリガタイミングの影響―

    電子情報通信学会環境電磁工学研究会, EMCJ2016-16, pp. 41-45  2016 

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  • Investigation of Relationship between Signal-to-Noise Ratio of EM Information Leakage and Side-Channel Attacking Cost

    EMC Joint Workshop 2016, EMCJ2016-25, pp. 23-24  2016 

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  • Validation of Optimization Method of On-board RL snubber According to Q Factor

    EMC Joint Workshop 2016, EMCJ2016-27, pp. 29-30  2016 

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  • Estimation Method of EM Information Leakage from Cryptographic-Device-Embedded Printed Circuit Boards

    2016 IEEE International Symposium on Electromagnetic Compatibility, MO-AM-6-3  2016 

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  • EMC設計技術実践講座基板の深掘り ー放射ノイズの発生メカニズムと低減法ー

    一般社団法人エレクトロニクス実装学会 2016サマーセミナー  2016 

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  • 電源層の2層化によるプレーナ型EBG構造の小型化

    電子情報通信学会環境電磁工学研究会, EMCJ2016-57, pp.41-45  2016 

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    電子情報通信学会2016年ソサイエティ大会, B-4-50, p. 258  2016 

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  • 損失を有する共振器型フィルタ実用化のための複雑形状の電源/GND層間の共振抑制評価

    電子情報通信学会2016年ソサイエティ大会, B-4-56, p. 264  2016 

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  • 内部電流波形に基づくAES回路のサイドチャネル情報漏洩特性の考察

    2015年 暗号と情報セキュリティシンポジウム(SCIS2015), 2F3-1  2015 

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  • 差分フォルト解析においてクリティカルなグリッチ注入タイミングの測定

    2015年 暗号と情報セキュリティシンポジウム(SCIS2015), 3A3-3  2015 

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  • 筋電義手からの放射量評価法の検討

    ギガビット研究会第5回ウェアラブル分科会  2015 

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  • フェライト膜の電気的特性を考慮した損失を有する共振器型フィルタの設計

    電子情報通信学会環境電磁工学研究会, EMCJ2015-86, pp.31-36  2015 

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  • 差動線路の屈曲部における非対称テーパ導入による伝送特性改善効果の評価

    エレクトロニクス実装学会平成27年度第3回超高速・高周波エレクトロニクス実装研究会, Vol. 15, No. 3, pp.1-6  2015 

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  • 損失を有する共振器型フィルタの設計法の提案と検証

    第17回IEEE広島支部学生シンポジウム, A-26  2015 

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  • 単純電力解析対策を目的としたRSA暗号回路のサイドチャネル波形分析

    第17回IEEE広島支部学生シンポジウム, A-71  2015 

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  • 平衡度の異なる線路接続位置へのキャパシタ実装によるコモンモードからノーマルモードへのモード変換抑制

    第17回IEEE広島支部学生シンポジウム, B-26  2015 

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  • サイドチャネル情報漏洩に寄与が大きいAES回路部の内部電流源に基づく検討

    第38回情報理論とその応用シンポジウム(SITA2015)予稿集, pp. 720-724  2015 

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  • IoT時代における暗号機器への物理的な攻撃に対する安全設計技術

    岡山大学 知恵の見本市2015  2015 

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  • IC電源供給回路共振抑制を目的としたオンボードRLスナバの最適パラメータ検討

    2015年電子情報通信学会ソサイエティ大会, B-4-47, p. 260  2015 

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  • 電源-グラウンド層間のノイズ低減のためのビアレス・オープンスタブ型EBG構造の提案

    電子情報通信学会環境電磁工学研究会, EMCJ2014-95, pp.57-62  2015 

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  • 差動線路の信号品質に与えるコモンモード特性インピーダンスの影響評価

    電子情報通信学会総合大会, B-4-63  2015 

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  • ミアンダ配線を有するフェライト膜付プレーナ型EBG構造を搭載した実機によるノイズ抑制評価

    第29回エレクトロニクス実装学会春季講演大会, 17C3-4, pp. 319-322  2015 

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  • 筋電義手からの放射量評価法の検討

    ギガビット研究会筋電義手分科会第4回研究会  2015 

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  • AES暗号回路における致命的なクロックグリッチ注入タイミングの測定

    第6回ホットチャネルワークショップ  2015 

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  • 電力変換回路の伝導妨害波予測を目的とした線形等価回路モデルの検討―スイッチング周波数変動影響の考察―

    電子情報通信学会環境電磁工学研究会, EMCJ2015-5, pp.19-24  2015 

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  • 電源系配線におけるモード変換位置へのコンデンサ実装によるコモンモードノイズ発生量の低減

    電子情報通信学会環境電磁工学研究会, EMCJ2015-9, pp.7-12  2015 

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  • 高密度実装のための差動線路屈曲部における非対称テーパ付密結合屈曲構造の収納性向上

    電子情報通信学会環境電磁工学研究会, EMCJ2015-39, pp.49-54  2015 

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  • 1バイト誤りを起こす時間幅を統計的に表わすサンプル数の検討

    第7回ホットチャネルワークショップ  2015 

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  • 電子機器へのサイドチャネル攻撃におけるセキュリティ技術

    第27回電気・電子機器のEMCワークショップ(湯沢WS)  2015 

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  • 電子機器への妨害波注入における電源ケーブルのコモンモード電圧とICコア電圧に発生するノイズとの関係

    平成26年度(第65回)電気・情報関連学会中国支部連合大会, p.115  2014 

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  • オンボードRLスナバの実装位置によるPDN共振抑制効果の検証

    平成26年度(第65回)電気・情報関連学会中国支部連合大会, p.351  2014 

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  • 洗練されたスケーラビリティと高度な安全性を有するペアリング暗号

    国立六大学連携コンソーシアム新技術説明会  2014 

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  • モデル定数の合理性向上を目的としたIH調理器の伝導妨害波予測モデル同定実験の改良

    第16回IEEE広島支部学生シンポジウム, B-14  2014 

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  • 内部等価電流源に基づく相関電力解析におけるAES暗号回路の情報漏洩源分析

    第16回IEEE広島支部学生シンポジウム, A-14  2014 

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  • ディジタルICのPDN共振を抑制するオンボードRLスナバの実装位置自由度の検討

    電子情報通信学会環境電磁工学研究会, EMCJ2014-81, pp.69-74  2014 

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  • 電源ケーブルへのバーストパルス注入による故障発生の検討

    第5回ホットチャネルワークショップ  2014 

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  • 暗号機器のサイドチャネル攻撃に対する安全設計に関する研究開発

    ICTイノベーションフォーラム2014  2014 

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  • グラウンド面からの高さを変えた場合の差動線路の屈曲部におけるモード変換量のモード等価回路による評価

    平成26年度(第65回)電気・情報関連学会中国支部連合大会, p.351  2014 

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  • 電源線から侵入した外乱に起因するクロックグリッチによるFPGA誤動作事例

    第28回エレクトロニクス実装学会春季講演大会  2014 

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  • 回路基板の多線条配線における諸問題の評価と展開

    ギガビット研究会 筋電義手分科会第3回研究会  2014 

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  • 回路基板の多線条配線における諸問題の評価と展開

    ギガビット研究会 筋電義手分科会第3回研究会  2014 

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  • ノーマル・コモン両モード間のモード変換を考慮したコモンモードアンテナモデルによる不要電磁放射シミュレーション

    電子情報通信学会エレクトロニクスシミュレーション研究会, EST2014-6, pp.29-34  2014 

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  • 回路シミュレーションに基づくサイドチャネル攻撃に対する安全性予測法

    2014エレクトロニクス実装学会最先端実装技術シンポジウム  2014 

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  • 内部等価電流源に基づくAES 暗号回路の情報漏洩源としての挙動分析

    電子情報通信学会環境電磁工学研究会, EMCJ2014-26, pp.13-18  2014 

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  • 電源ケーブルからICへ侵入する外来妨害波の注入方法による比較

    電子情報通信学会環境電磁工学研究会, EMCJ2014-22, pp.31-36  2014 

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  • フェライト薄膜とオープンスタブからなる損失を有する共振器型フィルタの作製と評価

    電子情報通信学会環境電磁工学研究会, EMCJ2014-27, pp.7-12  2014 

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  • 差動線路屈曲部における非対称テーパ付密結合屈曲構造の作製とモード変換抑制の評価

    電子情報通信学会2014年ソサイエティ大会, B-4-42, p.269  2014 

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  • フェライト膜付プレーナEBG構造の実用化のための検討

    第28回エレクトロニクス実装学会春季講演大会, 5A-12, pp.43-46  2014 

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  • 電源線から侵入した外乱に起因するクロックグリッチによるFPGA誤動作事例

    第28回エレクトロニクス実装学会春季講演大会, 5A-19, pp.63-66  2014 

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  • 故障利用攻撃を目的とした電源線からAES回路へのパルス注入実験

    第31回 暗号と情報セキュリティシンポジウム(SCIS2014)  2014 

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  • AES回路の等価電流源に基づくハミング距離漏えいモデルの検討

    第31回 暗号と情報セキュリティシンポジウム(SCIS2014)  2014 

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  • AES回路の等価電流源に基づくハミング距離漏えいモデルの検討

    第31回 暗号と情報セキュリティシンポジウム(SCIS2014), 3A2-2  2014 

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  • 差動線路の屈曲部におけるモード変換抑制のための非対称テーパ付密結合屈曲構造の提案

    電子情報通信学会環境電磁工学研究会  2014 

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  • フェライト膜付プレーナEBG構造のミアンダ配線を用いた小型化

    電子情報通信学会環境電磁工学研究会  2014 

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  • 差動線路の屈曲部におけるモード変換抑制のための非対称テーパ付密結合屈曲構造の提案

    電子情報通信学会環境電磁工学研究会, EMCJ2013-116, pp.27-32  2014 

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  • フェライト膜付プレーナEBG構造のミアンダ配線を用いた小型化

    エレクトロニクス実装学会 超高速・高周波エレクトロニクス実装研究会 平成25年度第4回公開研究会, pp. 1-4  2014 

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  • 暗号ICの安全評価用標準プリント基板の開発

    第18回岡山リサーチパーク研究・展示発表会  2014 

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  • 暗号ICの安全評価用標準プリント基板の開発

    第18回岡山リサーチパーク研究・展示発表会  2014 

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  • フェライト膜付プレーナEBG構造の実用化のための検討

    第28回エレクトロニクス実装学会春季講演大会  2014 

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  • 故障利用攻撃を目的とした電源線からAES回路へのパルス注入実験

    第31回 暗号と情報セキュリティシンポジウム(SCIS2014), 3A1-3  2014 

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  • 高速差動線路の屈曲部におけるモード変換に平衡度が及ぼす影響の評価

    電気・情報関連学会中国支部第64回連合大会, 11-13  2013 

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  • 高度な認証を実現する並列代数計算アルゴリズムのLSI実装およびサイドチャネル攻撃に対する安全設計手法の研究開発―製品レベルの安全設計手法―

    コンピュータセキュリティシンポジウム2013 (CSS2013)  2013 

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  • EMC技術とサイドチャネル攻撃シミュレーション

    IEEE EMC Society Sendai Chapter Colloquium  2013 

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  • FPGAのオンボード電源電圧予測へのLECCSモデルの適用

    電子情報通信学会環境電磁工学研究会, EMCJ2013-88  2013 

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  • 偏光ミー散乱ライダーを用いた大気中のエアロゾルと雲の観測

    2013年度日本気象学会関西支部 第1回例会(中国地区)  2013 

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    電子機器の電磁波イミュニティ講習会  2013 

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    ギガビット研究会 第5回シンポジウム  2013 

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  • AESへの相関電力解析に対するSubBytes?高速化効果の評価

    第15回 IEEE広島支部学生シンポジウム, A-70  2013 

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  • 2 本の伝送線路のS パラメータ測定に基づく同軸コネクタ部のF行列同定

    第15回 IEEE広島支部学生シンポジウム, A-70  2013 

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  • 差動線路の屈曲部のモード等価回路表現

    電子情報通信学会環境電磁工学研究会, EMCJ2013-98  2013 

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  • 暗号回路で発生するスイッチングノイズ電流を同定する等価電流源の改良

    2013 IEEE EMC Symposium (Denver) 報告会  2013 

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  • コモンモードおよびノーマルモードのアンテナモデルを用いた全EMI放射の定量予測

    電子情報通信学会環境電磁工学研究会, EMCJ2013-2  2013 

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  • 暗号ICで発生するサイドチャネル解析におけるノイズの等価電流源モデルに基づく一検討 ~SASEBO-Gを用いた検討~

    電子情報通信学会環境電磁工学研究会, EMCJ2013-5  2013 

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  • オープンスタブと磁性膜から構成される損失を有する共振器型フィルタを用いた平行平板共振抑制

    電子情報通信学会環境電磁工学研究会, EMCJ2013-14  2013 

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  • 回路基板の多線条配線における諸問題の評価と展開

    ギガビット研究会 第4回シンポジウム  2013 

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    岡山情報通信技術研究会 第11回研究会  2013 

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    電子情報通信学会環境電磁工学研究会, EMCJ2013-34  2013 

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    2013 IEEE International Symposium on Electromagnetic Compatibility  2013 

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    一般社団法人エレクトロニクス実装学会 2013サマーセミナー  2013 

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    イノベーション・ジャパン2013 ~大学見本市&ビジネスマッチング~  2013 

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    電子情報通信学会2013年ソサイエティ大会, BI-1-5  2013 

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    エレクトロニクス実装学会 2013ワークショップ  2013 

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    電気・情報関連学会中国支部第64回連合大会, 11-7  2013 

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  • プリント基板レベルでの相関電力解析に対する安全性予測

    2013年暗号と情報セキュリティシンポジウム (SCIS2013)  2013 

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  • 平行平板共振抑制のためのEBG構造とフェライト膜を組み合わせた電源層の評価

    第27回エレクトロニクス実装学会春季講演大会  2013 

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  • 損失を有する1/4波長共振器による電源/グラウンド層間共振抑制

    第27回エレクトロニクス実装学会春季講演大会  2013 

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  • EMCマクロモデルの暗号機器へのサイドチャネル攻撃に対する安全性予測への適用

    第27回エレクトロニクス実装学会春季講演大会  2013 

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  • 線路の平衡度および電圧反射係数とモード変換の関係の一考察

    2013年電子情報通信学会総合大会  2013 

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  • サイドチャネル攻撃予測のための暗号FPGAの等価電流源同定

    2013年電子情報通信学会総合大会  2013 

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  • ガードトレースへの周期構造導入によるコモンモード放射抑制と信号品質維持の両立

    電子情報通信学会環境電磁工学研究会, EMCJ2013-1  2013 

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  • ICのEMCおよびPI向上を目的としたRLダンパ回路の提案

    電子情報通信学会環境電磁工学研究会, EMCJ2012-8, pp.43-48  2012 

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  • 電力変換回路の伝導妨害波予測を目的とした線形等価回路モデルの検討~デュアルポートLISNを用いたモデル構築~

    電子情報通信学会環境電磁工学研究会, EMCJ2012-24, pp.17-22  2012 

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  • ノイズ対策のためのモード等価回路を用いた回路シミュレーション

    2012年電子情報通信学会総合大会, CS-6-6, p.S25-S26  2012 

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  • 暗号処理基板におけるサイドチャネル攻撃の安全性予測

    産業総合研究所本格研究ワークショップ  2012 

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  • EMCマクロモデルを用いた暗号機器へのサイドチャネル攻撃に対する安全性の予測

    電子情報通信学会環境電磁工学研究会, EMCJ2012-99, pp.87-94  2012 

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  • PCB上の非対称配線に起因するEMI/SI問題の検討

    ギガビット研究会 第3回シンポジウム  2012 

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  • STPケーブルの接地法とモード変換量の関係について平衡度を考慮した評価

    電子情報通信学会環境電磁工学研究会, EMCJ2012-32, pp. 1-6  2012 

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  • 損失をもつ1/4波長共振器を用いた平行平板共振抑制

    電子情報通信学会ソサイエティ大会,B-4-50, p.346  2012 

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  • コモンモード放射抑制のためのガードトレースに周期構造を導入した効果の実測による評価

    平成24年度電気・情報関連学会中国支部第63回連合大会, 11-5, p.142  2012 

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  • 線路間の平衡度不整合に起因するモード変換の回路表現に対する電磁界シミュレーションを用いた初期検討

    電子情報通信学会エレクトロニクスシミュレーション研究会, EST2012-55, pp.43-48  2012 

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  • 拡大体上乗算アルゴリズムCVMAのFPGA実装とハードウェア設計法

    コンピュータセキュリティシンポジウム2012 (CSS2012), DPS-01  2012 

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  • プリント基板/製品レベルでの暗号漏洩対策設計技術

    情報セキュリティセミナー  2012 

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  • 金属板近傍に配置された信号線からの放射電界を予測するための簡易等価モデルの提案

    第14回 IEEE広島支部学生シンポジウム, A-19, pp.54-57  2012 

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  • 間引き処理によるAES暗号の第10ラウンド鍵解読の高速化

    第14回 IEEE広島支部学生シンポジウム, A-83, pp.250-253  2012 

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  • 多導体線路系のモード等価回路構築の簡単化を目的としたネットリスト自動生成プログラムの作成

    第14回 IEEE広島支部学生シンポジウム, B-18, pp.330-333  2012 

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  • 平衡ケーブルと不平衡負荷の接続により生じる平衡度不整合がモード変換に及ぼす影響のモード等価回路を用いた評価

    第14回IEEE広島支部学生シンポジウム, B-19, pp.334-337  2012 

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  • 暗号処理基板におけるサイドチャネル攻撃の安全性予測

    ITソリューションフェアinママカリ’12  2012 

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  • 伝送線路の埋込みによるICパッケージのインダクタンス測定

    電子情報通信学会技術研究報告, エレクトロニクスシミュレーション研究会, EST2011-85, pp.11-16  2012 

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  • サイドチャネル攻撃に対するプリント基板上での対策技術としてのデカップリング効果のシミュレーション

    2012年暗号と情報セキュリティシンポジウム, 3C1-5  2012 

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  • モード分解法に基づくモード等価回路を用いた信号伝送系の回路解析

    第26回エレクトロニクス実装学会春季講演大会, 8A-10, pp.72-75  2012 

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  • 電源供給回路共振への臨界減衰適用によるIC/LSIのEMC性能改善

    第26回エレクトロニクス実装学会講演大会, 8A-19, pp.98-101  2012 

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  • 電力変換回路の線形等価回路モデル構築を目的とした2 ポートLISN の作製

    2012年電子情報通信学会総合大会, B-4-9, p.339  2012 

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  • 電力変換回路の伝導妨害波電圧低減設計を目的とした線形等価回路モデル構築

    2012年電子情報通信学会総合大会, B-4-10, p.340  2012 

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  • LECCSモデルを用いた暗号処理回路の等価電流源同定

    2012年電子情報通信学会総合大会, B-4-29, p.359  2012 

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  • 電源系配線のオンボードデカップリングによる暗号処理基板のサイドチャンネル攻撃耐性向上

    2011年電子情報通信学会総合大会, B-4-39, p. 352  2011 

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  • ケーブル接続された送受信機器のコモンモードモデルと同定(その3)

    電子情報通信学会技術研究報告 : 信学技報 111(319), 19-24  2011 

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  • EBG構造とフェライト膜を用いた電源層の不要電磁波伝搬抑制と電源品質の評価

    電子情報通信学会技術研究報告. EMCJ, 環境電磁工学 111(64), 75-80  2011 

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  • ケーブル接続された送受信機器のモード等価回路と同定(その2)

    電子情報通信学会技術研究報告. EMCJ, 環境電磁工学 111(64), 93-98  2011 

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  • チップ部へのTHRUパターンの埋め込みによるICパッケージインピーダンスの測定

    電子情報通信学会技術研究報告. EMCJ, 環境電磁工学 111(131), 31-36  2011 

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  • 2本のスタブを用いたオープンスタブ型EBG構造による阻止域の制御と設計

    電子情報通信学会技術研究報告. EMCJ, 環境電磁工学 111(131), 91-96  2011 

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  • PCB とその周辺のEMC およびSI/PI

    ギガビット研究会 第1回シンポジウム  2011 

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  • 寄生インピーダンスの共振に起因するIC電源系高周波電流ピークのダンピング抵抗挿入による低減

    電子情報通信学会技術研究報告. EMCJ, 環境電磁工学 111(269), 29-34  2011 

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  • 電力変換回路の伝導妨害波低減設計のための線形等価回路モデル構築

    電気・情報関連学会中国支部第62回連合大会  2011 

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  • 電力変換回路の線形等価回路モデル構築を目的とした2 ポートLISN の作製

    電気・情報関連学会中国支部第62回連合大会  2011 

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  • プリント回路基板と筺体の金属ネジ接続により発生する不要電磁波放射の抑制に関する研究

    第13回IEEE広島支部学生シンポジウム, A-21  2011 

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  • 電気光学プローブを用いた電界・磁界測定の検討

    第13回IEEE広島支部学生シンポジウム, A-22  2011 

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  • モード変換励振源を有するモード等価回路の有効性の実験的検証

    第13回IEEE広島支部学生シンポジウム, B-21  2011 

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  • オープンスタブ型EBG構造における2 本のスタブを用いた阻止域の制御

    2011年電子情報通信学会総合大会, B-4-40, p. 353  2011 

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  • 電源系デカップリングによる暗号用FPGAのサイドチャネル攻撃耐性向上

    電子情報通信学会技術研究報告. EMCJ, 環境電磁工学 111(18), 19-24  2011 

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  • ガードトレースへの周期構造導入による信号伝達特性の改善

    平成22年度電気・情報関連学会中国支部連合大会, pp. 186  2010 

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  • CISPR16-1準拠LISN用ローパスフィルタで使用するコイルの設計

    第12回IEEE 広島支部学生シンポジウム (HISS), A-4  2010 

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  • 平衡度不整合理論に基づくコモンモード等価アンテナの入力インピーダンスに注目したプリント回路基板からの放射量計算

    第12回IEEE広島支部学生シンポジウム (HISS), B-02  2010 

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  • EBG構造と磁性膜の組み合わせによる平行平板共振抑制における磁性膜の電気的特性依存性

    第12回IEEE 広島支部学生シンポジウム (HISS), B-04  2010 

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  • ケーブル接続された送受信機器のモード等価回路と同定

    電子情報通信学会環境電磁工学研究会, EMCJ2010-76, pp. 33-38  2010 

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  • LECCSモデルにおける寄生結合の評価とIBISモデルとの組み合わせによるPI/SI解析

    2010年電子情報通信学会ソサイエティ大会, BI-2-3, pp. SS81-SS82  2010 

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  • Fast and Optimal Placement of Decoupling-capacitors for Suppressing Radiated Emissions from Power-bus of Printed Circuit Boards

    2010 Asia-Pacific Radio Science Conference (AP-RASC'10), E2-4  2010 

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  • Increase of RF Power Current Due to Coupling between Power Distribution and IO Networks

    2010 Asia-Pacific Radio Science Conference (AP-RASC'10), EP-4  2010 

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  • IC/LSIに起因するEMIのI/O 端子終端条件の依存性に関する回路シミュレーションおよび実測による検証

    平成22年度電気・情報関連学会中国支部連合大会, pp. 137  2010 

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  • プリント回路基板上に構成するフィルタ設計を目的とした伝送線路モデルを用いた等価回路モデルの構築

    電子情報通信学会環境電磁工学研究会, EMCJ2009-112, pp. 81-86  2010 

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  • ケーブル接続された送受信機器のコモンモードモデルと同定

    電子情報通信学会環境電磁工学研究会, EMCJ2010-4, pp. 19-24  2010 

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  • Physics-Based Modeling of DGS Filter Formed on Return Plane of Printed Circuit Boards

    4th Pan-Pacific EMC Joint Meeting (PPEMC'2010), pp. 51-54  2010 

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  • EMIフィルタ設計への適用を目的とした電子レンジ内蔵インバータの線形等価回路モデル構築

    電子情報通信学会環境電磁工学研究会, EMCJ2010-14, pp. 25-30  2010 

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  • 電源系パターンの寄生容量を考慮したデカップリングインダクタの配置

    電子情報通信学会環境電磁工学研究会, EMCJ2010-28, pp. 39-44  2010 

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  • 電源-グランド間インピーダンス付加による非理想電源下でのIBISモデルの精度向上

    エレクトロニクス実装学会講演大会, 11A-07, 横浜, pp. 13-14  2009 

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  • EMI Simulation Based on Cavity Mode Model for Power-Bus Radiation Calculation of Power/Ground Planes with

    19th International Zurich Symposium on Electromagnetic Compatibility, WE-SEM-3-2, Singapore, pp. 427-430  2008 

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  • Determination of Grounding Location for Guard Trace to Reduce Common-mode Radiation

    International Conference on Electronics Packaging (ICEP) 2008, 11A3-1,Tokyo. pp. 124-129  2008 

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  • 配線パターンを変化させた基板による多電源ピンLECCS-coreモデルの評価

    電子情報通信学会技術研究報告, EMCJ2008-33,東京. pp. 43-48  2008 

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  • コモンモードアンテナモデルによるコネクタ接続されたプリント回路基板からの放射電磁波予測(その2)〜 インダクタ

    電子情報通信学会技術研究報告, EMCJ2008-32,東京. pp. 37-42  2008 

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  • Experimental Validation of Imbalance Difference Model to Estimate Common-Mode Excitation in PCBs

    2008 IEEE International Symposium on Electromagnetic Compatibility, TUE-AM-2-5, Detroit, USA  2008 

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  • Prediction of the Common-mode Radiated Emission from the Board to Board Interconnection through Common-mode Antenna Model

    2008 IEEE International Symposium on Electromagnetic Compatibility, THU-PM-1-4,Detroit, USA  2008 

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  • EMC Macro-modeling of CMOS Inverter Using LECCS-I/O Model with Additional Current Source

    2008 IEEE International Symposium on Electromagnetic Compatibility, THU-PM-1-5,Detroit, USA  2008 

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  • コモンモード放射低減のための抵抗付加によるガードトレース共振抑制

    IEEE広島支部 学生シンポジウム, B-18, 広島市, pp. 236-239  2008 

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  • プリント回路基板上の差動伝送におけるEBG構造を用いたコモンモード抑制効果の検証

    IEEE広島支部 学生シンポジウム, B-20, 広島市, pp. 264-267  2008 

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  • Suppressing Power Bus Resonance and Radiation Using Magnetic Material and EBG Structure

    19th International Zurich Symposium on Electromagnetic Compatibility, TH-SEM-5-1, Singapore, pp. 574-577  2008 

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  • Macro Model of Driver Circuits for EMI Simulation

    International Conference on Electronics Packaging (ICEP) 2008, 12C3-1,Tokyo. pp. 467-472  2008 

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  • 単一のスリットセグメントへの領域分割によるプリント回路基板の電源系共振の高速解析

    電子情報通信学会技術研究報告, EMCJ2008-118,東京, pp.25-30  2008 

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  • コモンモード放射低減のための平衡度不整合理論に基づくガードトレース接地法

    第22回エレクトロニクス実装学会講演大会, 17A-09, pp.17-18  2008 

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  • 多電源LSIのEMCマクロモデルLECCSの電流源位相が伝導ノイズシミュレーションに与える影響

    第22回エレクトロニクス実装学会学術講演大会, 18A-13, pp.91-92  2008 

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  • コモンモードアンテナモデルを実基板に適用するための検討―アンテナエレメントの取り扱いについて―

    電子情報通信学会総合大会, B4-55, 松山市, p. 398  2008 

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  • CMOSインバータの2電流源EMCマクロモデル構築

    電子情報通信学会総合大会, B-4-25, p. 334  2008 

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  • PCBの電源層間への高透磁率シート挿入による層間共振と放射の抑制

    電子情報通信学会2008総合大会, B-4-30, p.339  2008 

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  • 平衡度不整合理論で定義されるコモンモード励振源の実験的検証

    電子情報通信学会総合大会, B-4-37. p.346  2008 

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  • A Model of Signal Propagation along a Microstrip Line Crossing over a Slit in Ground Plane for Waveform

    The 3rd Pan-Pacific EMC Joint Meeting, 16S5-1, Tokyo, pp.91-92  2008 

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  • Common-Mode Radiation of Combined Boards deduced from the Common-Mode Antenna Model

    The 3rd Pan-Pacific EMC Joint Meeting, 15S1-4, Tokyo, pp.7-8  2008 

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  • EMI シミュレーションのためのドライバ回路のマクロモデル

    第22回エレクトロニクス実装学会講演大会, 18A-02, pp.69-70  2008 

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  • Modeling of a Microcontroller with Multiple Power Supply Pins for Conducted EMI Simulations

    2008 Electrical Design of Advanced Packaging and Systems Symposium (IEEE EDAPS 2008), D1-4-4, Seoul  2008 

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  • 伝送線路の電力伝搬モデルを用いた帰路面にスリットを有するプリント回路基板の信号品質解析

    IEEE広島支部 学生シンポジウム, B-24, 広島市, pp. 27-30  2008 

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  • I/Oゲートを介した給電系回路とI/O系回路との接続を考慮したマイクロコントローラ H8/3694FのEMCマクロモデル

    IEEE広島支部 学生シンポジウム, B-26, 広島市, pp. 299-302  2008 

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  • パッケージ・ボード間寄生結合のEMIへの影響とそのモデリング

    2008 Microwave Workshops and Exhibition (MWE 2008), WS-01-04, 横浜  2008 

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  • Determination of Effective Parasitic Capacitances around IC Package for EMC modeling

    EMC Compo 2007  2007 

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  • 寄生インピーダンスのEMCマクロモデルLECCS-coreに対する影響

    第21回エレクトロニクス実装学会講演大会, 15B-02, pp.117-118  2007 

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  • PCBの電源/グラウンドプレーンに形成したEBG構造に高透磁率材料を用いた単位セルの小型化と阻止域の拡大

    電子情報通信学会2007総合大会  2007 

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  • コモンモードアンテナモデルによるコネクタ接続されたプリント回路基板からの放射電磁波予測

    電子情報通信学会 環境電磁工学研究会 EMCJ2007-9, pp.45-54  2007 

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  • コモンモードアンテナモデルを用いたプリント回路基板からの放射予測-励振源の重ね合わせに関する検討-

    電子情報通信学会 環境電磁工学研究会 EMCJ2007-25, pp.39-44  2007 

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  • マイコンのEMCマクロモデル

    第13回EMCフォーラム 技術セッション「カーエレクトロニクスとEMC-最新モデルから学ぶマイコンのEMC挙動-」  2007 

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  • Miniaturization of Electromagnetic Bandgap (EBG) Structures with High-permeability Magnetic Metal Sheet

    2007 IEEE International Symposium on Electromagnetic Compatibility  2007 

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  • LECCSモデルの広帯域化を目的とした寄生容量表現法の検討

    電子情報通信学会環境電磁工学研究会, EMCJ2007-33, pp.5-10  2007 

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  • Prediction of Electromagnetic Emissions from PCBs with Interconnections Through Common-Mode Antenna Model

    18th International Zurich Symposium on Electromagnetic Compatibility (EMC Zurich Munich 2007), MOR-2, pp.107-110  2007 

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  • SPICEに基づくCMOSインバータのEMCマクロモデルの構築

    電気・情報関連学会中国支部第58回連合大会 講演番号13-5, p.91  2007 

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  • コネクタ接続プリント回路基板を用いたコモンモードアンテナモデルの評価

    IEEE広島支部 学生シンポジウム, B-14  2007 

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  • コモンモード放射低減のためのガードトレース接地ビア位置の検討

    IEEE広島支部 学生シンポジウム, B-15  2007 

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  • Excitation of Electromagnetic Modes by a Signal Transmission Line Overpassing a Slit of Return Plane

    PIERS(Progress In Electromagnetic Research Symposium) 2006-Tokyo  2006 

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  • Optical properties of Asian dust measured at several sites in Japan, IRS2004 : current problems in atmospheric radiation

    The International Radiation Symposium  2006 

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  • LSI電源系インピーダンスにおける内部回路動作所帯依存性の実験的検証

    電気・情報関連学会中国支部第57回連合大会  2006 

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  • バイスタティックライダによる水雲粒子径測定原理の検証

    電気・情報関連学会中国支部第57回連合大会  2006 

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  • マイクロストリップ線路の帰路面にあるスリットによって発生する複数モードの伝搬電力計算

    電気・情報関連学会中国支部第57回連合大会  2006 

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  • 直角に曲がったマイクロストリップ線路を有するプリント回路基板におけるコモンモードアンテナモデルを用いた放射予測

    電気・情報関連学会中国支部第57回連合大会  2006 

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  • 不平衡度変化に基づくコモンモードアンテナモデルを用いたコネクタ結合プリント回路基板からのコモンモード放射量予測

    電気・情報関連学会中国支部第57回連合大会  2006 

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  • Electromagnetic Modes Excited by a Signal Transmission Line Overpassing a Slit of Return Plane

    2nd Pan-Paciffic EMC Joint Meeting (PPEMC'06)  2006 

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  • 高速EMI シミュレータの開発を目的としたプリント回路基板からの放射計算

    IEEE広島支部 学生シンポジウム  2006 

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  • パッチアンテナ設計ツール開発を目的とした対向スリットを有平行2層板の共振特性解析

    IEEE広島支部 学生シンポジウム  2006 

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  • EBG構造を持つ電源/グランドプレーンの高透磁率材料による小型化

    IEEE広島支部 学生シンポジウム  2006 

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  • EMI Antenna Model Based on Common-Mode Potential Distribution for Fast Prediction of Radiated Emission

    IEEE  2006 

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  • LECCS-I/Oモデルの広帯域化を目的とした3ポートSパラメータ測定によるインピーダンスパラメータ抽出法の検討

    電子情報通信学会環境電磁工学研究会  2006 

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  • 黄砂飛来時の非水溶性粒子の粒径分布および吸収特性

    日本気象学会2005年度秋季大会  2005 

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  • 西日本4地点で取得したライダプロファイルの比較にもとづく黄砂輸送経路の推定

    第24回レーザセンシングシンポジウム  2005 

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  • ライダで測定した黄砂層における偏光解消度の粒径および体積密度に対する依存性の検証

    電気・情報関連学会中国支部第56回連合大会  2005 

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Industrial property rights

  • 印刷配線板

    豊田啓孝, 五百旗頭健吾, 林星小雨, 金子俊之, 内藤政則, 上原利久

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    Application no:CN ZL 201780046116.0  Date applied:2017.7.20

    Patent/Registration no:CN ZL 201780046116.0  Date registered:2021.4.23 

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  • 印刷配線板

    豊田啓孝, 五百旗頭健吾, 林星小雨, 金子俊之, 内藤政則, 上原利久

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    Application no:CN ZL 201780046115.6  Date applied:2017.7.20

    Patent/Registration no:CN ZL 201780046115.6  Date registered:2021.9.21 

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  • Printed wiring board and method of producing the same

    Yoshitaka Toyota, Kengo Iokibe, Yuki Yamashita, Toshiyuki Kaneko, Masanori Naito, Kiyohiko Kaiya, Toshihisa Uehara, Koichi Kondo

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    Application no:US 15/010,733  Date applied:2016.1.29

    Announcement no:US 2016/0227643 A1  Date announced:2016.8.4

    Patent/Registration no:US 10,104,765  Date registered:2018.10.16 

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  • 印刷配線板およびその製造方法

    豊田啓孝, 五百旗頭健吾, 山下祐輝, 金子俊之, 内藤政則, 海谷清彦, 上原利久, 近藤幸一

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    Application no:CN ZL201610066798.9  Date applied:2016.1.29

    Announcement no:CN 105657957 A  Date announced:2016.6.8

    Patent/Registration no:CN ZL201610066798.9  Date registered:2019.10.15 

    201610066798.9

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  • 印刷配線板およびその製造方法

    豊田啓孝, 五百旗頭健吾, 山下祐輝, 金子俊之, 内藤政則, 海谷清彦, 上原利久, 近藤幸一

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    Application no:TW 105102474  Date applied:2016.1.27

    Announcement no:TW 201640978  Date announced:2016.11.16

    Patent/Registration no:TW I682699  Date registered:2020.1.11 

    TW 201640978

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  • 印刷配線板およびその製造方法

    豊田啓孝, 五百旗頭健吾, 山下祐輝, 金子俊之, 内藤政則, 海谷清彦, 上原利久, 近藤幸一

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    Application no:特願2015-39026  Date applied:2015.2.27

    Announcement no:特開2016-111314  Date announced:2016.6.20

    Patent/Registration no:特許6894602  Date registered:2021.6.8 

    特開2016-111314

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  • 印刷配線板およびその製造方法

    豊田啓孝, 五百旗頭健吾, 山下祐輝, 内藤政則, 金子俊之, 海谷清彦, 上原利久, 近藤幸一

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    Application no:特願2019-084201  Date applied:2015.2.27

    Patent/Registration no:特許6829448  Date registered:2021.1.26 

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Awards

  • HISS最優秀研究賞

    2015  

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    Country:Japan

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  • 電気学会中国支部奨励賞

    2015  

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    Country:Japan

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  • 第16回IEEE広島支部学生シンポジウム優秀研究賞

    2014  

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    Country:Japan

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  • 研究功績賞

    2014  

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    Country:Japan

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  • 電気学会中国支部奨励賞

    2014  

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    Country:Japan

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  • EMTS 2013 Young Scientist Award

    2013  

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    Country:Japan

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  • 第15回 IEEE広島支部学生シンポジウム優秀研究賞

    2013  

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    Country:Japan

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  • Best Student Paper Award (Poster Presentation)

    2013  

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    Country:Japan

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  • 第26回エレクトロニクス実装学会春季講演大会優秀賞

    2013  

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  • IEICE Technical Committee on Electromagnetic Compatibility Young Scientist Excellent Paper Award

    2012  

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    Country:Japan

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  • エレクトロニクス実装学会電磁特性技術委員会賞

    2012  

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  • 第13回IEEE広島支部学生シンポジウム(HISS)優秀研究賞

    2011  

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  • 環境電磁工学研究会(EMCJ)若手優秀賞

    2011  

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  • IEEE広島支部学生シンポジウム(HISS)優秀研究賞

    2010  

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  • IEEE EMC Society Japan/Sendai Chapters Student Award

    2010  

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  • IEEE広島支部学生シンポジウム(HISS)最優秀プレゼンテーション賞

    2010  

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  • IEEE広島支部学生シンポジウム(HISS)優秀研究賞

    2010  

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  • エレクトロニクス実装学会電磁特性技術委員会賞

    2008  

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Research Projects

  • Design method development of side-channel attack countermeasures for cryptographic hardware based on signal-to-noise ratio of electromagnetic leakage

    Grant number:19H04110  2019.04 - 2023.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    五百旗頭 健吾

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    Grant amount:\15990000 ( Direct expense: \12300000 、 Indirect expense:\3690000 )

    (1)サイドチャネル情報漏洩源のSN比同定
    暗号回路の設計情報より暗号処理に伴って発生するスイッチング電流を予測し、その予測電流をSC解析した結果が実測より同定したスイッチング電流をSC解析した結果と一致することを示した(IEICE Trans. Comm.)。この結果はICチップにおけるSC情報漏洩強度を設計情報より予測できたことを意味している。SC情報漏洩強度とSN比の関係も検証済みであることから、情報漏洩源のSN比を同定できた。
    (2)サイドチャネル情報漏洩経路の伝達係数低減法
    AESアルゴリズムのFPGA実装およびマイコン実装についてSC情報漏洩帯域を実験的に検証した。その結果、クロック周波数とその高調波の側波帯、およびクロック周波数の下側波帯より低域に漏洩帯域があることを確認した。SC対策用フィルタのモデル化について、情報漏洩源から観測ポートへの伝達インピーダンスに関する検討を行った。その結果、伝達インピーダンスとSC情報漏洩強度に相関があることを確認した。SC情報漏洩の周波数特性から漏洩強度を予測するための定式化に関して、SN比と漏洩強度の関係式の妥当性を実験的に検証し、SN比に基づくSC情報漏洩強度予測の実現可能性を示した。(EMCJ2020-1)
    (3)SN比の目標値決定とその検証
    評価基板を作製し、評価用AES回路をFPGA実装した。暗号ICおよび評価用基板の等価回路モデル同定に関して、基板CADデータを電磁界解析モデルに変換するための中間モデルを作製した。関連して、SCA耐性評価基板として必要な電気的仕様を検討した。(HWS2020-11)

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  • Realization of secure and reliable communication in a remote control type / autonomous mobile system in the IoT era

    Grant number:16H01723  2016.04 - 2019.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)  Grant-in-Aid for Scientific Research (A)

    Nogami Yasuyuki

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    Grant amount:\39390000 ( Direct expense: \30300000 、 Indirect expense:\9090000 )

    In this research, using a specific drive system such as an electric vehicle and robot capable of autonomous driving and remote control, the advanced security technology (data authentication, device authentication, secure key update) we have clarified the security level that is realized without any problems by verifying how much the real-time performance is affected. Specifically, for the CAN system, data authentication with message authentication code that is generated by AES, random number generator, and lightweight encryption has been implemented. Then, side-channel attack has been demonstrated experimentally, key update function as the countermeasure using elliptic pairing-based cryptography has been also implemented. Their real-time processing could be realized.

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  • Vulnerability simulation of cryptographic circuit to side-channel attacks based on IC design information

    Grant number:16K00186  2016.04 - 2019.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)  Grant-in-Aid for Scientific Research (C)

    Iokibe Kengo

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    Grant amount:\4550000 ( Direct expense: \3500000 、 Indirect expense:\1050000 )

    A method to estimate side channel attack (SCA) vulnerability of cryptographic circuit from design information of IC was developed. The SCA vulnerability was simulated for an FPGA-implemented AES circuit and agreed with the measurement results accurately. Next, for establishing an SCA vulnerability design method, a theoretical formula that expresses the side channel information leakage (SCIL) intensity with the SNR of the leakage trace is verified by experiments, and its effectiveness is confirmed. Furthermore, the SCIL band of the AES circuit was derived and confirmed to be consistent with the experimental results, suggesting that the SCA vulnerability design method can be established based on the formula and the equivalent circuit model of FPGA power distribution circuit. Finally, we developed an electromagnetic interference source estimation method applying the SCA method and accurately estimated the interference intensities caused by individual interference sources.

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  • A Study of Developing a Prediction Method of Security of Cryptographic Devices against Side-Channel Attacks Based on Information Leakage Potential

    Grant number:26870392  2014.04 - 2016.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (B)  Grant-in-Aid for Young Scientists (B)

    Iokibe Kengo

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    Grant amount:\3900000 ( Direct expense: \3000000 、 Indirect expense:\900000 )

    Aiming for developing a method to predict security of cryptographic devices against side-channel attacks that is a new cryptanalytic method using physical behavior of the devices, we firstly confirmed that strength of side-channel information leakage can be simulated with an equivalent circuit model of an integrated circuit (IC) implementing a cryptographic circuit. Next, we indicated that the behavior of the cryptographic IC leaking the side-channel information can be seen in the equivalent circuit model. This can help develop a new and more efficient countermeasures to the attacks. Finally, we identified signal-to-noise ratios of side-channel traces as an information leakage potential to be used in prediction of side-channel attack security.

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  • 暗号機器のサイドチャネル攻撃に対する安全設計に関する研究開発

    2012.04 - 2013.03

    総務省  戦略的情報通信研究開発推進事業(SCOPE)  地域ICT振興型研究開発

    五百旗頭健吾, 渡邉 哲史, 籠谷裕人, 野上保之, 豊田啓孝

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  • Equivalent Model for Estimating Common-mode Noise in Complicated Systems

    Grant number:22360115  2010 - 2012

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    KOGA Liuji R, TOYOTA Yoshitaka, IOKIBE Kengo

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    Grant amount:\18330000 ( Direct expense: \14100000 、 Indirect expense:\4230000 )

    As for the issues of common-mode noise in complicated systems, we developed an equivalent model to use for analyzing the issues and consider countermeasures effectively. The model was developed focusing on the imbalance factor of the transmission line: mode conversion, which occurs at the interface where the imbalance factors change, is expressed by controlled sources; the power of mode conversion is expressed using modal characteristic impedance and the difference of the imbalance factors. This suggests that the imbalance factor be available as a design parameter as well as characteristic impedance. The model, which is an expansion of the multi-conductor transmission-line theory, will contribute to develop a new theoretical scheme for treating the present electrical and electronic systems.

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  • プリント基板で発生する放射EMI予測法の確立

    2009.04 - 2010.03

    科学技術振興機構(JST)  研究成果展開事業(企業化開発・ベンチャー支援・出資) 地域イノベーション創出総合支援事業 重点地域研究開発推進プログラム  シーズ発掘試験

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Class subject in charge

  • Security Implementation Exercise B (2021academic year) Fourth semester  - その他

  • Introduction to Security (2021academic year) 3rd and 4th semester  - 水7,水8

  • Laboratory Work and Practice on Basic Engineering (2021academic year) 1st and 2nd semester  - 火5,火6,火7,火8

  • Laboratory Work and Practice on Basic Engineering (2021academic year) 1st and 2nd semester  - 火5,火6,火7,火8

  • Laboratory Work and Practice on Basic Engineering (2021academic year) 1st and 2nd semester  - 火5,火6,火7,火8

  • Laboratory Work and Practice on Basic Engineering (2021academic year) 1st and 2nd semester  - その他

  • Technical Writing (2021academic year) Prophase  - その他

  • Technical Presentation (2021academic year) Late  - その他

  • Specific Research of Electronics and Information Systems Engineering (2021academic year) Year-round  - その他

  • Exercises on Cross-site Scripting Prevention (2020academic year) Summer concentration  - その他

  • Basic of information security E (2020academic year) 3rd and 4th semester  - 水7,水8

  • Collision-based Attack on Cryptography for Security Evaluation (2020academic year) Summer concentration  - その他

  • Laboratory Work and Practice on Basic Engineering (2020academic year) 1st and 2nd semester  - 火4,火5,火6,火7

  • Laboratory Work and Practice on Basic Engineering (2020academic year) 1st and 2nd semester  - 火4,火5,火6,火7

  • Cryptographic Hardware Security (2020academic year) Fourth semester  - その他

  • Technical Writing (2020academic year) Prophase  - その他

  • Technical Presentation (2020academic year) Late  - その他

  • Communication Network Engineering Lab I (2020academic year) 1st and 2nd semester  - 水2,水3,水4,水5,水6

  • Communication Network Engineering Exercise II (2020academic year) 3rd and 4th semester  - その他

  • Specific Research of Electronics and Information Systems Engineering (2020academic year) Year-round  - その他

  • Topics in Electronic and Information Systems Engineering (2020academic year) Prophase  - 金1,金2

  • Electrical and Communication Engineering Lab B (2020academic year) 3rd and 4th semester  - 水2,水3,水4,水5,水6

  • Electrical and Communication Engineering Lab II (2020academic year) 3rd and 4th semester  - 水2,水3,水4,水5,水6

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