Updated on 2022/11/02

写真a

 
KAGOTANI Hiroto
 
Organization
Institute for Promotion of Education and Campus Life Associate Professor
Position
Associate Professor
External link

Degree

  • 博士(工学) ( 東京工業大学 )

Research Interests

  • VLSIシステム設計

  • 非同期式プロセッサ

  • 自動合成

  • 局所性緩和

  • 非同期式回路

  • ランダム割当て

  • 最適化

  • パイプライン

  • 非同期式VLSIシステム

  • スケジューリング

  • 非同期式回路テスト

  • 非同期式論理合成

  • パイプライン動作

  • グラフ変形

  • 演算器割当て

  • パイプライン機構

  • 2相動作

  • 2相非同期式回路

  • 依存性グラフ

  • マッチング問題

Research Areas

  • Informatics / Computer system

Research History

  • Okayama University   Institute for Education and Student Services   Associate Professor

    2020.4

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  • Okayama University   The Graduate School of Natural Science and Technology   Lecturer

    2005.4 - 2020.3

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  • Okayama University   Faculty of Engineering   Lecturer

    1998.7 - 2005.3

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  • Okayama University   Faculty of Engineering   Research Assistant

    1994.10 - 1998.6

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Papers

  • A Consideration of Side-Channel Attacks on Curve25519 using Order 4 Rational Points

    ( 2019 )   69 - 74   2019.8

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    Language:Japanese  

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  • An Efficient Algorithm to Determine Equivalence of Pipelined Dependency Graphs for Their Simplification

    100 ( 6 )   616 - 626   2017.6

  • Attempt for Determining Cryptographic Circuit Blocks Leaking Side-Channel Information Based on Internal Current Source : Examination with FPGA Implementation of AES Circuits

    116 ( 253 )   79 - 84   2016.10

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  • Analysis of Side-channel Information Leaking Behavior in Cryptographic Circuit using Internal Current Source

    Iokibe Kengo, Tai Nobuhiro, Kagotani Hiroto, Onishi Hiroyuki, Toyota Yoshitaka, Watanabe Tetsushi

    IEEJ Transactions on Fundamentals and Materials   136 ( 6 )   365 - 371   2016

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    Language:Japanese   Publisher:The Institute of Electrical Engineers of Japan  

    Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors; (1) leakage is reduced by making Hamming distance (HD) at registers constant, (2) leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

    DOI: 10.1541/ieejfms.136.365

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  • FPGA Implementation of Various Elliptic Curve Pairings over Odd Characteristic Field with Non Supersingular Curves.

    Yasuyuki Nogami, Hiroto Kagotani, Kengo Iokibe, Hiroyuki Miyatake, Takashi Narita

    IEICE Trans. Inf. Syst.   99-D ( 4 )   805 - 815   2016

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    Pairing-based cryptography has realized a lot of innovative cryptographic applications such as attribute-based cryptography and semi homomorphic encryption. Pairing is a bilinear map constructed on a torsion group structure that is defined on a special class of elliptic curves, namely pairing-friendly curve. Pairing-friendly curves are roughly classified into supersingular and non supersingular curves. In these years, non supersingular pairing-friendly curves have been focused on from a security reason. Although non supersingular pairing-friendly curves have an ability to bridge various security levels with various parameter settings, most of software and hardware implementations tightly restrict them to achieve calculation efficiencies and avoid implementation difficulties. This paper shows an FPGA implementation that supports various parameter settings of pairings on non supersingular pairing-friendly curves for which Montgomery reduction, cyclic vector multiplication algorithm, projective coordinates, and Tate pairing have been combinatorially applied. Then, some experimental results with resource usages are shown.

    DOI: 10.1587/transinf.2015ICP0018

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    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet99d.html#NogamiKIMN16

  • Analysis on equivalent current source of AES-128 circuit for HD power model verification

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    IEEE International Symposium on Electromagnetic Compatibility   2014-December   302 - 305   2014.12

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    Publishing type:Research paper (international conference proceedings)  

    We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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  • Investigation in burst pulse injection method for fault based cryptanalysis

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    IEEE International Symposium on Electromagnetic Compatibility   2014-September ( September )   743 - 747   2014.9

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    This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

    DOI: 10.1109/ISEMC.2014.6899067

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  • Investigation on Aes Circuits in Information-Leaking-Behavior by Means of Internal Equivalent Current Source

    TAI Nobuhiro, IOKIBE Kengo, KAGOTANI Hiroto, OONISHI Hiroyuki, MAESHIMA Kazuhito, TOYOTA Yoshitaka, WATANABE Tetsushi

    IEICE technical report. Electromagnetic compatibility   114 ( 93 )   13 - 18   2014.6

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    In our previous study, we identified an internal equivalent current source representing the internal switching current of a cryptographic IC that occurred as the IC operated an encryption operation. Since the internal switching current is the source of information leakage, the internal equivalent current source is expected to be able to be applied to evaluate cryptographic ICs in security of side-channel attack. In this study, we investigated the internal equivalent current source with regard to its behavior as the source of information leakage. The investigation revealed that variance of the switching current varied temporally in a round operation and that the AES circuit with a hiding countermeasure provided information leakage at the moment when the variance was smaller than that in the remaining time period. This suggested that cryptographic circuits can be analyzed of their behavior as the information leakage source according to the internal equivalent current source.

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  • Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption

    TASAKI Tomoya, KAGOTANI Hiroto, SUGIYAMA Yuji

    IEICE technical report   113 ( 418 )   43 - 48   2014.1

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been proposed. However, the size of circuits synthesized by this algorithm tends to be large because it assumes QDI delay model. Yoshitake proposed a reduction method using a characteristic of a maximum delay loop in a dependency graph under SDI delay model. In this paper, we improve the method by extending the application range to dependency graphs that have multiple maximum delay loop.

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  • Evaluation of parallelization for multiple-precision Cyclic Vector Multiplication Algorithm using CUDA

    HARAMURA Satoshi, KAGOTANI Hiroto, NOGAMI Yasuyuki, SUGIYAMA Yuji

    IEICE technical report   113 ( 418 )   109 - 112   2014.1

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    Recently, studies on implementation of cryptographical algorithms on GPUs are widely conducted as GPGPU development environment provides easy access to GPUs for non-graphics programming. In this paper, we implement cyclic vector multiplication algorithm, or an efficient multiplication algorithm on extension fields, that will accelerate pairing cryptography. Since we adopt 256-bit characteristic for the base fields, we also implement Montgomery multiplication for 256-bit operands on GPU. As the result of implementation on NVIDIA GeForce GTX680, it is over 10 times slower than implementation on Core i7 3970X.

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  • Investigation in Burst Pulse Injection Method for Fault Based Cryptanalysis

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuyuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)   743 - 747   2014

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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  • Analysis on Equivalent Current Source of AES-128 Circuit for HD Power Model Verification

    Kengo Iokibe, Kazuhiro Maeshima, Hiroto Kagotani, Yasuvuki Nogami, Yoshitaka Toyota, Tetsushi Watanabe

    2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO)   302 - 305   2014

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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  • Investigation on FPGA Malfunctions by Clock Glitch Induced by Disturbance Invasion through Power Cable

    Iokibe Kengo, Maeshima Kazuhiro, Watanabe Tetsushi, Kagotani Hiroto, Nogami Yasuyuki, Hayashi Yu-ichi, Toyota Yoshitaka, Sone Hideaki

    Proceedings of JIEP Annual Meeting   28 ( 0 )   63 - 66   2014

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    Language:Japanese   Publisher:The Japan Institute of Electronics Packaging  

    DOI: 10.11486/ejisso.28.0_63

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  • Simplification of Pipelined Dependency Graphs by Minimizing the Number of Select and Merge Nodes

    KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji, MA Bin, CHNG Eng Siong, LI Haizhou

    IEICE Transactions on Information and Systems   95 ( 5 )   1206 - 1215   2012.5

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    In this paper, we propose integration of multimodal features using conditional random fields (CRFs) for the segmentation of broadcast news stories. We study story boundary cues from lexical, audio and video modalities, where lexical features consist of lexical similarity, chain strength and overall cohesiveness; acoustic features involve pause duration, pitch, speaker change and audio event type; and visual features contain shot boundaries, anchor faces and news title captions. These features are extracted in a sequence of boundary candidate positions in the broadcast news. A linear-chain CRF is used to detect each candidate as boundary/non-boundary tags based on the multimodal features. Important interlabel relations and contextual feature information are effectively captured by the sequential learning framework of CRFs. Story segmentation experiments show that the CRF approach outperforms other popular classifiers, including decision trees (DTs), Bayesian networks (BNs), naive Bayesian classifiers (NBs), multilayer perception (MLP), support vector machines (SVMs) and maximum entropy (ME) classifiers.

    DOI: 10.1587/transinf.E95.D.1206

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  • D-6-3 A Method for Size Reduction of Asynchronous Circuits using Maximum Delay Loop in Dependency Graphs

    Yoshitake Terutoshi, Kagotani Hiroto, Sugiyama Yuji

    Proceedings of the IEICE General Conference   2012 ( 1 )   64 - 64   2012.3

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  • D-1-1 Implementation and Evaluation of Branch and Bound Method on CUDA

    Irie Takeshi, Kagotani Hiroto, Sugiyama Yuji

    Proceedings of the IEICE General Conference   2012 ( 1 )   1 - 1   2012.3

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  • Memory Saving Implementation of Cyclic Vector Multiplication Algorithm

    TAKAHASHI Ryosuke, NEKADO Kenta, TAKAI Yusuke, NOGAMI Yasuyuki, KAGOTANI Hiroto, NARITA Takashi

    IEICE technical report   111 ( 124 )   145 - 150   2011.7

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    The authors have proposed a cyclic vector multiplication algorithm abbreviated as CVMA that is flexible to the parameters of extension field, that is extension degree and charasteristic. For the hardware implementation of CVMA, the authors have improved the double loop structure of CVMA to a single loop one, and it has been presented at SITA2010. However, it has a problem that it needs a lot of memory. Thus, this paper proposes a method to save the memory use of the single loop version of CVMA.

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  • Verification of Dependency Graph Pipelining Algorithm for Synthesizing Asynchronous Control Circuits

    KAGOTANI Hiroto, SUGIYAMA Yuji

    The IEICE transactions on information and systems   93 ( 11 )   2343 - 2353   2010.11

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  • Classification of MRCPs and Type-I CVMA Modified for Its Prime Field Multiplication

    TAKAI Yusuke, NEKADO Kenta, NOGAMI Yasuyuki, MORIKAWA Yoshitaka, KAGOTANI Hiroto

    IEICE technical report   110 ( 137 )   19 - 24   2010.7

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    Cyclic vector multiplication algorithm (CVMA) has been originally proposed as a vector multiplication algorithm for elements in a certain extension field. Recently, Granger et al. have proposed the primes called Minimal Redundancy Cyclotomic Primes (MRCPs) and they have applied CVMA for the modular multiplications with MRCPs. This paper shows that several detailed classes of MRCPs and their customized multiplication algorithms.

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  • Design and Development of a Web Application for Cooperative Software Asset Management

    TODORI Akitoshi, KAGOTANI Hiroto, SUGIYAMA Yuji

    IEICE technical report   108 ( 457 )   217 - 222   2009.2

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    Strict software asset management and legal use is part of corporate social responsibility. In our laboratory, we investigate the software asset periodically in order to guarantee legal use of software license. This investigation procedures, however, are likely to cause mistakes and omissions, and require the administrator and members a long time. In order to solve these problems, we design and develop a Web application system for software license asset management that can improve the efficiency of investigation. On the system, members log in to the server and enter information about their PCs and software via their Web browsers. Users can submit the information of their connecting PCs by just one click without manual investigation. As the result of a questionnaire, the system was evaluated as quite useful. Also, further improvement of the user interface was requested.

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  • A Proposal of a Scalable Web Server System Using Virtual Machine Monitor "Xen"

    SHOJI Tomoya, INOUE Yuuki, FUNABIKI Nobuo, NAKANISHI Toru, KAGOTANI Hiroto

    IEICE technical report   108 ( 286 )   105 - 108   2008.11

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    Recently, the virtualization technology has been often used to construct servers due to the efficiency of the computer resource utilization and the easiness of the system extension. The method of composing cluster systems using the virtualized servers has also been proposed. In this paper, we propose a safe and scalable Web server system using the virtualization technology. In this system, the SSL authentication protocol is adopted to authenticate the server hosts and the encrypted data communications. Besides, the system management tool is incorporated for the simple system management by realizing the automatic update functions of the system softwares such as the operating system and the Web server. We implemented the proposed system using Puppet as the system management tool, Ruby SNMP as the system management library, and Xen as the virtualization machine monitor. The experimental result using our implementation confirms the short time for the Web server extension.

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  • Control Circuit Construction for Asynchronous Pipeline Synthesis Using Dependency Graphs

    KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji

    The IEICE transactions on information and systems   91 ( 2 )   402 - 412   2008.2

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  • Synthesis of Asynchronous Pipelines Using Control Flow Graphs

    KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji

    The IEICE transactions on information and systems   90 ( 5 )   1167 - 1177   2007.5

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  • Experimental Evaluations of Network Load Dispersion Effects by VNC Proxy

    MATSUMOTO Kohei, KAGOTANI Hiroto, KOUMOTO Takuya, FUNABIKI Nobuo

    IEICE technical report   106 ( 355 )   51 - 54   2006.11

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    The Virtual Network Computing (VNC) has problems such as network load increase and access control for practical use in multi-client environment. We develop a VNC Proxy to solve those problems. In this paper, we evaluate load dispersion performance of the VNC Proxy through experimental results. We arrange proxies in consideration of the network toporogy and measure the network load and delay in the experiment. As a result, network load were dispersed by the VNC Proxy without critical delay.

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  • Synthesis of Asynchronous Pipelines using Control Flow Graphs

    KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji

    IEICE technical report   106 ( 199 )   1 - 6   2006.7

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    In this paper, we propose a method for synthesizing pipelines for asynchronous processor design using a kind of control flow graphs (dependency graphs). We first represent a specification given in CHP form as a secuential dependency graph and convert it into a set of small dependency graphs (minimal dependency graphs) each of which represents execution order of a dependent pair of micro-operations. Next, we synthesize a pipelined dependency graph from the minimal dependency graphs. Our method can implement asynchronous pipeline datapaths with much less registers than Teifel's method.

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  • A Proposal of Proxy for Load Dispersion and Access Control in VNC System

    MATSUMOTO Kohei, KAGOTANI Hiroto, KOUMOTO Takuya, FUNABIKI Nobuo

    IEICE technical report   106 ( 41 )   57 - 60   2006.5

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    The Virtual Network Computing (VNC) is a useful network application to let a user operate the desktop display of a remote PC on his/her local PC. However, VNC has two problems for practical use in multi-client environment. One is the increase of network loads when a number of clients are connecting to a VNC server. Another is the lack of capability of the access control of each user by the administrator of the VNC server. The more clients connect VNC server, the more serious these problems become. In this paper, we present a VNC proxy to solve these problems, where it reduces the network loads by dispersing the roles of the server into multiple mirrors, and enables the VNC administrator to control the access right by each client.

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  • Speed-up of Affine Transformation Realized by Decomposing It into Two One-dimensional processes : Consideration Based on the Usage of a DSP with Parallel Datapaths

    OHTA Hiroshi, OZAKI Ryo, KAGOTANI Hiroto, HASHIMOTO Reiji, OKAMOTO Takuji

    IEICE technical report   105 ( 689 )   27 - 32   2006.3

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    This paper describes a method of fast affine transformation for video images. A DSP with parallel datapaths and a single local memory for a data buffer is used. The affine transformation is carried out by decomposing it into two consecutive one dimensional processes; one for horizontal direction and the other for vertical. In order to speed up the transformation, a main memory (MM) and the local memory (LM) are structured to a ring buffer for frames of the video image and to a ring buffer for parts of a frame, respectively. It is desirable to select the number of datapaths so that the time required for transmission of a part of a frame between MM and LM becomes nearly equal to that for its interpolation by datapaths. Experimental results showed that the transformation speed in the proposed method was about five times faster than usual ones.

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  • Superconductive logic circuits constructed by the use of two thresholds of SQUID.

    Masahiro Kawai, Yoichiro Sato, Hiroto Kagotani, Takuji Okamoto

    Systems and Computers in Japan   36 ( 2 )   42 - 50   2005

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    DOI: 10.1002/scj.20136

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  • A Synthesis Method of Control Circuits for Pipelined Asynchronous Processors

    ONISHI Yozo, KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji

    117 ( 122 )   191 - 196   2004.12

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    Language:Japanese   Publisher:Information Processing Society of Japan (IPSJ)  

    We propose a synthesis method of control circuits for pipelined asynchronous processors from specifications given as a dependency graph and dependencies. This method gives control circuits by connecting handshaking control modules corresponding to graph nodes according to the edges of the graph and dependencies. These control modules are designed to achieve efficient pipelines by parallelizing working and idle phases, which are composing a micro-operation. This method can synthesize smaller hardware than a conventional one.

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  • A Synthesis Method of Control Circuits for Pipelined Asynchronous Prosessors

    ONISHI Yozo, KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji

    IEICE technical report. Dependable computing   103 ( 482 )   121 - 126   2004.12

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    We propose a synthesis method of control circuits for pipelined asynchronous processors from specifications given as a dependency graph and dependencies. This method gives control circuits by connecting handshaking control modules corresponding to graph nodes according to the edges of the graph and dependencies. These control modules are designed to achieve efficient pipelines by parallelizing working and idle phases, which are composing a micro-operation. This method can synthesize smaller hardware than a conventional one.

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  • A Pipelining Algorithm for Asynchronous Processors

    KAGOTANI Hiroto, SUGIYAMA Yuji, OKAMOTO Takuji

    VLD2004   104 ( 321 )   9 - 14   2004.9

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    We propose a synthesis method for pipelines that improve throughput of asynchronous processors. In this paper, we focus on restricted specifications that do not include conditional branches. Given a specification as a set of dependencies between micro-operations executed in a target processor, the proposed algorithm can synthesize a pipelined Dependency Graph representing execution sequence of micro-operations in the processor. We focus on restricted specifications excluding conditional branches.

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  • Model analysis of coronary hemodynamics incorporating autoregulation.

    Mitsuyasu Kagiyama, Hiroyuki Michinishi, Hiroto Kagotani, Takuji Okamoto, Yasuo Ogasawara, Fumihiko Kajiya

    Systems and Computers in Japan   35 ( 14 )   21 - 31   2004

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    Publishing type:Research paper (scientific journal)  

    DOI: 10.1002/scj.10709

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  • Superconductive Logic Circuits Constructed by the Use of Two Thresholds of SQUID

    KAWAI Masahiro, SATO Yoichiro, KAGOTANI Hiroto, OKAMOTO Takuji

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   86 ( 12 )   855 - 862   2003.12

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  • Simulation of Coronary Hemodynamics

    OGASAWARA Yasuo, MICHINISHI Hiroyuki, KAGOTANI Hiroto, OKAMOTO Takuji, KAJIYA Fumihiko

    IEICE technical report. ME and bio cybernetics   103 ( 376 )   45 - 45   2003.10

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  • Model Analysis of Coronary Hemodynamics Incorporating Auto-Reguration

    KAGIYAMA Mitsuyasu, MICHINISHI Hiroyuki, KAGOTANI Hiroto, OKAMOTO Takuji, OGASAWARA Yasuo, KAJIYA Fumihiko

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   86 ( 10 )   1502 - 1510   2003.10

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    Other Link: http://search.jamas.or.jp/link/ui/2004070791

  • A Multi-Window System for Smooth Window Operations by the Combination of Drawing-Period Generation Method and Display-Period Generation Method

    SATO Yoichiro, YOKOHIRA Tokumi, KAGOTANI Hiroto, OKAMOTO Takuji, KAYANO Isao

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   86 ( 9 )   650 - 660   2003.9

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  • Analysis of hemodynamics taking account of auto-reguration

    KAGIYAMA Mitsuyasu, MICHINISHI Hiroyuki, KAGOTANI Hiroto, OKAMOTO Takuji, OGASAWARA Yasuo, KAJIYA Fumihiko

    IEICE technical report. ME and bio cybernetics   102 ( 597 )   17 - 20   2003.1

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    In this paper, coronary hemodynamics of the beating heart is analyzed by a simulation study. The auto-regulation is modeled by changing the elastance values at arterioles. The auto-regulation subsystem is incorporated into our previous medel. Blood flows and their waveforms in the arterioles are analyzed transmurally, and the effects of the auto-regulation on intramyocardial arterial now are studied by changing pressure amplitude.

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  • Asynchronous PipeRench: Architecture and Performance Estimations.

    Hiroto Kagotani, Herman Schmit

    11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003)(FCCM)   121   2003

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE Computer Society  

    DOI: 10.1109/FPGA.2003.1227248

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    Other Link: https://dblp.uni-trier.de/db/conf/fccm/fccm2003.html#KagotaniS03

  • A Formula for Performance Evaluation of Synchronizers Constructed with Cascaded CMOS D Flip-Flops

    YAMASOTO Yoshinobu, SATO Yoichiro, KAGOTANI Hiroto, OKAMOTO Takuji

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   84 ( 10 )   1484 - 1492   2001.10

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  • Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs.

    Hiroto Kagotani, Takuji Okamoto, Takashi Nanya

    Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001(ASP-DAC)   425 - 430   2001

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    DOI: 10.1145/370155.370439

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  • 2相式非同期回路における2相制御モジュールの削減法

    籠谷 裕人, 岡本 卓爾, 南谷 崇

    第60回全国大会講演論文集   2000 ( 1 )   103 - 104   2000.3

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  • A method of affine transformation for rectangular video image.

    Hiroto Kagotani, Yoichiro Sato, Yoshimichi Takahara, Takuji Okamoto

    Systems and Computers in Japan   31 ( 7 )   75 - 85   2000

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    DOI: 10.1002/(SICI)1520-684X(200007)31:7<75::AID-SCJ9>3.0.CO;2-P

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  • Systematic reducing of metastable operations in CMOS D flip-flops.

    Yoichiro Sato, Yoshinobu Yamasoto, Masanori Saito, Hiroto Kagotani, Takuji Okamoto, Masahiro Kawai

    Systems and Computers in Japan   31 ( 3 )   20 - 28   2000

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    DOI: 10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5

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  • An Formula for Performance Evaluation of CMOS Based Synchronizers

    YAMASOTO Yoshinobu, SATO Yoichiro, KAGOTANI Hiroto, OKAMOTO Takuji

    IEICE technical report. Computer systems   99 ( 6 )   97 - 104   1999.4

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    This study describes a formula for performance evaluation of synchronizers constructed with cascaded CMOS D flip-flop (DFF)s. First, it is shown that 5 parameters (clock pulse period, clock pulse duty ratio, a number of DFFs, characteristics of DFF and incidence of input changes) are classified into 3 groups (clock pulse period and a number of DFFs, clock pulse duty ratio and characteristics of DFF, incidence of input changes) which have independent effects upon the reliability of the synchronizer. Second, the formula is derived by the use of quantitative evaluation results of each groups effects on the reliability. And then the formula is examined for its validity. According to this results, by the use of the formula, the reliability of the synchronizer can be evaluated with almost 7% errors against the results obtained by the use of an existing evaluation method.

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  • Composition of Dependency Graphs for Asynchronous Circuit Synthesis based on Synchronous Circuit Scheduling

    KAGOTANI Hiroto, OKAMOTO Takuji, NANYA Takashi

    The Transactions of the Institute of Electronics,Information and Communication Engineers. A   82 ( 2 )   239 - 246   1999.2

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  • A Josephson Flip-Flop for Conflict Resolving

    SATO Yoichiro, KAWAI Masahiro, KAGOTANI Hiroto, OKAMOTO Takuji

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   82 ( 2 )   441 - 445   1999.2

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  • An Affine Transformer for Rectangular Video Image using Two Identical Functional Blocks

    TAKAHARA Yoshimichi, KAGOTANI Hiroto, SATO Yoichiro, OKAMOTO Takuji

    IEICE technical report. Computer systems   98 ( 323 )   59 - 66   1998.10

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    In this paper, we propose a construction of an affine transformer for rectangular video image based on two transform sequences that are equivalent but composed of different steps. It comprises two identical blocks connected in parallel, each of which can transform each frame in two frame periods and consists of two types of modules. As an example, we show constructions of them. Especially, we show a simple configuration of address generators which need to generate complex address sequences for switching two transform sequences. The proposed affine transformer reduces hardware volume without reducing its speed compared with the existing one.

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  • Systematic Reducing of Metastable Operation Occurred in CMOS D Flip-Flops

    SATO Yoichiro, YAMASOTO Yoshinobu, SAITO Masanori, KAGOTANI Hiroto, OKAMOTO Takuji, KAWAI Masahiro

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   81 ( 9 )   1090 - 1098   1998.9

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  • A Fast Simplex Method for Deciding shether Specified Signal Changes Occur or Not

    OHNISHI Atsushi, KAGOTANI Hiroto, SUGIYAMA Yuji

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   81 ( 4 )   417 - 427   1998.4

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  • Estimation of Malfunctions Caused by Metastable Operation in a Synchronizer

    SATO Yoichiro, YAMASOTO Yoshinobu, KAGOTANI Hiroto, OKAMOTO Takuji

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   81 ( 3 )   292 - 302   1998.3

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  • A Method of Affine Transformation for Rectangular Video Image

    KAGOTANI Hiroto, SATO Yoichiro, TAKAHARA Yoshimichi, OKAMOTO Takuji

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   81 ( 1 )   11 - 20   1998.1

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  • Composition of Dependency Graphs for Asynchronous Circuit Synthesis based on Synchronous Circuit Scheduling

    KAGOTANI Hiroto, OKAMOTO Takuji, NANYA Takashi

    Technical report of IEICE. FTS   97 ( 224 )   47 - 54   1997.8

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    In this paper, we propose a method of transforming given CDFGs into dependency graphs that can be mapped onto fast asynchronous circuits so far as fixed hardware resource constraints permit. In the method, first, an approximate scheduling of the CDFG is performed using an algorithm for synchronous circuits, then, using the result, functional units are allocated to operations so that each operation has to wait for as few other operations as possible. Next, a dependency graph is generated from the CDFG and sharing relations between operations so that consistency is not violated.

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  • An Affine Transformer for Motion Picture using Functional Modules

    KAGOTANI Hiroto, TAKAHARA Yoshimichi, ASAI Satoshi, SATO Yoichiro, OKAMOTO Takuji

    IEICE technical report. Computer systems   96 ( 231 )   47 - 54   1996.8

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    Digital motion picture can be affine-transformed by executing right-angle rotation (RR) and X-axis 1-dimensional affine transformation (XT) twice in this order. This paper describes a method for realizing RR and XT functions by an array of functional memory modules and interpolation modules at every row. Each of functional memory modules has a low speed two dimensional memory cell array of DRAM structure. They execute RRs of square sub-images and XT in parallel every frame, by the control of built-in special address generators and cooperation with interpolation modules. Optimal scale of functional memory modules is mainly decided by speed of DRAM cells.

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  • Dependency Graph Representation of Mutual Exclusion and Its Implementation Using Two-Phase Quasi-Delay-Insensitive Circuit

    KAGOTANI Hiroto, OBATA Toshinori, OKAMOTO Takuji, NANYA Takashi

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   79 ( 5 )   237 - 244   1996.5

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  • Pipelining Algorithm of Dependency Graphs for Asynchronous Processor Design

    KAGOTANI Hiroto, OKAMOTO Takuji, NANYA Takashi

    Technical report of IEICE. ICD   96 ( 20 )   9 - 16   1996.4

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    Dependency graphs that represent specifications of systems such as processors can be easily mapped into asynchronous circuits. It, however, has not been known how to derive pipelined dependency graphs systematically. In this paper, we propose an algorithm that can transform given dependency graphs representing repeated execution of operations into pipelined graphs by (1) searching for all pairs of operations that can be pipelined and (2) applying a graph transformation to paths between operations of each pair.

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  • A Fast Simplex Method of Deciding whether Specified Signal Changes Occur or Not

    OHNISHI Atsushi, KAGOTANI Hiroto, SUGIYAMA Yuji

    Technical report of IEICE. ICD   96 ( 20 )   1 - 8   1996.4

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    This paper discusses on the simplex method for deciding whether specified signal changes are occurred or not in an asynchronous circuit. It shows that the simultaneous linear inequality that represents the above condition has the property that every coefficient of the inequality is 0 or ±1, and shows that such property always holds when the inequality is converted in simplex process. Using the property, a fast simplex method is obtained by simplifying the conversion operation of inequality, and it reduces decision time to 10% or less than that of original one.

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  • Optimization of Asynchronous Processors through the Decomposition of Micro-operations

    YASUE Kazuhito, MORIZAWA Rafael K., KAGOTANI Hiroto, NANYA Takashi

    Technical report of IEICE. ICD   96 ( 20 )   17 - 23   1996.4

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    This paper presents a method that speeds up a quasi-delay-insensitive processor design obtained using the dependency graph (DG) method. In the DG method, an operation involving register transfers was called micro-operation-the most basic type of operation. In this method, an operation is divided into two parts:one, where values are read from registers and fed into combinational logic, and another where the results of an operation are written into a source register. Each basic part composes an explicit dependency relation between read/write operations, and are considered in the parallelization of a DG. Also, the resulting circuit's size does not differ using both methods.

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  • Parallelization of Dependency Graphs for High-Speed Quasi-Delay-Insensitive Processor Design

    Kagotani Hiroto, Sugimoto Masahiko, Okamoto Takuji, Nanya Takashi

    Proceedings of the IEICE General Conference   1996 ( 1 )   86 - 86   1996.3

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  • Performance enhancement of two-phase quasi-delay-insensitive circuits.

    Hiroto Kagotani, Takashi Nanya

    Systems and Computers in Japan   27 ( 5 )   39 - 46   1996

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    DOI: 10.1002/scj.4690270504

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  • A Multiwindow Generation by Combination of Software and Hardware Methods

    TSUNASHIMA Nobuaki, SATO Yoichiro, YOKOHIRA Tokumi, KAGOTANI Hiroto, OKAMOTO Takuji

    IEICE technical report. Computer systems   95 ( 210 )   9 - 16   1995.8

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    This paper proposes a multiwindow generation method which can smoothly execute successive window operations such as move, resize and scroll, and requires a small amount of hardware. An image of a window which is a target of the successive operations is stored in an image memory, images of the other windows are stored in another image memory according to the principle of the software method, and a multiwindow image is generated according to the principle of the hardware method. The time for changing a window which is a target of successive operations is reduced by DMA transfer between two memories which decreases the amount of image transferred into them by CPU.

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  • Dependency Graph Representation of Mutual Exclusion and its Implementation using Two-Phase Quasi-Delay-Insensitive Circuit

    Kagotani Hiroto, Obata Toshinori, Okamoto Takuji, Nanya Takashi

    Technical report of IEICE. FTS   95 ( 87 )   57 - 64   1995.6

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    Dependency Graph allows designers to describe systems including conditional branches, loops, and complex concurrent operations, etc. Systems described in Dependency Graph can be easily translated into two-phase quasi-delay-insensitive circuits. It has, however, no capability to represent mutual exclusion functions realized by arbiters. In this paper, we first propose addition of a new type of nodes that represents mutual exclusion as an extension to the Dependency Graph. Next, we describe circuit blocks mapped from the new nodes, that consists of asynchronous arbiter and Q-elements, and redefine conflict relations that are used for enhancing performance of circuits. Finally, two examples are described.

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  • On Performance Enhancement of Two-Phase Quasi-Delay-Insensitive Circuits

    KAGOTANI Hiroto, MANYA Takashi

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   78 ( 4 )   416 - 423   1995.4

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  • A Translation Method of Arbitration from Dependency Graphs into Two-phase Quasi-Delay Insensitive Circuits

    Kagotani Hiroto, Obata Toshinori, Okamoto Takuji, Nanya Takashi

    Proceedings of the IEICE General Conference   1995 ( 1 )   283 - 283   1995.3

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  • Synthesis of two-phase quasi-delay-insensitive circuits from dependency graphs.

    Hiroto Kagotani, Takashi Nanya

    Systems and Computers in Japan   26 ( 4 )   11 - 19   1995

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    DOI: 10.1002/scj.4690260402

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  • Synthesis of Two-Phase Quasi-Delay-Insensitive Circuits from Dependency Graphs

    KAGOTANI Hiroto, NANYA Takashi

    The Transactions of the Institute of Electronics,Information and Communication Engineers.   77 ( 8 )   548 - 556   1994.8

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  • Design and Evaluation of Asynchronous Processor TITAC

    Ueno Yoichiro, Takamura Akihiro, Ozawa Kunihiko, Kagotani Hiroto, Kuwako Masashi, Nanya Takashi

    IEICE technical report. Computer systems   95 - 102   1994

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    This paper describes the design,implementation,and evaluation of TITAC,an asynchronous generalpurpose microprocessor based on the delay-insensitive model with isochronic forks.A main purpose of the TITAC is to demonstrate that a design methodology is readily available to realize fully asynchronous VLSI systems that work in practice.We also aimed to evaluate the delay-insensitivity and the power consumption of TITAC.One of the most significant features of TITAC architecture lies in the control section which include two different types of controllers,i.e.hardwired-logic control and microprogram control.

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  • TITAC: Design of A Quasi-Delay-Insensitive Microprocessor.

    Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura

    IEEE Des. Test Comput.   11 ( 2 )   50 - 63   1994

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    DOI: 10.1109/54.282445

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  • On Handshake Control for 2-phase Delay-insensitive Processors

    Kagotani Hiroto, Nanya Takashi

    Technical report of IEICE. FTS   93 ( 303 )   73 - 80   1993.10

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    In 2-phase delay-insensitive circuits,approximately a half of the processing time is wasted by the second phase called idle phase that does not perform any actual operation.We propose a handshake controller that enables next operations to start without waiting for the completion of the idle phase so that we can reduce the processing time.Replacing a conventional control module simply with the new module is not always allowed because of the dependencies.We solved this problem by using additional AND gates. Logic simulation shows that this method can improve the throughput of circuits without increasing the number of the gates.

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  • Synthesis System of Asynchronous Circuits using Dependency Graph

    46 ( 0 )   135 - 136   1993.3

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  • Synthesis System of Asynchronous Control Circuits based on Process Description

    44 ( 0 )   159 - 160   1992.2

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  • A Method for Automatic Synthesis of Control circuits in Asynchronous Processors

    42 ( 0 )   144 - 145   1991.2

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Research Projects

  • Realization of secure and reliable communication in a remote control type / autonomous mobile system in the IoT era

    Grant number:16H01723  2016.04 - 2019.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)  Grant-in-Aid for Scientific Research (A)

    Nogami Yasuyuki

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    Grant amount:\39390000 ( Direct expense: \30300000 、 Indirect expense:\9090000 )

    In this research, using a specific drive system such as an electric vehicle and robot capable of autonomous driving and remote control, the advanced security technology (data authentication, device authentication, secure key update) we have clarified the security level that is realized without any problems by verifying how much the real-time performance is affected. Specifically, for the CAN system, data authentication with message authentication code that is generated by AES, random number generator, and lightweight encryption has been implemented. Then, side-channel attack has been demonstrated experimentally, key update function as the countermeasure using elliptic pairing-based cryptography has been also implemented. Their real-time processing could be realized.

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  • Design method of optimized asynchronous pipelines using control-flow graphs

    Grant number:24500065  2012.04 - 2016.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)  Grant-in-Aid for Scientific Research (C)

    KAGOTANI Hiroto

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    Grant amount:\4940000 ( Direct expense: \3800000 、 Indirect expense:\1140000 )

    Pipelines are effective for improving performance of asynchronous circuits, which are expected to reduce power consumption and electromagnetic radiation by eliminating clock signals. Although pipelining using control-flow graphs are effective for reducing circuit size, there remains some redundant circuitry increasing the control circuits. In this research, an algorithm for simplifying pipelined control-flow graphs by eliminating redundant nodes. Also, an improved algorithm reduces computational complexity for the simplification.

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  • 非同期式プロセッサ設計における演算器資源割当ての最適化法

    Grant number:11780225  1999 - 2000

    日本学術振興会  科学研究費助成事業 奨励研究(A)  奨励研究(A)

    籠谷 裕人

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    Grant amount:\2300000 ( Direct expense: \2300000 )

    本研究では,与えられた仕様に基づき、使用可能な演算器数(すなわちコスト)に制約を与えた上で、極力高速な非同期式プロセッサが実現できるような静的演算器割当て法を得ることを目的に、昨年度に行った既存アルゴリズムの制約緩和に引き続いて、本年度は最適化法の局所性緩和を行った。
    従来の演算器割当て最適化法では、プロセッサの実行ステップごとに演算器の割当てを行う際、そのステップの直前の演算との依存関係にのみ着目して割当ての最適化を図った。しかし、各演算の実行時間が一定の確率分布にしたがって変動するという仮定下にある非同期式プロセッサでは、同じ実行ステップであっても,演算開始時刻の同期が取られるわけではない。このため、次ステップへの影響の大きい演算ほど、早く利用可能となる可能性の高い演算器を割り当てることが有効である。
    そこで、本研究では、このような割当てを導出する以下のようなアルゴリズムを開発した。まず、ステップi-1の割当てが完了するごとに、実行時間の確率分布を用いてそのステップまでの各演算の平均完了時刻を算出する。次に、ステップiの各演算について、それ以降のステップへの影響度として、ステップi+1の演算のうち、依存性のある演算の個数を求める。そして、ステップiの演算集合と演算器集合を結ぶ完全2部グラフを作成して、これらの指標をもとに各枝に重みを割り振り、最大重みマッチング問題を解くことによって、ステップiの割当てを決定する。
    この割当てアルゴリズムをいくつかのベンチマークに対して適用してみた。従来法では、ランダムな割当てを10000回試行した場合に、それよりよい割当てが10%前後得られていたのに対し、本方法では、それを上回るランダムな割当てはたかだか1-2個しか存在せず、繰り返しの試行をすることなく最適に近い割当てが得られ、効果が大きいことがわかった。

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  • パイプライン化された依存性グラフからの高速非同期式プロセッサの生成

    Grant number:09780288  1997 - 1998

    日本学術振興会  科学研究費助成事業 奨励研究(A)  奨励研究(A)

    籠谷 裕人

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    Grant amount:\1600000 ( Direct expense: \1600000 )

    本研究では、パイプライン動作を表現した依存性グラフ(プロセッサ内で実行される部分処理(基本操作)間の実行順序や条件分岐などを記述した有向グラフ)から、効率的に動作する2相非同期式回路を生成する手段を得ることを目的とし、その基本アルゴリズムを開発した。
    まず、バイプライン動作を表す依存性グラフを、より効率的に作成するため、以前に開発した依存性グラフのパイプライン化アルゴリズムを抜本的に改良した。
    次に、以上の研究成果を用いてより一般的な依存性グラフを用いて試験した結果、前年度に開発したアルゴリズムでは、一定の条件を満たしたクラスの依存性グラフにしか適用できないことが判明した。そのため、やはり、条件分岐を含まない場合に限定し、アルゴリズムを改良した。改良したアルゴリズムでは、バイプライン動作を表現した依存性グラフが、動作ステージ間でループ構造を構成する点に着目し、これらのループ構造ごとに、ループの最初に実行される基本操作と最後に実行される基本操作の相を反転させるように、グラフを構成し直す。これによって、並列に動作すべき基本操作対において、稼動相どうしが並列に動作できる2相依存性グラフが生成できるようになった。本アルゴリズムが、上記前提のもとで正当であることについても、ループ構造ごとの繰り返し適用である点に着目し、そのループ構造の複雑度に関する帰納法を適用することで証明可能となった。
    本方法では、条件分岐を含まない場合に関しては、その目的を達成したが、条件分岐を含む場合のアルゴリズムは未完成である。この点は、条件分岐を含む依存性グラフの構造を、上述のように一般的な構成要素に分解することによって可能となると考えられる。

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  • 非同期式パイプライン型プロセッサの自動合成に関する研究

    Grant number:08780287  1996

    日本学術振興会  科学研究費助成事業 奨励研究(A)  奨励研究(A)

    籠谷 裕人

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    Grant amount:\900000 ( Direct expense: \900000 )

    本研究では、パイプライン機構を備えた非同期式プロセッサの自動合成手法の開発を目的とし、依存性グラフ(プロセッサ内で実行される部分処理(基本操作)間の実行順序や条件分岐などを記述した有向グラフ)のパイプライン化手法を確立した。
    パイプラインとは、何度も繰り返される処理内の、繰り返し間にまたがる基本操作間の並列実行であると一般化できる。そこで、依存性グラフにおいて、最後に実行される基本操作と、次の繰り返し時に最初に実行される基本操作との間に依存関係がなければ、これらが並列に実行できるように依存性グラフの一部を変形すればよい。この変形は、二つの基本操作間の有向パスを複製し、各基本操作を異なるパスに配置することによって行われる。
    しかしこのとき、他の部分処理との依存関係から、変形を行っても並列には実行されない場合が存在し、その結果、与えられるグラフによっては、何度でも変形が可能となって手続きが停止しないことがあることが判明した。そこで、ある変形が実際に並列実行に有効かどうかを判定する手法を考案し、有効な場合のみ変形を適用するという条件を加えた。そして、以上のパイプライン化手続きが正当であることが証明された。
    本研究の成果により、パイプライン化された非同期式プロセッサが容易に設計できるようになると考えられる。
    本手法においては、極端な遅延も存在すると仮定しており、ほとんど同時に動作しないのに別々のハードウェアを割り当てなければならない場合があるなど、ハードウェア量が増大し得るという問題が残る。従って、今後、遅延の仮定に制約を設け、ハードウェア量と動作速度とのトレードオフを考慮した、スケジューリング法を確立していくことが必要となる。

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  • Study on Implementation and Evaluation of High-performance Asynchronous Microprocessor

    Grant number:07558036  1995 - 1996

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)  Grant-in-Aid for Scientific Research (A)

    NANYA Takashi, FUKUMA Masao, KAGOTANI Hiroto, UENO Yoichiro, YONEDA Tomohiro, FUJIWARA Eiji

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    Grant amount:\8700000 ( Direct expense: \8700000 )

    A 32-bit asynchronous microprocessor, whose architecture was borrowed from the MIPS R2000 processor, has been fabricated using 3 layr metal, 0.5 micron rule CMOS standard cell technology, integrating 496,367 MOS transistors and 8.6K Byte memory macro in 12.5 mm x 12.5mm. The processor chip works correctly with its power supply voltage being varied through the range from 1.5V to 6.0V and the temperature of its package surface being heated up to about 85 degrees Celsius by hair dryer and cooled down with liquid nitrogen, and achieves 52 VAX MIPS using the Dhrystone V2.1 benchmark with a power consumption of 2W at 3.3 V for room temperature. A significant feature of the design is the introduction of a new delay model, called the Scalable-Delay-Insensitive (SDI) model, which provides with a reasonable approach to dependable and high-performance asynchronous VLSI system design. the delay-insensitivity and the high-performance that the processor has been proved to achieve demonstrate that the asynchronous event-driven approach is very promising and encouraging for high-preformance VLSI system design with future device technologies.

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