Publishing type：Research paper (international conference proceedings)  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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Publishing type：Research paper (international conference proceedings)  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

DOI： 10.1109/ISEMC.2014.6899067

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

In our previous study, we identified an internal equivalent current source representing the internal switching current of a cryptographic IC that occurred as the IC operated an encryption operation. Since the internal switching current is the source of information leakage, the internal equivalent current source is expected to be able to be applied to evaluate cryptographic ICs in security of side-channel attack. In this study, we investigated the internal equivalent current source with regard to its behavior as the source of information leakage. The investigation revealed that variance of the switching current varied temporally in a round operation and that the AES circuit with a hiding countermeasure provided information leakage at the moment when the variance was smaller than that in the remaining time period. This suggested that cryptographic circuits can be analyzed of their behavior as the information leakage source according to the internal equivalent current source.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been proposed. However, the size of circuits synthesized by this algorithm tends to be large because it assumes QDI delay model. Yoshitake proposed a reduction method using a characteristic of a maximum delay loop in a dependency graph under SDI delay model. In this paper, we improve the method by extending the application range to dependency graphs that have multiple maximum delay loop.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Recently, studies on implementation of cryptographical algorithms on GPUs are widely conducted as GPGPU development environment provides easy access to GPUs for non-graphics programming. In this paper, we implement cyclic vector multiplication algorithm, or an efficient multiplication algorithm on extension fields, that will accelerate pairing cryptography. Since we adopt 256-bit characteristic for the base fields, we also implement Montgomery multiplication for 256-bit operands on GPU. As the result of implementation on NVIDIA GeForce GTX680, it is over 10 times slower than implementation on Core i7 3970X.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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Language：Japanese   Publisher：The Japan Institute of Electronics Packaging  

DOI： 10.11486/ejisso.28.0_63

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

In this paper, we propose integration of multimodal features using conditional random fields (CRFs) for the segmentation of broadcast news stories. We study story boundary cues from lexical, audio and video modalities, where lexical features consist of lexical similarity, chain strength and overall cohesiveness; acoustic features involve pause duration, pitch, speaker change and audio event type; and visual features contain shot boundaries, anchor faces and news title captions. These features are extracted in a sequence of boundary candidate positions in the broadcast news. A linear-chain CRF is used to detect each candidate as boundary/non-boundary tags based on the multimodal features. Important interlabel relations and contextual feature information are effectively captured by the sequential learning framework of CRFs. Story segmentation experiments show that the CRF approach outperforms other popular classifiers, including decision trees (DTs), Bayesian networks (BNs), naive Bayesian classifiers (NBs), multilayer perception (MLP), support vector machines (SVMs) and maximum entropy (ME) classifiers.

DOI： 10.1587/transinf.E95.D.1206

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

The authors have proposed a cyclic vector multiplication algorithm abbreviated as CVMA that is flexible to the parameters of extension field, that is extension degree and charasteristic. For the hardware implementation of CVMA, the authors have improved the double loop structure of CVMA to a single loop one, and it has been presented at SITA2010. However, it has a problem that it needs a lot of memory. Thus, this paper proposes a method to save the memory use of the single loop version of CVMA.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Cyclic vector multiplication algorithm (CVMA) has been originally proposed as a vector multiplication algorithm for elements in a certain extension field. Recently, Granger et al. have proposed the primes called Minimal Redundancy Cyclotomic Primes (MRCPs) and they have applied CVMA for the modular multiplications with MRCPs. This paper shows that several detailed classes of MRCPs and their customized multiplication algorithms.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Strict software asset management and legal use is part of corporate social responsibility. In our laboratory, we investigate the software asset periodically in order to guarantee legal use of software license. This investigation procedures, however, are likely to cause mistakes and omissions, and require the administrator and members a long time. In order to solve these problems, we design and develop a Web application system for software license asset management that can improve the efficiency of investigation. On the system, members log in to the server and enter information about their PCs and software via their Web browsers. Users can submit the information of their connecting PCs by just one click without manual investigation. As the result of a questionnaire, the system was evaluated as quite useful. Also, further improvement of the user interface was requested.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Recently, the virtualization technology has been often used to construct servers due to the efficiency of the computer resource utilization and the easiness of the system extension. The method of composing cluster systems using the virtualized servers has also been proposed. In this paper, we propose a safe and scalable Web server system using the virtualization technology. In this system, the SSL authentication protocol is adopted to authenticate the server hosts and the encrypted data communications. Besides, the system management tool is incorporated for the simple system management by realizing the automatic update functions of the system softwares such as the operating system and the Web server. We implemented the proposed system using Puppet as the system management tool, Ruby SNMP as the system management library, and Xen as the virtualization machine monitor. The experimental result using our implementation confirms the short time for the Web server extension.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

The Virtual Network Computing (VNC) has problems such as network load increase and access control for practical use in multi-client environment. We develop a VNC Proxy to solve those problems. In this paper, we evaluate load dispersion performance of the VNC Proxy through experimental results. We arrange proxies in consideration of the network toporogy and measure the network load and delay in the experiment. As a result, network load were dispersed by the VNC Proxy without critical delay.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

In this paper, we propose a method for synthesizing pipelines for asynchronous processor design using a kind of control flow graphs (dependency graphs). We first represent a specification given in CHP form as a secuential dependency graph and convert it into a set of small dependency graphs (minimal dependency graphs) each of which represents execution order of a dependent pair of micro-operations. Next, we synthesize a pipelined dependency graph from the minimal dependency graphs. Our method can implement asynchronous pipeline datapaths with much less registers than Teifel's method.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

The Virtual Network Computing (VNC) is a useful network application to let a user operate the desktop display of a remote PC on his/her local PC. However, VNC has two problems for practical use in multi-client environment. One is the increase of network loads when a number of clients are connecting to a VNC server. Another is the lack of capability of the access control of each user by the administrator of the VNC server. The more clients connect VNC server, the more serious these problems become. In this paper, we present a VNC proxy to solve these problems, where it reduces the network loads by dispersing the roles of the server into multiple mirrors, and enables the VNC administrator to control the access right by each client.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper describes a method of fast affine transformation for video images. A DSP with parallel datapaths and a single local memory for a data buffer is used. The affine transformation is carried out by decomposing it into two consecutive one dimensional processes; one for horizontal direction and the other for vertical. In order to speed up the transformation, a main memory (MM) and the local memory (LM) are structured to a ring buffer for frames of the video image and to a ring buffer for parts of a frame, respectively. It is desirable to select the number of datapaths so that the time required for transmission of a part of a frame between MM and LM becomes nearly equal to that for its interpolation by datapaths. Experimental results showed that the transformation speed in the proposed method was about five times faster than usual ones.

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Publishing type：Research paper (scientific journal)  

DOI： 10.1002/scj.20136

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：SCRIPTA TECHNICA-JOHN WILEY & SONS  

In this paper, the authors propose a multiwindow system that can smoothly execute window operations such as moving, resizing, or scrolling by using a combination of a drawing-time composition method and display-time composition method. Memory for storing the image of the window for which the window operation is to be performed (operation target window) and memory for storing a composite image of all other windows generated by a drawing-time composition method are both established in this system. The image that is displayed on the actual screen is obtained by using a display-time composition method to combine images that were read in parallel from both of these memories to generate the multiwindow image. The authors performed a trial experiment using a 640-pixel by 480-pixel display device to verify that no flicker appeared on the display screen when updating the operation target window. From the results of this trial experiment, they suggested that smooth window operations probably can also be executed for a 1280-pixel by 1024-pixel display device. (C) 2004 Wiley Periodicals, Inc.

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Language：Japanese   Publisher：Information Processing Society of Japan (IPSJ)  

We propose a synthesis method of control circuits for pipelined asynchronous processors from specifications given as a dependency graph and dependencies. This method gives control circuits by connecting handshaking control modules corresponding to graph nodes according to the edges of the graph and dependencies. These control modules are designed to achieve efficient pipelines by parallelizing working and idle phases, which are composing a micro-operation. This method can synthesize smaller hardware than a conventional one.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

We propose a synthesis method of control circuits for pipelined asynchronous processors from specifications given as a dependency graph and dependencies. This method gives control circuits by connecting handshaking control modules corresponding to graph nodes according to the edges of the graph and dependencies. These control modules are designed to achieve efficient pipelines by parallelizing working and idle phases, which are composing a micro-operation. This method can synthesize smaller hardware than a conventional one.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

We propose a synthesis method for pipelines that improve throughput of asynchronous processors. In this paper, we focus on restricted specifications that do not include conditional branches. Given a specification as a set of dependencies between micro-operations executed in a target processor, the proposed algorithm can synthesize a pipelined Dependency Graph representing execution sequence of micro-operations in the processor. We focus on restricted specifications excluding conditional branches.

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Publishing type：Research paper (scientific journal)  

DOI： 10.1002/scj.10709

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Other Link： http://search.jamas.or.jp/link/ui/2004070791

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

In this paper, coronary hemodynamics of the beating heart is analyzed by a simulation study. The auto-regulation is modeled by changing the elastance values at arterioles. The auto-regulation subsystem is incorporated into our previous medel. Blood flows and their waveforms in the arterioles are analyzed transmurally, and the effects of the auto-regulation on intramyocardial arterial now are studied by changing pressure amplitude.

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Other Link： http://search.jamas.or.jp/link/ui/2003184015

Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

DOI： 10.1109/FPGA.2003.1227248

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Other Link： https://dblp.uni-trier.de/db/conf/fccm/fccm2003.html#KagotaniS03

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Publishing type：Research paper (international conference proceedings)   Publisher：ACM  

DOI： 10.1145/370155.370439

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Other Link： https://dblp.uni-trier.de/db/conf/aspdac/aspdac2001.html#KagotaniON01

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DOI： 10.1002/(SICI)1520-684X(200007)31:7<75::AID-SCJ9>3.0.CO;2-P

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DOI： 10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This study describes a formula for performance evaluation of synchronizers constructed with cascaded CMOS D flip-flop (DFF)s. First, it is shown that 5 parameters (clock pulse period, clock pulse duty ratio, a number of DFFs, characteristics of DFF and incidence of input changes) are classified into 3 groups (clock pulse period and a number of DFFs, clock pulse duty ratio and characteristics of DFF, incidence of input changes) which have independent effects upon the reliability of the synchronizer. Second, the formula is derived by the use of quantitative evaluation results of each groups effects on the reliability. And then the formula is examined for its validity. According to this results, by the use of the formula, the reliability of the synchronizer can be evaluated with almost 7% errors against the results obtained by the use of an existing evaluation method.

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In this paper, we propose a construction of an affine transformer for rectangular video image based on two transform sequences that are equivalent but composed of different steps. It comprises two identical blocks connected in parallel, each of which can transform each frame in two frame periods and consists of two types of modules. As an example, we show constructions of them. Especially, we show a simple configuration of address generators which need to generate complex address sequences for switching two transform sequences. The proposed affine transformer reduces hardware volume without reducing its speed compared with the existing one.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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In this paper, we propose a method of transforming given CDFGs into dependency graphs that can be mapped onto fast asynchronous circuits so far as fixed hardware resource constraints permit. In the method, first, an approximate scheduling of the CDFG is performed using an algorithm for synchronous circuits, then, using the result, functional units are allocated to operations so that each operation has to wait for as few other operations as possible. Next, a dependency graph is generated from the CDFG and sharing relations between operations so that consistency is not violated.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Digital motion picture can be affine-transformed by executing right-angle rotation (RR) and X-axis 1-dimensional affine transformation (XT) twice in this order. This paper describes a method for realizing RR and XT functions by an array of functional memory modules and interpolation modules at every row. Each of functional memory modules has a low speed two dimensional memory cell array of DRAM structure. They execute RRs of square sub-images and XT in parallel every frame, by the control of built-in special address generators and cooperation with interpolation modules. Optimal scale of functional memory modules is mainly decided by speed of DRAM cells.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Dependency graphs that represent specifications of systems such as processors can be easily mapped into asynchronous circuits. It, however, has not been known how to derive pipelined dependency graphs systematically. In this paper, we propose an algorithm that can transform given dependency graphs representing repeated execution of operations into pipelined graphs by (1) searching for all pairs of operations that can be pipelined and (2) applying a graph transformation to paths between operations of each pair.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper discusses on the simplex method for deciding whether specified signal changes are occurred or not in an asynchronous circuit. It shows that the simultaneous linear inequality that represents the above condition has the property that every coefficient of the inequality is 0 or ±1, and shows that such property always holds when the inequality is converted in simplex process. Using the property, a fast simplex method is obtained by simplifying the conversion operation of inequality, and it reduces decision time to 10% or less than that of original one.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper presents a method that speeds up a quasi-delay-insensitive processor design obtained using the dependency graph (DG) method. In the DG method, an operation involving register transfers was called micro-operation-the most basic type of operation. In this method, an operation is divided into two parts:one, where values are read from registers and fed into combinational logic, and another where the results of an operation are written into a source register. Each basic part composes an explicit dependency relation between read/write operations, and are considered in the parallelization of a DG. Also, the resulting circuit's size does not differ using both methods.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Publishing type：Research paper (scientific journal)  

DOI： 10.1002/scj.4690270504

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper proposes a multiwindow generation method which can smoothly execute successive window operations such as move, resize and scroll, and requires a small amount of hardware. An image of a window which is a target of the successive operations is stored in an image memory, images of the other windows are stored in another image memory according to the principle of the software method, and a multiwindow image is generated according to the principle of the hardware method. The time for changing a window which is a target of successive operations is reduced by DMA transfer between two memories which decreases the amount of image transferred into them by CPU.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Dependency Graph allows designers to describe systems including conditional branches, loops, and complex concurrent operations, etc. Systems described in Dependency Graph can be easily translated into two-phase quasi-delay-insensitive circuits. It has, however, no capability to represent mutual exclusion functions realized by arbiters. In this paper, we first propose addition of a new type of nodes that represents mutual exclusion as an extension to the Dependency Graph. Next, we describe circuit blocks mapped from the new nodes, that consists of asynchronous arbiter and Q-elements, and redefine conflict relations that are used for enhancing performance of circuits. Finally, two examples are described.

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Publishing type：Research paper (scientific journal)  

DOI： 10.1002/scj.4690260402

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper describes the design,implementation,and evaluation of TITAC,an asynchronous generalpurpose microprocessor based on the delay-insensitive model with isochronic forks.A main purpose of the TITAC is to demonstrate that a design methodology is readily available to realize fully asynchronous VLSI systems that work in practice.We also aimed to evaluate the delay-insensitivity and the power consumption of TITAC.One of the most significant features of TITAC architecture lies in the control section which include two different types of controllers,i.e.hardwired-logic control and microprogram control.

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Publishing type：Research paper (scientific journal)  

DOI： 10.1109/54.282445

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

In 2-phase delay-insensitive circuits,approximately a half of the processing time is wasted by the second phase called idle phase that does not perform any actual operation.We propose a handshake controller that enables next operations to start without waiting for the completion of the idle phase so that we can reduce the processing time.Replacing a conventional control module simply with the new module is not always allowed because of the dependencies.We solved this problem by using additional AND gates. Logic simulation shows that this method can improve the throughput of circuits without increasing the number of the gates.

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