Updated on 2025/10/23

写真a

 
Minoru Watanabe
 
Organization
Faculty of Environmental, Life, Natural Science and Technology Professor
Position
Professor
External link

Degree

  • 博士(情報工学) ( 2005.9   Kyushu Institute of Technology )

Research Areas

  • Informatics / Computer system  / リコンフィギャラブルシステム、FPGA,光再構成型ゲートアレイ

Education

  • Shizuoka University   工学研究科   光電機械工学専攻

    - 1994

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    Country: Japan

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  • Shizuoka University   工学部   光電機械工学科

    - 1992

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    Country: Japan

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Research History

  • 岡山大学 環境生命自然科学学域   教授

    2023.4

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  • Okayama University   Faculty of Engineering Department of Information Technology   Professor

    2021.4 - 2023.3

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  • Shizuoka University   創造科学技術大学院 ナノビジョンサイエンス部門   Associate Professor

    2012.4 - 2021.3

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  • Shizuoka University   Faculty of Engineering Department of Electrical and Electronic Engineering   Associate Professor

    2007.4 - 2021.3

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  • Kyushu Institute of Technology   情報工学部 システム創成情報工学科

    2005.4 - 2007.3

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  • Kyushu Institute of Technology   情報工学部 システム創成情報工学科   Research Assistant

    2004.4 - 2005.3

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  • Kyushu Institute of Technology   情報工学部 制御システム工学科   Research Assistant

    2000.1 - 2004.3

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  • 日産自動車株式会社

    1994.4 - 1999.12

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Professional Memberships

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Committee Memberships

  • International Conference on Field-Programmable Technology   Program committee  

    2024.6 - 2024.12   

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  • IEEE 43rd International Conference on Consumer Electronics   Special Session Chair  

    2024.2 - 2025.1   

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  • IEEE 43rd International Conference on Consumer Electronics   Design Competition Chair  

    2024.2 - 2025.1   

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  • International Conference on Field-Programmable Technology   Program committee  

    2023.6 - 2023.9   

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  • リコンフィギャラブルシステム研究専門委員会   専門委員  

    2023.4 - 2024.3   

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  • ISoIRS 2023   Program Committee  

    2023.4 - 2023.11   

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  • MWSCAS   Program Committee  

    2023.4 - 2023.5   

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  • International Conference on Consumer Electronics   Design Competitioin Chair  

    2023.2 - 2024.1   

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    Committee type:Academic society

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  • International Conference on Consumer Electronics   Special Session Chair  

    2023.2 - 2024.1   

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  • リコンフィギャラブルシステム研究専門委員会   専門委員  

    2022.4 - 2023.3   

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  • リコンフィギャラブルシステム研究会 FPGAデザインコンテスト   実行委員長  

    2022.4 - 2022.10   

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  • International Conference on Field-Programmable Technology   Design Competitioin Chair  

    2021.12 - 2022.12   

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  • リコンフィギャラブルシステム研究専門委員会   専門委員  

    2021.4 - 2022.3   

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  • International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   Program Committee  

    2021.4 - 2021.6   

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  • リコンフィギャラブルシステム研究会   FPGAデザインコンテスト 実行委員長  

    2021.3 - 2021.10   

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  • International Conference on Field-Programmable Technology   Design Competitioin Chair  

    2020.12 - 2021.12   

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  • 電子情報通信学会 東海支部   学生委員  

    2020.4 - 2021.3   

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Papers

  • Compact and robust holographic memory for optically reconfigurable gate arrays Reviewed

    Virgile J., Prat Balagna, Minoru Watanabe, Nobuya Watanabe

    IEEE Electrical Design of Advanced Packaging and Systems   2025.12

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

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  • A recovery method for radiation degradation factors on an optically reconfigurable gate array VLSI Reviewed

    Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe

    IEEE International Integrated Reliability Workshop   2025.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

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  • Holographic memory formed by three laser sources with different wavelengths for application to optical reconfiguration Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    Optical Review   32 ( 3 )   546 - 556   2025.6

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:Springer Science and Business Media LLC  

    DOI: 10.1007/s10043-025-00979-8

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    Other Link: https://link.springer.com/article/10.1007/s10043-025-00979-8/fulltext.html

  • Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI Reviewed

    Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe

    2025 IEEE International Conference on Consumer Electronics (ICCE)   1 - 3   2025.1

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/icce63647.2025.10929849

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  • Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA Reviewed

    Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

    2025 IEEE International Conference on Consumer Electronics (ICCE)   1 - 4   2025.1

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/icce63647.2025.10929881

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  • Implementation of Mono Instruction Set Computer with Small Register Files Reviewed

    Soma Imai, Minoru Watanabe, Nobuya Watanabe

    2025 IEEE International Conference on Consumer Electronics (ICCE)   1 - 3   2025.1

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/icce63647.2025.10929872

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  • Fast-Neutron Soft-Error Tolerance of a Radiation-Hardened Repairable Field Programmable Gate Array Reviewed

    Minoru Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shingo Tamaki, Isao Murata, Sachie Kusaka

    IEEE International Conference on Consumer Electronics   2025.1

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  • Evaluation of a Wafer-Scale VLSI Using Programmable Architecture Reviewed

    Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

    IEEE International Conference on Consumer Electronics   2025.1

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  • Radiation-Hardened Triple Modular Redundant Serial Communication System Using Triple Communication Lines Reviewed

    Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

    IEEE International Conference on Consumer Electronics   2025.1

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  • Development of a Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Arrays Reviewed

    Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe

    IEEE International Conference on Consumer Electronics   2025.1

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  • Triple Modular Redundancy Logic Design from High-Level Hardware Description Reviewed

    Nobuya Watanabe, Minoru Watanabe

    IEEE International Conference on Consumer Electronics   2025.1

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  • Prediction of Fuel Debris Location in Fukushima Nuclear Power Plant using Machine Learning Reviewed International coauthorship

    Saed Alrawash, Matthew F. Hale, Barry Lennox, Malcolm J. Joyce, Andrew West, Minoru Watanabe, Zhongming Zhang, Michael D. Aspinall

    EPJ Web of Conferences   302   17004 - 17004   2024.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:EDP Sciences  

    Accurate fuel debris location is crucial part of the decommissioning of the Fukushima Nuclear Power plants. Conventional methods face challenges due to extreme radiation and complex structure of the materials involved. In this study, we propose a novel approach utilising neutron detection and machine learning to estimate fuel material location. Geant4 simulations and pythonTM scripts have been used to generate a comprehensive dataset to train a machine learning model using MATLAB’s regression learner. A Gaussian Process Regression model was chosen for training and prediction. The results show excellent prediction performance to estimate the corium thickness effectively and to locate the nuclear fuel material with a mean square error (MSE) of 0.01. By combining the machine learning with nuclear simulation codes, this promises to enhance the nuclear decommissioning efforts to retrieve nuclear fuel debris.

    DOI: 10.1051/epjconf/202430217004

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  • OPTICALLY RECONFIGURED GATE ARRAY VLSI WITH A TRIPLE-MODULAR REDUNDANT OPTICAL CONFIGURATION CIRCUIT Reviewed

    Kiyoto Yonechi, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • REALIZATION OF A HUGE-SCALE RADIATION-HARDENED OPTICALLY RECONFIGURABLE GATE ARRAY VLSI Reviewed

    Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024ABLE GATE ARRAY VLSI   1 - 4   2024.10

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  • IMPLEMENTATION OF A MONO INSTRUCTION SET COMPUTER ON A RADIATION-HARDENED OPTICALLY RECONFIGURABLE GATE ARRAY Reviewed

    Soma Imai, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • Formation of holographic memory using laser combiner consisting of three laser sources with different wavelength for optical reconfiguration Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    International Symposium on Imaging, Sensing, and Optical Memory 2024   59 - 60   2024.10

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  • TRIPPLE MODULAR REDUNDANT RISC-V PROCESSOR ON A CYCLONE FPGA Reviewed

    Masato Isobe, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • A 4-BIT COUNTER IMPLEMENTATION ON A REPAIRABLE FPGA Reviewed

    Ryota Hosoya, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • A RING OSCILLATOR IMPLEMENTATION ONTO AN OPTICALLY RECONFIGURABLE GATE ARRAY VLSI Reviewed

    Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • Clock distribution exploiting switching matrices on an optically reconfigurable gate array Reviewed

    Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • Triple modular redundant serial communication circuit used in a severe radiation environment Reviewed

    Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   1 - 4   2024.10

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  • Exploring the Impact of Heterogeneous Cm-244 Distribution on Neutron Flux within Fukushima Daiichi Fuel Debris Invited

    Saed Alrawash, Matthew Hale, Barry Lennox, Malcolm Joyce, Andrew Wes, Minoru Watanabe, Japa, Zhongming Zhang, Michael Aspinall

    International Topical Workshop on Fukushima-Daiichi Decommissioning Research 2024   2024.10

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

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  • Design and development of a radiation-hard robot for the RHINO project Invited

    Matthew Frederick Hale, Andrew Wes, Saed Alrawash, Minoru Watanabe, Malcolm Joyce, Michael Aspinall, Barry Lennox

    2024.10

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  • Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI Reviewed

    Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

    IEEE International System-on-Chip Conference   1 - 6   2024.9

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  • Radiation-hardened programmable two-phase clock generator Reviewed

    Minoru Watanabe

    2024 International Electronics Symposium (IES)   140 - 144   2024.8

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    Authorship:Lead author, Last author, Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ies63037.2024.10665801

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  • Holographic memory optimization method for an Optically reconfigurable gate array

    Takumi Fukumoto, Minoru Watanabe, Nobuya Watanabe

    E08 - E08   2024.8

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  • A triple modular redundant RISC-V processor on a Cyclone V FPGA

    Masato Isobe, Minoru Watanabe, Nobuya Watanabe

    RISC-V Day Tokyo 2024 Summer English   1 - 1   2024.8

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  • Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI Reviewed

    Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe

    2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)   239 - 240   2024.7

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/asap61560.2024.00055

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  • Analysis of Clock Tree Buffer Degradation Caused by Radiation Reviewed

    Minoru Watanabe

    Lecture Notes in Computer Science   120 - 133   2024.3

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    Authorship:Lead author, Last author, Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:Springer Nature Switzerland  

    DOI: 10.1007/978-3-031-55673-9_9

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  • Wafer-scale VLSI realization using programmable architecture Reviewed

    Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

    2024 IEEE International Conference on Consumer Electronics (ICCE)   1 - 2   2024.1

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/icce59016.2024.10444278

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  • Fast-neutron soft-error tolerance experimentation with a radiation-hardened optically reconfigurable gate array Reviewed

    Minoru Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shigeo Matsuyama, Misako Miwa

    2024 IEEE International Conference on Consumer Electronics (ICCE)   1 - 2   2024.1

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    DOI: 10.1109/icce59016.2024.10444280

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  • Parallel Configuration Experiment for a Radiation-Hardened Optically Reconfigurable Gate Array with a Holographic Polymer-Dispersed Liquid Crystal Memory Reviewed

    Sae Goto, Minoru Watanabe, Akifumi Ogiwara, Nobuya Watanabe

    International Conference on Consumer Electronics   2024.1

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  • Holographic Memory Formed by Different Laser Wavelengths in Laser Combiner System for Optically Reconfigurable Gate Array Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    IEEE International Conference on Consumer Electronics   2024.1

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  • Application Design System for High-Speed Dynamically Reconfigurable Gate Arrays Reviewed

    IEEE International Conference on Consumer Electronics   2024.1

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  • Remote monitoring system for optically reconfigurable gate arrays in radiation environments. Reviewed

    Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

    IEEE International Conference on Consumer Electronics   1 - 2   2024

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/ICCE59016.2024.10444276

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    Other Link: https://dblp.uni-trier.de/db/conf/iccel/icce2024.html#SekiokaWW24

  • Radiation-hardened stabilized power supply unit based on bipolar transistors Reviewed

    Takato Tanizawa, Minoru Watanabe

    International Conference on Microelectronics   2023.12

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  • Optical multi-context scrubbing operation on a redundant system Reviewed International journal

    Kakeru Ando, Minoru Watanabe, Nobuya Watanabe

    Optics Express   31 ( 23 )   38529 - 38529   2023.10

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    Authorship:Corresponding author   Publishing type:Research paper (scientific journal)   Publisher:Optica Publishing Group  

    This paper presents a proposal of the world-first optical multi-context scrubbing operation on a redundant system that can maintain the state of a sequential circuit and the operation continuously without any interruption on a radiation-hardened optically reconfigurable gate array even after a permanent failure suddenly happens on the sequential circuit or a flip-flop by radiation. Up to now, a high-speed optical scrubbing operation has been demonstrated on a radiation-hardened optically reconfigurable gate array. In addition, a multi-context scrubbing operation based on the high-speed optical scrubbing operation has already been demonstrated. Although the multi-context scrubbing operation presents the benefit that it can treat both soft-errors and permanent failures caused by radiation simultaneously, the conventional contributions have never presented how to maintain the state of a sequential circuit after a permanent failure occurs on flip-flops. Therefore, in the conventional multi-context scrubbing operation, all the operations must be restarted from the initial condition each time a permanent failure occurs on a programmable gate array. As a result, conventional multi-context scrubbing operations could not be applied for real-time systems. The proposed optical multi-context scrubbing method that can solve the issue has been experimentally evaluated on a radiation-hardened optically reconfigurable gate array.

    DOI: 10.1364/oe.500666

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  • An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit Reviewed

    Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe

    2023 IEEE 36th International System-on-Chip Conference (SOCC)   2023.9

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/socc58585.2023.10257130

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  • Construction of Laser Interferometer Consisting of Different Wavelengths Using Laser Combiner System for Fabrication of Holographic Memory for Optically Reconfigurable Gate Array Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    Microoptics Conference (MOC)   2023.9

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  • Design example of a triple modular redundancy ALU, a register file, and a program counter for a processor

    Masato Isobe, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Evaluation of low-voltage operations of an optically reconfigurable gate array VLSI

    Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • An optically reconfigurable gate array driven by an unstabilized power supply unit

    Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Total-ionizing-dose tolerance of an optically reconfigurable gate array VLSI

    Kaho Yamada, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • A mono instruction set computer architecture on an optically reconfigurable gate array VLSI

    Soma Imai, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Realization of a wafer-scale VLSI by using optically reconfigurable gate array architecture

    Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Sequential circuit implementation onto optically reconfigurable gate array VLSI using a ring oscillator

    Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Remote monitoring system used in a severe radiation environment

    Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Photodiode current range measurement result of an optically reconfigurable gate array VLSI

    Sae Goto, Minoru Watanabe, Nobuya Watanabe

    The seventh International Forum on the Decommissioning of the Fulushima Daiichi Nuclear Power Plant   2023.8

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  • Multi-context-scrubbing operation for a 1-bit counter circuit Reviewed

    Kakeru Ando, Minoru Watanabe, Nobuya Watanabe

    2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)   1 - 6   2023.6

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/newcas57931.2023.10198189

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  • Design example of a triple modular redundancy ALU and register-file for RISC-V processors

    Masato Isobe, Minoru Watanabe, Nobuya Watanabe

    RISC-V Days Tokyo 2023 Summer conference   2023.6

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  • Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock Reviewed

    Minoru Watanabe

    2023 IEEE International Symposium on Circuits and Systems (ISCAS)   1 - 6   2023.5

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    Authorship:Lead author, Last author, Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/iscas46773.2023.10181472

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  • Multi-context optically reconfigurable gate array system used for fast-neutron experiments Reviewed

    Sae Goto, Kakeru Ando, Kaho Yamada, Minoru Watanabe, Nobuya Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shingo Tamaki, Isao Murata, Sachie Kusaka

    16TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE   - ( - )   1 - 1   2023.4

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  • Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor Reviewed

    Daisuke Bamba, Minoru Watanabe, Nobuya Watanabe

    2023 IEEE International Conference on Consumer Electronics (ICCE)   - ( - )   1 - 2   2023.1

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    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/icce56470.2023.10043521

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  • Optically reconfigurable gate array VLSI that can support a perfect parallel configuration Reviewed

    Sae Goto, Minoru Watanabe, Nobuya Watanabe

    18th IEEE Asia Pacific Conference on Circuits and Systems   2022.11

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    DOI: 10.1109/APCCAS55924.2022.10090314

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  • Cf252 neutron soft error tolerance of an optoelectronic field programmable gate array VLSI Reviewed

    Minoru Watanabe

    IEEE International Integrated Reliability Workshop   2022.10

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  • Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI Reviewed

    Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe

    IEEE International Conference on Electronics Circuits and Systems   2022.10

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    DOI: 10.1109/ICECS202256217.2022.9970905

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  • Total-ionizing-dose tolerance of an optically reconfigurable gate array VLSI

    Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe

    The sixth International Forum on the Decommissioning of the Fukushima Daiichi Nuclear Power Station   2022.8

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  • Optically reconfigurable gate array VLSI without any common signal

    Sae Goto, Minoru Watanabe, Nobuya Watanabe

    The sixth International Forum on the Decommissioning of the Fukushima Daiichi Nuclear Power Station   2022.8

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  • Radiation-hardened optically reconfigurable gate array Invited

    Minoru Watanabe

    Global Summit and Expo on Nanotechnology and Nanomaterials (GSENN)   2022.6

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    DOI: 10.7567/JJAP.54.09MA06

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  • Convolutional neural network implementations using Vitis AI Reviewed

    Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya

    IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC)   365 - 371   2022.1

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    DOI: 10.1109/CCWC54503.2022.9720794

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  • Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation Reviewed

    Hiroshi Ito, Minoru Watanabe

    International Conference on Field-Programmable Technology   2021.12

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    DOI: 10.1109/ICFPT52863.2021.9609910

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  • Analysis of optical properties and internal structures of γ-ray-irradiated holographic devices formed using liquid crystal composites Reviewed International journal

    Akifumi Ogiwara, Minoru Watanabe

    Optical Materials   123   111932 - 111932   2021.12

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    DOI: 10.1016/j.optmat.2021.111932

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  • Radiation Hardened Optically Reconfigurable Gate Array Invited Reviewed

    Minoru Watanabe

    2021.11

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    DOI: 10.7567/JJAP.54.09MA06

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  • Optically reconfigurable gate array with a 1 Grad total-ionizing-dose tolerant holographic memory Reviewed

    Junya Ishido, Minoru Watanabe, Akifumi Ogiwara

    IEEE Photonics Conference (IPC)   2021.10

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    DOI: 10.1109/ipc48725.2021.9592957

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  • Holographic gratings formed by wavelength multiplexing in liquid crystal composites Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    26th Microoptics Conference (MOC)   2021.9

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    DOI: 10.23919/moc52031.2021.9598095

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  • Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs Reviewed

    Kurea Murakami, Minoru Watanabe

    IEEE International Symposium on Circuits and Systems (ISCAS)   2021.5

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    DOI: 10.1109/iscas51556.2021.9401291

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  • Effects of a radiation dose in gamma-ray irradiation fields on holographic gratings formed by liquid crystal composites Reviewed International journal

    Akifumi Ogiwara, Makishi Toda, Junya Ishido, Minoru Watanabe, Hiroshi Kakiuchida

    OSA Continuum   4 ( 2 )   514 - 514   2021.2

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    DOI: 10.1364/osac.415702

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  • Optical Multi-Context Blind Scrubbing for Field Programmable Gate Arrays Reviewed International journal

    Yusuke Takaki, Minoru Watanabe

    IEEE Photonics Journal   12 ( 6 )   1 - 11   2020.12

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    DOI: 10.1109/jphot.2020.3038900

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  • Radiation-hardened configuration-context realization for field programmable gate arrays Reviewed

    H. Shinba, M. Watanabe

    Applied Optics   59 ( 19 )   5680 - 5686   2020.6

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    DOI: 10.1364/AO.396525

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  • Multi-context holographic memory exploiting a wavelength-dependent optimization technique Invited Reviewed

    Junya Ishido, Minoru Watanabe

    IEEE International Conference on Photonics   2020.5

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    DOI: 10.1109/ICP46580.2020.9206463

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  • Implementation of RISC-V Processor and MAX-10 FPGA

    Md Roman Ahmed, Minoru Watanabe

    The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University   2020.3

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  • Place and route tool for optically reconfigurable gate arrays with fault cells

    Yuki Takena, Minoru Watanabe

    The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University   2020.3

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  • Radiation tolerance of a crystal oscillator circuit

    Yuichi Moriya, Minoru Watanabe

    The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University   2020.3

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  • Radiation-hardened optically reconfigurable gate array using a multi-wavelength holographic memory Reviewed

    Junya Ishido, Minoru Watanabe

    IEEE Workshop on Silicon Errors in Logic – System Effects   2020.2

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  • Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation Reviewed

    Masaki Watanabe, Minoru Watanabe

    IEEE Asia Pacific Conference on Circuits and Systems   2019.11

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    DOI: 10.1109/APCCAS47518.2019.8953122

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  • Effect of radiation dose of Gamma-Ray irradiation on volume gratings using liquid crystal composites Reviewed

    Makishi Toda, Akifumi, Ogiwara, Minoru Watanabe

    Microoptics Conference   238 - 239   2019.11

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    DOI: 10.23919/MOC46630.2019.8982829

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  • Parallel-operation-oriented optically reconfigurable gate array VLSI with four gate array layers Reviewed

    Hirotoshi Ito, Minoru Watanabe

    IEEE International Conference on Space Optical Systems and Applications   2019.10

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  • Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array Reviewed

    Hirotoshi Ito, Minoru Watanabe

    2019.9

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  • FPGA implementation of a robot control algorithm Reviewed

    Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano

    International Conference on Emerging Technologies and Factory Automation   2019.9

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  • Optically Reconfigurable Gate Array with a triple modular redundancy Reviewed

    Toru Yoshinaga, Minoru Watanabe

    International Conference on Space Science and Communication   2019.7

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  • A 1.15 Grad total-ionizing-dose tolerance parallel-operation-oriented optically reconfigurable gate array VLSI Reviewed

    Takumi Fujimori, Minoru Watanabe

    IEEE International Workshop on Metrology for AeroSpace   2019.6

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  • An optically reconfigurable gate array workable under a strong gamma radiation environment Reviewed

    Shinya Fujisaki, Takumi Fujimori, Minoru Watanabe

    IEEE- Workshop on Microelectronics and Electron Devices   2019.4

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    DOI: 10.1109/WMED.2019.8714154

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  • 1 Grad radiation-hardened optoelectronic embedded system

    M. Watanabe

    IEEE Workshop on Silicon Errors in Logic – System Effects   2019.3

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  • FPGAによる自動車の自動走行コンテスト Invited

    渡邊 実

    情報・システムソサイエティ誌   24 ( 3 )   2019

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  • Soft-error tolerance of an optically reconfigurable gate array VLSI Reviewed

    T. Fujimori, M. Watanabe

    INTERNATIONAL CONFERENCE ON SYSTEMS ENGINEERING   1 - 6   2018.12

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    DOI: 10.1109/ICSENG.2018.8638203

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  • Radiation-hardened motor controller

    2018.11

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  • Many modular redundancy implementation on CPLD

    Masaki Watanabe, Minoru Watanabe

    2018.11

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  • Full-hardware robot controller

    2018.11

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  • Radiation-hardened power supply unit

    2018.11

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  • Radiation-hardened optically reconfigurable gate array Reviewed

    2018.11

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  • An optically reconfigurable gate array using four liquid crystal spatial light modulators Reviewed

    Y. Takaki, M. Watanabe

    IEEE CPMT Symposium Japan   185 - 188   2018.11

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    DOI: 10.1109/ICSJ.2018.8602907

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  • Triple modular redundancy optically reconfigurable gate array

    2018.11

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  • Optically reconfigurable gate array using a colored configuration, Reviewed

    T. Fujimori, M. Watanabe

    Applied Optics   57 ( 29 )   8625 - 8631   2018.10

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    DOI: 10.1364/AO.57.008625

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  • Effects of radiation exposure on volume gratings formed in liquid crystal composites Reviewed

    A Ogiwara, M. Toda, M. Watanabe, H. Kakiuchida

    2018 KJF International Conference on Organic Materials for Electronics and Photonics   2018.9

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  • Radiation-hardened and stabilized power supply unit based on a lithiumion battery Reviewed

    S. Fujisaki, M. Watanabe

    Radiation and its Effects on Components and Systems conference   2018.9

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  • Total-Ionizing-Dose Tolerance of the configuration function of MAX3000A CPLDs Reviewed

    T. Fujimori, M. Watanabe

    Data Workshop   2018.9

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  • Ultrasonic sensor system with a 94 Mrad total-ionizing-dose tolerance Reviewed

    S. Fujisaki, M. Watanabe

    IEEE International Conference on Semiconductor Electronics   263 - 266   2018.8

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    DOI: 10.1109/SMELEC.2018.8481328

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  • A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory Reviewed

    T. Fujimori, M. Watanabe

    NASA/ESA Conference on Adaptive Hardware and Systems   2018.8

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    DOI: 10.1109/AHS.2018.8541375

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  • Tolerance of radiation exposure on volume gratings using liquid crystal composites Reviewed

    M.Toda, A.Ogiwara, M.Watanabe

    27th International Liquid Crystal Conference (ILCC2018)   P4-C2-47   2018.7

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  • A 603 Mrad total-ionizing-dose tolerance optically reconfigurable gate array VLSI Reviewed

    T. Fujimori, M. Watanabe

    International Conference on Signals and Systems   249 - 254   2018.5

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    DOI: 10.1109/ICSIGSYS.2018.8372766

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  • High total-ionizing-dose tolerance field programmable gate array Reviewed

    T. Fujimori, M. Watanabe

    IEEE International Symposium on Circuits and Systems   1 - 4   2018.5

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    DOI: 10.1109/ISCAS.2018.8351543

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  • An 807 Mrad total dose tolerance of an optically reconfigurable gate array VLSI

    T. Fujimori, M. Watanabe

    2018.4

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  • FFT implementation using mono-instruction set computer (MISC) architecture Reviewed

    H. Shinba, M. Watanabe

    Second Workshop on Pioneering Processor Paradigms   2018.2

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  • Resistance evaluation of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation Reviewed

    Akifumi Ogiwara, Minoru Watanabe, Yoshizumi Ito

    22nd Microoptics Conference, MOC 2017   2017-   200 - 201   2017.11

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    DOI: 10.23919/MOC.2017.8244556

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  • Parallel light configuration that increases the radiation tolerance of integrated circuits Reviewed

    Takumi Fujimori, Minoru Watanabe

    OPTICS EXPRESS   25 ( 23 )   28136 - 28145   2017.11

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    DOI: 10.1364/OE.25.028136

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  • Small Area Implementation for Optically Reconfigurable Gate Array VLSI: FFT Case Reviewed

    Ili Shairah Abdul Halim, Fuminori Kobayashi, Minoru Watanabe, Koichiro Mashiko, Ooi Chia Yee

    JOURNAL OF SCIENTIFIC & INDUSTRIAL RESEARCH   76 ( 11 )   697 - 700   2017.11

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  • FPGA hardware accelerator for holographic memory calculations for optically reconfigurable gate arrays Reviewed

    Yoshizumi Ito, Minora Watanabe

    2017 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2017   146 - 149   2017.11

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    DOI: 10.1109/ICSOS.2017.8357225

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  • Optically reconfigurable gate array driven by a lithium-ion battery Reviewed

    S. Fujisaki, M. Watanabe, Y. Takaki

    IEEE CPMT Symposium Japan   227 - 230   2017.11

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    DOI: 10.1109/ICSJ.2017.8240123

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  • Holographic memory calculation FPGA accelerator for optically reconfigurable gate arrays Reviewed

    Takumi Fujimori, Minoru Watanabe

    Proceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017   2018-   620 - 625   2017.11

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    DOI: 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.109

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  • Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array Reviewed

    Takumi Fujimori, Minoru Watanabe

    International System on Chip Conference   2017-   91 - 95   2017.9

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE Computer Society  

    DOI: 10.1109/SOCC.2017.8226014

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  • Asynchronous optical bus for optical VLSIs Reviewed

    Takumi Fujimori, Minoru Watanabe

    7th International Conference on Innovative Computing Technology, INTECH 2017   162 - 166   2017.8

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    DOI: 10.1109/INTECH.2017.8102440

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  • Multi-context scrubbing method Reviewed

    Takumi Fujimori, Minora Watanabe

    Midwest Symposium on Circuits and Systems   2017-   1548 - 1551   2017.8

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    DOI: 10.1109/MWSCAS.2017.8053231

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  • Development of a radiation-hardened embedded system used for robots decommissioning nuclear reactors Reviewed

    M. Watanabe

    ACTINIDES2017   2017.7

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  • 500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA Reviewed

    Yoshizumi Ito, Minora Watanabe, Akifumi Ogiwara

    2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017   167 - 171   2017.7

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    DOI: 10.1109/AHS.2017.8046374

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  • High-speed scrubbing based on asynchronous optical configuration Reviewed

    Takumi Fujimori, Minoru Watanabe

    2017 2nd International Conference on Opto-Electronic Information Processing, ICOIP 2017   74 - 78   2017.7

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    DOI: 10.1109/OPTIP.2017.8030702

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  • Gate density advantage of parallel-operation-oriented FPGA architecture Reviewed

    Takumi Fujimori, Minora Watanabe

    Proceedings of the IEEE National Aerospace Electronics Conference, NAECON   2017   155 - 158   2017.6

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    DOI: 10.1109/NAECON.2017.8268761

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  • Tolerance of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation Reviewed

    Akifumi Ogiwara, Minoru Watanabe, Yoshizumi Ito

    APPLIED OPTICS   56 ( 16 )   4854 - 4860   2017.6

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    DOI: 10.1364/AO.56.004854

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  • 300 Mrad total-ionizing-dose tolerance of a holographic memory on an optically reconfigurable gate array Reviewed

    Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

    2017 6th International Symposium on Next Generation Electronics, ISNE 2017   1 - 3   2017.5

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    DOI: 10.1109/ISNE.2017.7968743

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  • Error injection analysis for triple modular and penta-modular redundancies Reviewed

    Ryo Terada, Minoru Watanabe

    2017 6th International Symposium on Next Generation Electronics, ISNE 2017   1 - 4   2017.5

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    DOI: 10.1109/ISNE.2017.7968746

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  • Motor controller radiation tolerance experiments Reviewed

    Takumi Hatamochi, Minoru Watanabe

    2017 6th International Symposium on Next Generation Electronics, ISNE 2017   1 - 2   2017.5

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    DOI: 10.1109/ISNE.2017.7968747

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  • High-speed scrubbing demonstration using an optically reconfigurable gate array Reviewed

    Takumi Fujimori, Minoru Watanabe

    OPTICS EXPRESS   25 ( 7 )   7807 - 7817   2017.4

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    DOI: 10.1364/OE.25.007807

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  • Japanese High-level Synthesis Tools for FPGA Hardware Acceleration Invited Reviewed

    WATANABE Minoru, SANO Kentaro, TAKAMAEDA Shinya, MIYOSHI Takefumi, NAKAJO Hironori

    J100-B ( 1 )   1 - 10   2017.1

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    Recently, field programmable gate arrays (FPGAs) are being widely used for consumer electronics, automotive embedded systems, space embedded systems, and so on. Since the performances of FPGAs were much lower than those of application specific integrated circuits (ASICs) until around 2006 due to their look-up table and switching matrix architectures, FPGAs were only used for prototyping systems, tests, research equipment, and so on and could not be used for high-performance systems. However, subsequently, FPGAs have been being fabricated by using the latest VLSI technology while ASICs could only use retro process technologies. Up to now, the performances of FPGAs have been improved drastically. A lot of papers have presented that hardware accelerators on FPGAs are useful for increasing the performances of a software operations on computer systems. Moreover, XILINX and Altera are currently providing general-purpose high-level synthesis tools. However, the performances are not better than those of designs using hardware description language. Therefore, this paper introduces some new Japanese high-level synthesis tools which are useful for specific domains.

    DOI: 10.14923/transcomj.2016jbi0002

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  • Optically reconfigurable gate array platform for Mono-instruction set computer architecture Reviewed

    Hiroki Shimba, Minoru Watanabe

    2017 IEEE 7th Annual Computing and Communication Workshop and Conference   1 - 4   2017.1

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    DOI: 10.1109/CCWC.2017.7868473

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  • A 200 Mrad radiation tolerance of a polymer-dispersed liquid crystal holographic memory Reviewed

    Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

    PROCEEDINGS OF 2016 IEEE 18TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS; IEEE 14TH INTERNATIONAL CONFERENCE ON SMART CITY; IEEE 2ND INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (HPCC/SMARTCITY/DSS)   1534 - 1535   2016.12

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    DOI: 10.1109/HPCC-SmartCity-DSS.2016.29

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  • Compilation time advantage of parallel-operation-oriented optically reconfigurable gate arrays Reviewed

    Takumi Fujimori, Minoru Watanabe

    2016 INTERNATIONAL CONFERENCE ON ADVANCED MECHATRONIC SYSTEMS (ICAMECHS)   306 - 311   2016.11

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    DOI: 10.1109/ICAMechS.2016.7813465

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  • A 300 Mrad total-ionizing dose experiment of lasers used for holographic memories Reviewed

    T. Akabe, M. Watanabe

    International Conference On Advances in Computing, Electronics and Electrical Technology   17 - 20   2016.11

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  • Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays Reviewed

    Bharat Ramanathan, Minoru Watanabe

    2016 11TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION (ICCSE)   454 - 457   2016.8

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    DOI: 10.1109/ICCSE.2016.7581623

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  • Effects of multi-context information recorded at different regions in holographic polymer-dispersed liquid crystal on optical reconfiguration Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    JAPANESE JOURNAL OF APPLIED PHYSICS   55 ( 8 )   08RG04-1 - 08RG04-6   2016.8

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    DOI: 10.7567/JJAP.55.08RG04

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  • Direct optical communication on an optically reconfigurable gate array Reviewed

    Shinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi

    2016 FIFTH INTERNATIONAL CONFERENCE ON FUTURE COMMUNICATION TECHNOLOGIES (FGCT)   17 - 20   2016.8

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    DOI: 10.1109/FGCT.2016.7605065

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  • Demonstrating a Holographic Memory Having 100 Mrad Total-Ionizing-Dose Tolerance Reviewed

    Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara

    PROCEEDINGS OF 2016 7TH INTERNATIONAL CONFERENCE ON MECHANICAL AND AEROSPACE ENGINEERING, (ICMAE)   377 - 380   2016.7

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    DOI: 10.1109/ICMAE.2016.7549569

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  • Radiation tolerance of a MEMS mirror device Reviewed

    Takumi Fujimori, Minoru Watanabe

    2016 INTERNATIONAL CONFERENCE ON OPTICAL MEMS AND NANOPHOTONICS (OMN)   1 - 2   2016.7

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    DOI: 10.1109/OMN.2016.7565925

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  • Architecture-Independent Negative Logic Implementation for Optically Reconfigurable Gate Arrays Reviewed

    Takumi Fujimori, Minoru Watanabe

    PROCEEDINGS OF 2016 7TH INTERNATIONAL CONFERENCE ON MECHANICAL AND AEROSPACE ENGINEERING, (ICMAE)   381 - 385   2016.7

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    DOI: 10.1109/ICMAE.2016.7549570

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  • A 180 Mrad Total-Ionizing Dose Experiment for Laser Arrays on Optically Reconfigurable Gate Arrays Reviewed

    K. Akagi, M. Watanabe

    25th Annual Single Event Effects (SEE) Symposium   2016.5

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  • Quality Recovery Method of Interference Patterns Generated From Faulty MEMS Spatial Light Modulators Reviewed

    Minoru Watanabe

    JOURNAL OF LIGHTWAVE TECHNOLOGY   34 ( 3 )   910 - 917   2016.2

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    DOI: 10.1109/JLT.2015.2483622

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  • Full FPGA Game Machine Reviewed

    Takumi Fujimori, Minoru Watanabe

    2016 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE)   431 - 432   2016.1

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    DOI: 10.1109/ICCE.2016.7430678

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  • Reconfiguration performance recovery on optically reconfigurable gate arrays Reviewed

    Tomoya Akabe, Minoru Watanabe

    2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID)   603 - 604   2016.1

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    DOI: 10.1109/VLSID.2016.67

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  • Angle-multiplexing recording of circuit information in volume hologram using liquid crystal composites

    Akifumi Ogiwara, Yuta Maeda, Minoru Watanabe

    Optics InfoBase Conference Papers   2016

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    DOI: 10.1364/iprsn.2016.jtu4a.38

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  • Sustainable advantage of a parallel configuration in an optical FPGA Reviewed

    Minoru Watanabe

    2015 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION (SII)   807 - 810   2015.12

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    DOI: 10.1109/SII.2015.7405083

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  • Triple modular redundancy on parallel-operation-oriented optically reconfigurable gate arrays Reviewed

    Yoshizumi Ito, Minoru Watanabe

    2015 IEEE INTERNATIONAL CONFERENCE ON AEROSPACE ELECTRONICS AND REMOTE SENSING TECHNOLOGY (ICARES)   2015.12

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    DOI: 10.1109/ICARES.2015.7429829

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  • Total-ionizing-dose tolerance analysis of an optically reconfigurable gate array VLSI

    Minoru Watanabe

    2015 IEEE International Conference on Aerospace Electronics and Remote Sensing Technology (ICARES)   2015.12

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    DOI: 10.1109/icares.2015.7429832

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  • FPGA Trax Solver based on a Neural Network Design Reviewed

    Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe

    2015 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (FPT)   260 - 263   2015.12

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    DOI: 10.1109/FPT.2015.7393119

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  • Formation of holographic polymer dispersed liquid crystal memory by angle-multiplexing recording for optically reconfigurable gate arrays Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    APPLIED OPTICS   54 ( 36 )   10623 - 10629   2015.12

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    DOI: 10.1364/AO.54.010623

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  • Triple modular redundancy on parallel-operation-oriented FPGA architectures for optical communications Reviewed

    Minoru Watanabe

    2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015   1 - 4   2015.10

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    DOI: 10.1109/ICSOS.2015.7425070

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  • 100 mrad total-ionizing dose tolerance experiment of a laser array Reviewed

    Kouta Akagi, Minoru Watanabe

    2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015   1 - 3   2015.10

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    DOI: 10.1109/ICSOS.2015.7425076

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  • Fresnel lens radiation shield for photodiodes Reviewed

    Minoru Watanabe

    2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015   1 - 2   2015.10

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    DOI: 10.1109/ICSOS.2015.7425088

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  • Effect of Laser Exposure Condition on Formation of Holographic Memory by Angle-multiplexing Recording using Liquid Crystal composites Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    2015 20TH MICROOPTICS CONFERENCE (MOC)   1 - 2   2015.10

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    DOI: 10.1109/MOC.2015.7416433

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  • Investigating the radiation tolerance of a laser array for an optically reconfigurable gate array Reviewed

    Kouta Akagi, Minoru Watanabe

    2015 20TH MICROOPTICS CONFERENCE (MOC)   1 - 2   2015.10

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    DOI: 10.1109/MOC.2015.7416484

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  • Total ionizing dose tolerance of the serial configuration on cyclone II FPGA Reviewed

    Hiroyuki Ito, Minoru Watanabe

    2015 IEEE International Conference on Space Optical Systems and Applications, ICSOS 2015   1 - 4   2015.10

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    DOI: 10.1109/ICSOS.2015.7425067

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  • Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics Reviewed

    Daisaku Seto, Minoru Watanabe

    JAPANESE JOURNAL OF APPLIED PHYSICS   54 ( 9 )   09MA06-1 - 09MA06-5   2015.9

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    DOI: 10.7567/JJAP.54.09MA06

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  • Formation of holographic memory by angle-multiplexing recording in liquid crystal composites Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    2015 11th Conference on Lasers and Electro-Optics Pacific Rim, CLEO-PR 2015   3   1 - 2   2015.8

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    DOI: 10.1109/CLEOPR.2015.7376567

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  • Holographic scrubbing technique for a programmable gate array Reviewed

    Minoru Watanabe, Takumi Fujimori

    2015 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS)   1 - 5   2015.6

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    DOI: 10.1109/AHS.2015.7231161

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  • Radiation-hardened Optically Reconfigurable Gate Array Using a Negative Logic Configuration without a Dedicated VLSI Reviewed

    T. Fujimori, M. Watanabe

    24th Annual Single Event Effects (SEE) Symposium   2015.5

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  • High-resolution configuration of optically reconfigurable gate arrays Reviewed

    Kouta Akagi, Minoru Watanabe

    2015 International Symposium on Next-Generation Electronics (ISNE)   1 - 4   2015.5

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    DOI: 10.1109/ISNE.2015.7131967

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  • Design of a parallel-operation-oriented FPGA Reviewed

    Minoru Watanabe

    2015 International Symposium on Next-Generation Electronics (ISNE)   1 - 4   2015.5

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    DOI: 10.1109/ISNE.2015.7132021

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  • Radiation tolerance experiment for a dynamically reconfigurable vision architecture, Reviewed

    M. Watanabe, S. Kawahito

    International Journal of Image Processing Techniques   2 ( 1 )   59 - 62   2015.4

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  • Total ionizing dose effects of optical components on an optically reconfigurable gate array Reviewed

    Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   9040   393 - 400   2015.3

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    DOI: 10.1007/978-3-319-16214-0_35

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  • Parallel-Operation-Oriented Optically Reconfigurable Gate Array Reviewed

    Takumi Fujimori, Minoru Watanabe

    ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2015   9017   3 - 14   2015.3

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    DOI: 10.1007/978-3-319-16086-3_1

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  • Radiation tolerance of optically reconfigurable gate arrays

    R. Moriwaki, H. Ito, M. Watanabe, A. Ogiwara, H. Maekawa

    International Symposium Toward the Future of Advanced Researches in Shizuoka University   2015.1

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  • Optically Reconfigurable Gate Array Prototype System

    M. Seo, M. Watanabe

    The 1st RIS-MJIIT Workshop on Renewable and Sustainable Integrated Systems   2015

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  • Radiation tolerance experiment for a dynamically reconfigurable vision architecture Reviewed

    M. Watanabe, S. Kawahito

    International Conference on Advances in Computing, Electronics and Electrical Technology   1 - 4   2014.12

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  • Dependable Optically Reconfigurable Gate Array Architecture

    Minoru Watanabe

    International Symposium on Optical Memory   210 - 211   2014.10

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  • Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture Reviewed

    Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito

    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   1528 - 1531   2014.6

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    DOI: 10.1109/ISCAS.2014.6865438

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  • A parallel-operation-oriented FPGA architecture Reviewed

    M. Watanabe

    International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies   123 - 126   2014.6

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  • Optically Reconfigurable Gate Array with an Angle-Multiplexed Holographic Memory Reviewed

    Retsu Moriwaki, Hikaru Maekawa, Akifumi Ogiwara, Minoru Watanabe

    GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI   341 - 346   2014.5

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    DOI: 10.1145/2591513.2591597

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  • Radiation tolerance of color configuration on an optically reconfigurable gate array Reviewed

    Takumi Fujimori, Minoru Watanabe

    PROCEEDINGS OF 2014 IEEE INTERNATIONAL PARALLEL & DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW)   205 - 210   2014.5

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    DOI: 10.1109/IPDPSW.2014.27

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  • Dependable optically differential reconfigurable gate array Reviewed

    M. Seo, M. Watanabe

    International Conference on Space Optical Systems and Applications, CD-ROM (6 pages)   2014.5

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  • Enhanced radiation tolerance of an optically reconfigurable gate array by exploiting an inversion/non-inversion implementation Reviewed

    Takashi Yoza, Minoru Watanabe

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   8405   156 - 166   2014.4

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    DOI: 10.1007/978-3-319-05960-0_14

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  • A high-density optically reconfigurable gate array VLSI using variable holographic memory patterns Reviewed

    K. Akagi, M. Watanabe

    International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems   2014.3

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  • Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

    Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

    Emerging Liquid Crystal Technologies IX   9004   90040M-1   2014.2

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    DOI: 10.1117/12.2038024

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  • Mono-instruction set computer architecture on a 3D optically reconfigurable gate array Reviewed

    Hiroyuki Ito, Minoru Watanabe

    2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS)   173 - 176   2013.12

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    DOI: 10.1109/EDAPS.2013.6724417

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  • Many-module redundancy implementation of mono instruction set computers for 3D optical FPGAs Reviewed

    Yuya Shirahashi, Minoru Watanabe

    2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS)   169 - 172   2013.12

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    DOI: 10.1109/EDAPS.2013.6724416

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  • Color configuration method for an optically reconfigurable gate array Reviewed

    Takumi Fujimori, Minoru Watanabe

    PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)   406 - 409   2013.12

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    DOI: 10.1109/FPT.2013.6718400

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  • FPGA Blokus Duo Solver using a massively parallel architecture Reviewed

    Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe

    PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)   494 - 497   2013.12

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    DOI: 10.1109/FPT.2013.6718426

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  • A dynamic optically reconfigurable gate array using a blue laser Reviewed

    Takayuki Kubota, Minoru Watanabe

    4th International Conference on Photonics, ICP 2013 - Conference Proceeding   129 - 131   2013.10

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    DOI: 10.1109/ICP.2013.6687090

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  • Angle-multiplexing recording of multi-context for optically reconfigurable gate array in holographic memory using liquid crystal composites Reviewed

    Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

    2013 18TH MICROOPTICS CONFERENCE (MOC)   2013.10

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  • Temperature dependence of anisotropic diffraction in holographic polymer-dispersed liquid crystal memory Reviewed

    Akifumi Ogiwara, Minoru Watanabe, Retsu Moriwaki

    APPLIED OPTICS   52 ( 26 )   6529 - 6536   2013.9

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    DOI: 10.1364/AO.52.006529

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  • IMAGE RECOGNITION OPERATION ON A DYNAMICALLY RECONFIGURABLE VISION ARCHITECTURE Reviewed

    Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito

    2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS   1 - 4   2013.9

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    DOI: 10.1109/FPL.2013.6645603

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  • A fine-grained dependable optically reconfigurable gate array as a multi-soft-core processor platform Reviewed

    Retsu Moriwaki, Minoru Watanabe

    Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013   7 - 12   2013.9

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    DOI: 10.1109/MCSoC.2013.33

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  • Fourier transformation on an optically reconfigurable gate array Reviewed

    Hiroyuki Ito, Minoru Watanabe

    2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)   193 - 196   2013.8

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    DOI: 10.1109/MWSCAS.2013.6674618

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  • Configuration on an optically reconfigurable gate array under the maximum 120°C temperature condition Reviewed

    R. Moriwaki, M. Watanabe, A. Ogiwara

    OptoElectronics and Communications Conference   1 - 2   2013.7

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  • A 7-depth search FPGA Connect6 Solver Reviewed

    R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, A. Tanigawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   95 - 98   2013.6

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  • Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method Reviewed

    Yuichiro Yamaji, Minoru Watanabe

    Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013   172 - 177   2013.6

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    DOI: 10.1109/AHS.2013.6604242

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  • A dependability-increasing demonstration for a 16-configuration context optically reconfigurable gate array Reviewed

    A. Tanigawa, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   129 - 132   2013.6

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  • Formation of holographic memory by recording of multi-context in liquid crystal composites

    Akifumi Ogiwara, Hikaru Maekawa, Minoru Watanabe, Retsu Moriwaki

    2013 Conference on Lasers and Electro-Optics Pacific Rim (CLEOPR)   1 - 2   2013.6

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    DOI: 10.1109/cleopr.2013.6600439

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  • Dependability-increasing technique for a multi-context optically reconfigurable gate array Reviewed

    Akira Tanigawa, Minoru Watanabe

    2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   1568 - 1571   2013.5

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    DOI: 10.1109/ISCAS.2013.6572159

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  • 0.18 μm CMOS process photodiode memory Reviewed

    Takayuki Kubota, Minoru Watanabe

    Proceedings - IEEE International Symposium on Circuits and Systems   1464 - 1467   2013.5

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    DOI: 10.1109/ISCAS.2013.6572133

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  • MEMS interleaving method for optically reconfigurable gate arrays Reviewed

    Y. Yamaji, M. Watanabe

    IEEE International Conference on Electro/Information Technology   172 - 177   2013.5

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  • Formation of temperature dependable holographic memory using holographic polymer-dispersed liquid crystal Reviewed

    Akifumi Ogiwara, Minoru Watanabe, Retsu Moriwaki

    Optics Letters   38 ( 7 )   1158 - 1160   2013.4

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    DOI: 10.1364/OL.38.001158

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  • Power consumption of mono-instruction set computers (MISCs) Reviewed

    H. Ito, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips   2013.4

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  • Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation Reviewed

    Retsu Moriwaki, Minoru Watanabe

    Applied Optics   52 ( 9 )   1939 - 1946   2013.3

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    DOI: 10.1364/AO.52.001939

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  • Dependability-increasing method of processors under a space radiation environment Reviewed

    Yuya Shirahashi, Minoru Watanabe

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   7806   218   2013.3

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    DOI: 10.1007/978-3-642-36812-7_21

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  • Temperature Dependable Holographic Memory Using Holographic Polymer-dispersed Liquid Crystal Reviewed

    A. Ogiwara, M. Watanabe, R. Moriwaki

    Progress In Electromagnetics Research Symposium   322 - 325   2013.3

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  • A 9-configuration-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory

    R. Moriwaki, M. Watanabe, A. Ogiwara

    Takayanagi Kenjiro Memorial Symposium   112 ( 325 )   S3_10_1 - S3_10_4   2012.11

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    Optically reconfigurable gate arrays (ORGAs) have been developed as a type of dynamically reconfigurable gate array that can achieve a high-speed reconfiguration and numerous reconfiguration contexts. However, in the ORGAs, many laser sources are necessary to address the numerous configuration contexts. Therefore, as a reduction method of the number of lasers, an ORGA using a polymer-dispersed liquid crystal holographic memory has been proposed. This paper presents a more advanced 9-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory.

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  • A uniform partitioning method for mono-instruction set computer (MISC) Reviewed

    Hiroyuki Ito, Minoru Watanabe

    Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012   832 - 837   2012.9

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    DOI: 10.1109/NBiS.2012.107

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  • A 256-configuration-context MEMS optically reconfigurable gate array Reviewed

    Y. Yamaji, M. Watanabe

    International Conference on Solid State Devices and Materials   232 - 233   2012.9

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  • Inversion/non-inversion reconfiguration scheme for a 0.18 μm CMOS process optically reconfigurable gate array VLSI Reviewed

    Takahiro Watanabe, Minoru Watanabe

    2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)   117 - 120   2012.8

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    DOI: 10.1109/MWSCAS.2012.6291971

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  • 0.18 μm CMOS Process highly sensitive differential optically reconfigurable gate array VLSI Reviewed

    Takahiro Watanabe, Minoru Watanabe

    2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)   308 - 313   2012.8

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    DOI: 10.1109/ISVLSI.2012.71

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  • A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function Reviewed

    Takashi Yoza, Minoru Watanabe

    Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012   361 - 366   2012.8

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    DOI: 10.1109/FPL.2012.6339205

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  • Optical reconfiguration by anisotropic diffraction in holographic polymer-dispersed liquid crystal memory Reviewed

    Akifumi Ogiwara, Minoru Watanabe

    APPLIED OPTICS   51 ( 21 )   5168 - 5177   2012.7

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    DOI: 10.1364/AO.51.005168

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  • Methods for detection and compensation of alignment errors occurring between a programmable optically reconfigurable gate array and its writer system Reviewed

    Shinya Kubota, Minoru Watanabe

    PROCEEDINGS OF THE 2012 IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON)   182 - 185   2012.7

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    DOI: 10.1109/NAECON.2012.6531052

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  • Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation Reviewed

    R. Moriwaki, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   127 - 132   2012.7

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  • A 4-configuration context fiber-linked optically reconfigurable gate array Reviewed

    Yumiko Ueno, Minoru Watanabe

    Technical Digest - 2012 17th Opto-Electronics and Communications Conference, OECC 2012   592 - 593   2012.6

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    DOI: 10.1109/OECC.2012.6276587

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  • A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array Reviewed

    Takashi Yoza, Minoru Watanabe

    2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)   92 - 98   2012.6

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    DOI: 10.1109/AHS.2012.6268635

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  • 0.18 μm CMOS process high-sensitivity optically reconfigurable gate array VLSI Reviewed

    T. Watanabe, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   147 - 151   2012.5

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  • FPGA Connect6 Solver with Hardware Sort Units Reviewed

    R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, T. Watanabe, Y. Aoyama, M. Seo, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   163 - 166   2012.5

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  • High speed - low power optical configuration on an ORGA with a phase-modulation type holographic memory Reviewed

    Takahiro Watanabe, Minoru Watanabe

    2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW)   256 - 260   2012.5

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    DOI: 10.1109/IPDPSW.2012.28

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  • Mono-instruction computer on a dynamically reconfigurable gate array Reviewed

    Y. Nihira, M, Watanabe

    Workshop on Synthesis And System Integration of Mixed Information technologies   66 - 70   2012.3

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  • Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arrays Reviewed

    Takahiro Watanabe, Minoru Watanabe

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   7199   163 - 173   2012.3

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    DOI: 10.1007/978-3-642-28365-9_14

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  • A full dynamically reconfigurable vision-chip system including a lens-array Reviewed

    Y. Kamikubo, M. Watanabe, S. Kawahito

    Workshop on Synthesis And System Integration of Mixed Information technologies   272 - 277   2012.3

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  • Dependable Optically Reconfigurable Gate Array

    Minoru Watanabe

    2012 International Workshop on Advanced Nanovision Science   47 - 50   2012.1

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  • Binary MEMS optically reconfigurable gate array for an artificial brain system Reviewed

    Yuichiro Yamaji, Minoru Watanabe

    PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON ARTIFICIAL LIFE AND ROBOTICS (AROB 17TH '12)   614 - 617   2012.1

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  • Gray-level image recmgnitimrmn a dynamically recmnfigurablevisimnarchitecture Reviewed

    Yuki Kamikubo, Minonu Witanabe, Shoji Kawahito

    International System on Chip Conference   61 - 65   2012

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    DOI: 10.1109/SOCC.2012.6398381

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  • Holographic polymer-dispersed liquid crystal memory for optically reconfigurable gate array using subwavelength grating mask Reviewed

    Akifumi Ogiwara, Minoru Watanabe, Takayuki Mabuchi, Fuminori Kobayashi

    APPLIED OPTICS   50 ( 34 )   6369 - 6376   2011.12

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    DOI: 10.1364/AO.50.006369

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  • An FPGA Connect6 Solver with a Two-Stage Pipelined Evaluation Reviewed

    Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe

    2011 International Conference on Field-Programmable Technology, FPT 2011   2011.12

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    DOI: 10.1109/FPT.2011.6133249

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  • Full liquid crystal spatial light modulator writer system for a programmable optically reconfigurable gate array Reviewed

    S. Kubota, M. Watanabe

    MICROOPTICS CONFERENCE   H-47   2011.11

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  • Holographic polymer-dispersed liquid crystal memory for optically reconfigurable gate array using subwavelength grating mask Reviewed

    OGIWARA Akifumi, WATANABE Minoru, MABUCHI Takayuki, KOBAYASHI Fuminori

    APPLIED OPTICS   50 ( 34 )   6369 - 6376   2011.11

  • Robust holographic storage system design Reviewed

    Takahiro Watanabe, Minoru Watanabe

    OPTICS EXPRESS   19 ( 24 )   24147 - 24158   2011.11

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    DOI: 10.1364/OE.19.024147

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  • Triple module redundancy scheme on an optically reconfigurable gate array Reviewed

    Y. Torigai, M. Watanabe

    International SoC Design Conference   250 - 253   2011.11

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    DOI: 10.1109/ISOCC.2011.6138757

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  • Multi-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory Reviewed

    R. Moriwaki, M. Watanabe, A. Ogiwara, F. Kobayashi

    MICROOPTICS CONFERENCE   1 - 2   2011.11

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  • Holographic memory formed by multi-context recording for optically reconfigurable gate array Reviewed

    A. Ogiwara, M. Watanabe, F. Kobayashi

    17th Microopics Conference (MOC)   1 - 2   2011.11

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  • Dependable optically reconfigurable gate array with a phase-modulation type holographic memory Reviewed

    Takahiro Watanabe, Minoru Watanabe

    2011 21st International Conference on Field Programmable Logic and Applications   34 - 37   2011.9

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    DOI: 10.1109/FPL.2011.17

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  • A Four-Context Programmable Optically Reconfigurable Gate Array With a Reflective Silver-Halide Holographic Memory Reviewed

    Shinya Kubota, Minoru Watanabe

    IEEE PHOTONICS JOURNAL   3 ( 4 )   665 - 675   2011.8

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    DOI: 10.1109/JPHOT.2011.2160335

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  • Novel dynamic module multiple redundancy for optically reconfigurable gate arrays

    Minoru Watanabe

    IEEE International Midwest Symposium on Circuits & Systems   2011.8

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  • Dynamic reconfiguration on a dynamically reconfigurable vision-chip architecture Reviewed

    A. Gundjalam, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   2011.7

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  • A MEMS writer system embedded for a programmable optically reconfigurable gate array Reviewed

    S. Kubota, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   130 - 135   2011.6

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  • Optically reconfigurable gate array with a polymer-dispersed liquid crystal holographic memory Reviewed

    Takayuki Mahuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi

    Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011   44 - 49   2011.6

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    DOI: 10.1109/AHS.2011.5963965

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  • Parallel template matching operations on a dynamically reconfigurable vision-chip architecture Reviewed

    Hironari Nakada, Minora Watanabe, Shoji Kawahito

    2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011   205 - 208   2011.6

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    DOI: 10.1109/NEWCAS.2011.5981291

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  • A 16-laser array for an optically reconfigurable gate array Reviewed

    Takahiro Watanabe, Minoru Watanabe

    2011 International Conference on Space Optical Systems and Applications, ICSOS'11   255 - 260   2011.5

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    DOI: 10.1109/ICSOS.2011.5783679

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  • A configuration-speed acceleration method for a sequential circuit using a negative logic implementation Reviewed

    Retsu Moriwaki, Minoru Watanabe

    2011 International Conference on Space Optical Systems and Applications, ICSOS'11   213 - 217   2011.5

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    DOI: 10.1109/ICSOS.2011.5783670

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  • Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control Reviewed

    Mao Nakajima, Minoru Watanabe

    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS   4 ( 2 )   2011.5

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    DOI: 10.1145/1968502.1968506

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  • Reduction method of refresh cycles for a dynamic optically reconfigurable gate array Reviewed

    Y. Aoyama, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips   2011.4

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  • Programming Options for an Optical FPGA with Clockwise Dynamic Reconfigurability Reviewed

    F. Matsusaki, F. Kobayashi, A. Nagino, M. Watanabe

    International Conference on Innovative Computing and Communication and Asia-Pacific Conference on Information Technology and Ocean Engineering   2011.3

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  • MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays Reviewed

    Hironobu Morita, Minoru Watanabe

    RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS   6578   242 - 252   2011.3

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    DOI: 10.1007/978-3-642-19475-7_25

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  • A 144-configuration context MEMS optically reconfigurable gate array Reviewed

    Yuichiro Yamaji, Minoru Watanabe

    2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC)   237 - 241   2011

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    DOI: 10.1109/SOCC.2011.6085083

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  • A 64-context MEMS optically reconfigurable gate array Reviewed

    Yuichiro Yamaji, Minoru Watanabe

    2010 International Conference on Field-Programmable Technology   499 - 502   2010.12

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    DOI: 10.1109/FPT.2010.5681467

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  • Fiber remote configuration for an optically reconfigurable gate array with four configuration contexts Reviewed

    Yumiko Ueno, Minoru Watanabe

    OPTICS COMMUNICATIONS   283 ( 23 )   4614 - 4618   2010.12

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    DOI: 10.1016/j.optcom.2010.06.090

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  • Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability Reviewed

    D. Seto, M. Nakajima, M. Watanabe

    Applied Optics   49 ( 36 )   6986 - 6994   2010.12

  • Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability Reviewed

    Daisaku Seto, Mao Nakajima, Minoru Watanabe

    APPLIED OPTICS   49 ( 36 )   6986 - 6994   2010.12

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  • Multi-context programmable optically reconfigurable gate array using a silver-halide holographic memory Reviewed

    Shinya Kubota, Minoru Watanabe

    2010 IEEE/SICE International Symposium on System Integration: SI International 2010 - The 3rd Symposium on System Integration, SII 2010, Proceedings   431 - 435   2010.12

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    DOI: 10.1109/SII.2010.5708364

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  • Othello solver based on a soft-core MIMD processor array Reviewed

    Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe

    2010 International Conference on Field-Programmable Technology   511 - 514   2010.12

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    DOI: 10.1109/FPT.2010.5681470

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  • Background light effect of a dynamically reconfigurable vision-chip architecture Reviewed

    Retsu Moriwaki, Minoru Watanabe

    2010 IEEE/SICE International Symposium on System Integration: SI International 2010 - The 3rd Symposium on System Integration, SII 2010, Proceedings   426 - 430   2010.12

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    DOI: 10.1109/SII.2010.5708363

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  • A retention time improvement method for a MEMS dynamic optically reconfigurable gate array Reviewed

    Hironobu Morita, Minoru Watanabe

    2010 International Symposium on Micro-NanoMechatronics and Human Science: From Micro and Nano Scale Systems to Robotics and Mechatronics Systems, MHS 2010, Micro-Nano GCOE 2010, Bio-Manipulation 2010   257 - 261   2010.11

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    DOI: 10.1109/MHS.2010.5669547

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  • High-speed fiber-linked remote reconfiguration Reviewed

    Yumiko Ueno, Minoru Watanabe

    TENCON 2010 - 2010 IEEE Region 10 Conference   1203 - 1206   2010.11

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    DOI: 10.1109/TENCON.2010.5686374

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  • Template matching operations on a dynamically reconfigurable vision-chip architecture Reviewed

    Hironari Nakada, Minoru Watanabe

    2010 10th International Symposium on Communications and Information Technologies   1091 - 1096   2010.10

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    DOI: 10.1109/ISCIT.2010.5665152

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  • Formation of holographic memory using subwavelength grating mask for optically reconfigurable gate array Reviewed

    A. Ogiwara, M. Watanabe, T. Mabuchi, F. Kobayashi

    MICROOPTICS CONFERENCE   108 - 109   2010.10

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  • Development of optically reconfigurable gate arrays

    Minoru Watanabe

    International Symposium on Optical Memory   188 - 189   2010.10

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  • Fault tolerance of a holographic storage system Reviewed

    Takahiro Watanabe, Minoru Watanabe

    2010 10th International Symposium on Communications and Information Technologies   1126 - 1130   2010.10

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    DOI: 10.1109/ISCIT.2010.5665158

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  • Recovery method for a laser array failure on Dynamic Optically Reconfigurable Gate Arrays Reviewed

    Daisaku Seto, Minoru Watanabe

    2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems   411 - 419   2010.10

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    DOI: 10.1109/DFT.2010.55

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  • Programmable optically reconfigurable gate array using a silver-halide holographic memory including six configuration contexts Reviewed

    S. Kubota, M. Watanabe

    International Conference on Solid State Devices and Materials   67 - 68   2010.9

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  • Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array Reviewed

    Yuji Aoyama, Minoru Watanabe

    23rd IEEE International SOC Conference   243 - 247   2010.9

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    DOI: 10.1109/SOCC.2010.5784753

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  • Microelectromechanical Configuration of an Optically Reconfigurable Gate Array Reviewed

    Hironobu Morita, Minoru Watanabe

    IEEE JOURNAL OF QUANTUM ELECTRONICS   46 ( 9 )   1288 - 1294   2010.9

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    DOI: 10.1109/JQE.2010.2047378

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  • Relationship between alignment errors of optical components and power consumption in optoelectronic devices Reviewed

    Hironobu Morita, Minoru Watanabe

    2010 IEEE CPMT Symposium Japan, ICSJ10   2010.8

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    DOI: 10.1109/CPMTSYMPJ.2010.5680217

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  • Superimposing acceleration and optimization method of optical reconfiguration speed without any increase of laser power Reviewed

    Takayuki Mabuchi, Minoru Watanabe

    APPLIED OPTICS   49 ( 22 )   4120 - 4126   2010.8

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    DOI: 10.1364/AO.49.004120

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  • Formation of holographic memory for defect tolerance in optically reconfigurable gate arrays Reviewed

    APPLIED OPTICS   49 ( 22 )   4255 - 4261   2010.8

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  • A superimposing acceleration and optimization method of optical reconfiguration speed without any increase of laser power Reviewed

    APPLIED OPTICS   49 ( 22 )   4120 - 4126   2010.8

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  • Formation of holographic memory for defect tolerance in optically reconfigurable gate arrays Reviewed

    Akifumi Ogiwara, Minoru Watanabe, Takayuki Mabuchi, Fuminori Kobayashi

    APPLIED OPTICS   49 ( 22 )   4255 - 4261   2010.8

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    DOI: 10.1364/AO.49.004255

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  • Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array Reviewed

    Shinya Kubota, Minoru Watanabe

    2010 53rd IEEE International Midwest Symposium on Circuits and Systems   913 - 916   2010.8

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    DOI: 10.1109/MWSCAS.2010.5548776

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  • Excellent fault tolerance of a MEMS optically differential reconfigurable gate array Reviewed

    Hironobu Morita, Minoru Watanabe

    2010 International Conference on Optical MEMS and Nanophotonics, Optical MEMS and Nanophotonics 2010   133 - 134   2010.8

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    DOI: 10.1109/OMEMS.2010.5672149

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  • Dynamically reconfigurable vision-chip architecture Reviewed

    Maki Yasuda, Minoru Watanabe

    2010 International Conference on Field Programmable Logic and Applications, FPL 2010   508 - 512   2010.8

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    DOI: 10.1109/FPL.2010.101

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  • Binary MEMS optically reconfigurable gate array Reviewed

    Hironobu Morita, Minoru Watanabe

    Proceedings - 9th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2010   63 - 68   2010.8

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    DOI: 10.1109/ICIS.2010.89

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  • Programmable optically reconfigurable gate array using a silver-halide holographic memory Reviewed

    Shinya Kubota, Minoru Watanabe

    2010 15TH OPTOELECTRONICS AND COMMUNICATIONS CONFERENCE   370 - 371   2010.7

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  • Partial block-by-block reconfiguration for a dynamic optically reconfigurable gate array Reviewed

    D. Seto, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   232 - 237   2010.7

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  • A four-context optically reconfigurable gate array using a laser array attachment Reviewed

    T. Mabuchi, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies   143 - 147   2010.6

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  • Recovery method for a turn-off failure mode of a laser array on an ORGA Reviewed

    Daisaku Seto, Minoru Watanabe

    2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010   235 - 240   2010.6

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    DOI: 10.1109/AHS.2010.5546252

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  • Acceleration method of optical reconfigurations using analog configuration contexts Reviewed

    Yuji Aoyama, Minoru Watanabe

    2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010   304 - 308   2010.6

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    DOI: 10.1109/AHS.2010.5546242

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  • A 100-context optically reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS   2884 - 2887   2010.5

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    DOI: 10.1109/ISCAS.2010.5536965

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  • Configuration power reduction effect of an ORGA with analog configuration contexts Reviewed

    Y. Aoyama, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips   189   2010.4

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  • Power reduction method using negative logic implementation Reviewed

    R. Moriwaki, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips   192   2010.4

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  • MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment Reviewed

    Daisaku Seto, Minoru Watanabe

    RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS   5992   134 - 144   2010.3

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    DOI: 10.1007/978-3-642-12133-3_14

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  • Fiber remote configuration for a dynamic optically reconfigurable gate array Reviewed

    Yumiko Ueno, Minoru Watanabe

    2010 15TH OPTOELECTRONICS AND COMMUNICATIONS CONFERENCE (OECC)   Optoelectronics and Communications Conference   250 - 251   2010

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  • Optical buffering technique under a space radiation environment Reviewed

    Mao Nakajima, Minoru Watanabe

    OPTICS LETTERS   34 ( 23 )   3719 - 3721   2009.12

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    DOI: 10.1364/OL.34.003719

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  • Formation of volume holographic memory using liquid-crystal composites for optically reconfigurable gate array Reviewed

    A. Ogiwara, Y. Ochi, M. Miyake, M. Watanabe, T. Mabuchi, F. Kobayashi

    15th MICROOPTICS CONFERENCE   194 - 195   2009.10

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  • A Four-Context Optically Differential Reconfigurable Gate Array Reviewed

    Mao Nakajima, Minoru Watanabe

    JOURNAL OF LIGHTWAVE TECHNOLOGY   27 ( 20 )   4460 - 4470   2009.10

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    DOI: 10.1109/JLT.2009.2024173

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  • Scaling prospect of optically differential reconfigurable gate array VLSIs Reviewed

    Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING   60 ( 1-2 )   137 - 143   2009.8

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    DOI: 10.1007/s10470-008-9210-9

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  • Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI Reviewed

    Shinichi Kato, Minoru Watanabe

    Embedded Computer Systems: Architectures, Modeling, and Simulation   5657   139 - 148   2009.7

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    DOI: 10.1007/978-3-642-03138-0_15

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  • A multi-context programmable optically reconfigurable gate array

    S. Kubota, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   305 - 306   2009.7

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  • Defect tolerance of an optically reconfigurable gate array with a one-time writable volume holographic memory Reviewed

    Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara

    2009 NASA/ESA Conference on Adaptive Hardware and Systems   106 - 111   2009.7

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    DOI: 10.1109/AHS.2009.62

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  • A sixteen-context dynamic optically reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    2009 NASA/ESA Conference on Adaptive Hardware and Systems   120 - 125   2009.7

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    DOI: 10.1109/AHS.2009.64

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  • Optically reconfigurable gate array with a one-time writable holographic memory Reviewed

    T. Mabuchi, K. Miyashiro, M. Watanabe, A. Ogiwara

    International Conference on engineering of reconfigurable systems and algorithms   307 - 308   2009.7

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  • Alignment compensation method for an optically reconfigurable gate array Reviewed

    H. Morita, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   332 - 333   2009.7

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  • A 16-context optically reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    IEEE International Conference on Application-specific Systems, Architectures and Processors   227 - 230   2009.7

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    DOI: 10.1109/ASAP.2009.41

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  • A programmable dynamic optically reconfigurable gate array

    Shinya Kubota, Minoru Watanabe

    2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference   323 - 326   2009.6

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    DOI: 10.1109/newcas.2009.5290410

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  • Fast reconfiguration experiments of an optically differential reconfigurable gate array with nine configuration contexts Reviewed

    Mao Nakajima, Minoru Watanabe

    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5   2013 - 2016   2009.5

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    DOI: 10.1109/ISCAS.2009.5118187

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  • A Nine-context Programmable Optically Reconfigurable Gate Array with Semiconductor Lasers Reviewed

    Shinya Kubota, Minoru Watanabe

    GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI   269 - 273   2009.5

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    DOI: 10.1145/1531542.1531606

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  • Dynamic optically reconfigurable gate array with high defect tolerance Reviewed

    D. Seto, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips   171   171   2009.4

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  • Power reduction effect of an inversion/non-inversion dynamic optically reconfigurable gate array Reviewed

    S. Kato, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips   172   2009.4

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  • Fast Optical Reconfiguration of a Nine-Context DORGA Reviewed

    Mao Nakajima, Minoru Watanabe

    International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science   5453   123 - 132   2009.3

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    DOI: 10.1007/978-3-642-00641-8_14

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  • An estimation of an inversion/non-inversion dynamic optically reconfigurable gate array VLSI Reviewed

    S. Kato, M. Watanabe

    International Conference on Space Optical Systems and Applications   ICSOS2009 - 26   2009.2

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  • Configuration experiments for an optically reconfigurable gate array with a silver-halide holographic memory Reviewed

    M. Nakajima, M. Watanabe

    International Conference on Space Optical Systems and Applications   ICSOS2009 - 21   2009.2

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  • Triple-module redundancy for an optically reconfigurable gate array Reviewed

    D. Seto, M. Watanabe

    International Conference on Space Optical Systems and Applications   ICSOS2009 - 27   2009.2

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  • An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture Reviewed

    Daisaku Seto, Minoru Watanabe

    2009 Asia and South Pacific Design Automation Conference   117 - 118   2009.1

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    DOI: 10.1109/ASPDAC.2009.4796460

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  • Programmable Optically Reconfigurable Gate Array Architecture and its writer Reviewed

    KUBOTA S.

    APPLIED OPTICS   48 ( 2 )   302 - 308   2009.1

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  • Programmable optically reconfigurable gate array architecture and its writer Reviewed

    Shinya Kubota, Minoru Watanabe

    APPLIED OPTICS   48 ( 2 )   302 - 308   2009.1

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    DOI: 10.1364/AO.48.000302

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  • An inversion/non-inversion dynamic optically reconfigurable gate array VLSI Reviewed

    WATANABE M.

    World Scientific and Engineering Academy and Society Transactions on Circuits and Systems   8 ( 1 )   11 - 20   2009.1

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  • Fault tolerance analysis of MEMS holographic memory for DORGAs Reviewed

    Daisaku Seto, Minoru Watanabe

    20th Anniversary MHS 2009 and Micro-Nano Global COE - 2009 International Symposium on Micro-NanoMechatronics and Human Science   33 - 37   2009

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    DOI: 10.1109/MHS.2009.5352102

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  • A lens-less imaging holographic memory writer system for a programmable optically reconfigurable gate array Reviewed

    Shinya Kubota, Minoru Watanabe

    2009 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ELECTRONIC AND PHOTONIC DEVICES AND SYSTEMS (ELECTRO-2009)   112 - 115   2009

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    DOI: 10.1109/ELECTRO.2009.5441161

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  • Fault tolerance of a dynamic optically reconfigurable gate array with a one-time writable volume holographic memory Reviewed

    Takayuk Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara

    2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2   917 - +   2009

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    DOI: 10.1109/MWSCAS.2009.5235916

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  • A multi-context programmable optically reconfigurable gate array without a beam splitter Reviewed

    Shinya Kubota, Minoru Watanabe

    2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2   971 - 974   2009

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    DOI: 10.1109/MWSCAS.2009.5235928

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  • MEMS OPTICALLY RECONFIGURABLE GATE ARRAY Reviewed

    Hironobu Morita, Minoru Watanabe

    FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS   511 - 515   2009

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    DOI: 10.1109/FPL.2009.5272445

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  • 36-Context dynamic optically reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    2009 IEEE/SICE International Symposium on System Integration: SI International 2008 - The 2nd Symposium on System Integration   19 - 23   2009

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    DOI: 10.1109/SI.2009.5384563

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  • An optical configuration acceleration method using negative logic implementation Reviewed

    Retsu Moriwaki, Minoru Watanabe

    2009 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ELECTRONIC AND PHOTONIC DEVICES AND SYSTEMS (ELECTRO-2009)   552 - 555   2009

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    DOI: 10.1109/ELECTRO.2009.5441043

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  • Fiber remote configuration for an optically reconfigurable gate array Reviewed

    Yumiko Ueno, Minoru Watanabe

    2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009)   460 - 463   2009

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    DOI: 10.1109/SOCDC.2009.5423925

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  • MEMS inversion/non-inversion dynamic optically reconfigurable gate array Reviewed

    Daisaku Seto, Minoru Watanabe

    2009 IEEE/SICE International Symposium on System Integration: SI International 2008 - The 2nd Symposium on System Integration   24 - 29   2009

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    DOI: 10.1109/SI.2009.5384560

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  • MEMS Optically Differential Reconfigurable Gate Array Reviewed

    Hironobu Morita, Minoru Watanabe

    2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009)   119 - 122   2009

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    DOI: 10.1109/EDSSC.2009.5394174

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  • A 36-context optically reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009)   412 - 415   2009

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    DOI: 10.1109/SOCDC.2009.5423866

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  • A 13.75 ns holographic reconfiguration of an optically differential reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing   852 - 855   2009

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    DOI: 10.1109/IIH-MSP.2009.250

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  • Allowable alignment errors of components in an optically reconfigurable gate array Reviewed

    H. Morita, M. Watanabe

    International Topical Meeting on Information Photonics   50 - 51   2008.11

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  • Multi-speed configuration for ORGAs Reviewed

    M. Nakajima, M. Watanabe

    International Topical Meeting on Information Photonics   166 - 167   2008.11

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  • Liquid crystal holographic configurations for ORGAs Reviewed

    YAMAGUCHI N.

    APPLIED OPTICS   47 ( 26 )   4692 - 4700   2008.10

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  • Liquid crystal holographic configurations for optically reconfigurable gate arrays Reviewed

    Naoki Yamaguchi, Minoru Watanabe

    APPLIED OPTICS   47 ( 26 )   4692 - 4700   2008.9

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  • Optical configuration using a silver-halide holographic memory including four configuration contexts Reviewed

    D. Seto, M. Watanabe

    International Conference on Solid State Devices and Materials   116 - 117   2008.9

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  • A 770ns holographic reconfiguration of a four-context DORGA Reviewed

    M. Nakajima, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   289 - 292   2008.7

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  • MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration ? a 6502 Perspective- Reviewed

    F. Kobayashi, Y. Morikawa, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   222 - 228   2008.7

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  • A dynamic optically reconfigurable gate array - Perfect emulation Reviewed

    Daisaku Seto, Minoru Watanabe

    IEEE JOURNAL OF QUANTUM ELECTRONICS   44 ( 5-6 )   493 - 500   2008.5

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    DOI: 10.1109/JQE.2008.916705

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  • Analysis of retention time under multi-configuration on a DORGA Reviewed

    Daisaku Seto, Minoru Watanabe

    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS   131 - 134   2008

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    DOI: 10.1109/SOCC.2008.4641495

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  • A 9-context Optically Reconfigurable Gate Array Reviewed

    Takayuki Mabuchi, Minoru Watanabe

    ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3   1 - 4   2008

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    DOI: 10.1109/SOCDC.2008.4815560

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  • A double or triple module redundancy model exploiting dynamic reconfigurations Reviewed

    Kouji Shinohara, Minoru Watanabe

    PROCEEDINGS OF THE 2008 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS   114 - 121   2008

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    DOI: 10.1109/AHS.2008.67

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  • Multi-optical configuration using spreading beams Reviewed

    Naoki Yamaguchi, Minoru Watanabe

    2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2   386 - 389   2008

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    DOI: 10.1109/MWSCAS.2008.4616817

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  • Optical configuration of an 11,424 gate-count dynamic optically reconfigurable gate array using a VCSEL Reviewed

    Daisaku Seto, Minoru Watanabe

    2008 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION   95 - 99   2008

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    DOI: 10.1109/SI.2008.4770433

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  • A 937.5 ns multi-context holographic configuration with a 30-75 mu s retention time Reviewed

    Mao Nakajima, Daisaku Seto, Minoru Watanabe

    2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8   3502 - 3507   2008

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    DOI: 10.1109/IPDPS.2008.4536539

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  • Dynamic holographic reconfiguration on a four-context ODRGA Reviewed

    Mao Nakajima, Minoru Watanabe

    2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS   173 - 178   2008

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    DOI: 10.1109/ASAP.2008.4580174

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  • Inversion/non-inversion dynamic optically reconfigurable gate array Reviewed

    Minoru Watanabe, Mao Nakajima

    PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS   249 - +   2008

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  • Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI Reviewed

    Shinichi Kato, Minoru Watanabe

    PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY   377 - 380   2008

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    DOI: 10.1109/FPT.2008.4762422

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  • An 11,424-gate dynamic optically reconfigurable gate array VLSI Reviewed

    Mao Nakajima, Minoru Watanabe

    PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY   293 - 296   2008

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  • An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays Reviewed

    Takayuki Mabuchi, Minoru Watanabe

    PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY   289 - 292   2008

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    DOI: 10.1109/FPT.2008.4762400

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  • An acceleration and optimization method for optical reconfiguration Reviewed

    Minoru Watanabe, Naoki Yamaguchi

    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS   607 - 612   2008

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    DOI: 10.1109/VLSI.2008.26

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  • A dynamic optically reconfigurable gate array with a silver-halide holographic memory Reviewed

    Daisaku Seto, Minoru Watanabe

    Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008   511 - 514   2008

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    DOI: 10.1109/ISVLSI.2008.94

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  • Defect tolerance of holographic configurations in ORGAs Reviewed

    Kouji Shinohara, Minoru Watanabe

    2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8   3488 - 3495   2008

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    DOI: 10.1109/IPDPS.2008.4536537

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  • An optical reconfiguration system with four contexts Reviewed

    Naoki Yamaguchi, Minoru Watanabe

    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS   601 - 606   2008

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    DOI: 10.1109/VLSI.2008.27

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  • Programmable Optically Reconfigurable Gate Array Architecture using a PAL-SLM Reviewed

    Shinya Kubota, Minoru Watanabe

    2008 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION   100 - 104   2008

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    DOI: 10.1109/SI.2008.4770434

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  • Optimization of reconfiguration speed control bits for an Optically Reconfigurable Gate Array Reviewed

    M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms   2007.7

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  • 272 gate count optically differential reconfigurable gate array VLSI Reviewed

    M. Watanabe, T. Shiki, F. Kobayashi

    International Conference on engineering of reconfigurable systems and algorithms   2007.7

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  • Power Consumption Reduction Method of Dynamic Optically Reconfigurable Gate Array VLSIs Reviewed

    M. Watanabe, F. Kobayashi

    IEEE Symposium on Low-Power and High-Speed Chips   145   2007.4

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  • Asynchronous Sampling Rate Converter by Fourier Interpolation in the Time Domain Reviewed

    INOUE Manabu, KOBAYASHI Fuminori, WATANABE Minoru

    Transactions of the Society of Instrument and Control Engineers   43 ( 2 )   145 - 152   2007.2

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    A time-domain SRC, sampling rate converter, using Fourier interpolation to achieve less gate count than in frequency domain is proposed. The new SRC is implemented in 1/150 of the circuit size of conventional SRC with moderate performance using filters. It can also be used as back-end for filter-type SRC to achieve high performance efficiently.

    DOI: 10.9746/ve.sicetr1965.43.145

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  • Superimposing technique of reconfiguration contexts Reviewed

    M. Watanabe, F. Kobayashi

    ACM/SIGDA International Symposium on Field Programmable Gate Arrays   227 - 228   2007.2

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  • Superimposing technique of reconfiguration contexts for increasing reconfiguration speed Reviewed

    M. Watanabe, F. Kobayashi

    Mobile Computing Hardware Architectures Design Symposium   2007.1

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  • A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    PROCEEDINGS OF THE ASP-DAC 2007   124 - +   2007

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    DOI: 10.1109/ASPDAC.2007.357972

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  • Optically differential reconfigurable gate array Reviewed

    Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi

    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS   90 ( 11 )   132 - 139   2007

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    DOI: 10.1002/ecjb.20420

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  • Reconfiguration performance analysis of a dynamic optically reconfieurable gate array architecture Reviewed

    Daisaku Seto, Minoru Watanabe

    ICFPT 2007: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS   265 - 268   2007

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    DOI: 10.1109/FPT.2007.4439262

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  • Reconfigurations of a dynamic optically reconfigurable architecture under a constant laser exposure Reviewed

    Minoru Watanabe, Daisaku Seto

    EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS   405 - 408   2007

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    DOI: 10.1109/EDSSC.2007.4450148

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  • A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays Reviewed

    Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi

    Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM   2007

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    DOI: 10.1109/IPDPS.2007.370391

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  • Holographic memory reconfigurable VLSI Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11   401 - 404   2007

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    DOI: 10.1109/ISCAS.2007.378474

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  • An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI Reviewed

    Minoru Watanabe

    20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS   75 - 78   2007

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    DOI: 10.1109/SOCC.2007.4545430

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  • DORGA holographic memory architecture Reviewed

    Minoru Watanabe, Shoutarou Fukagawa, Fuminori Kobayashi

    2007 INTERNATIONAL CONFERENCE ON MICROELECTRONICS   222 - +   2007

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    DOI: 10.1109/ICM.2007.4497743

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  • Scaling rule of optically differential reconfigurable gate array VLSIs Reviewed

    Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

    2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3   101 - 104   2007

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    DOI: 10.1109/MWSCAS.2007.4488553

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  • A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array Reviewed

    Mao Nakajima, Minoru Watanabe

    ICFPT 2007: INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS   297 - 300   2007

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    DOI: 10.1109/FPT.2007.4439270

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  • Manufacturing-defect tolerance analysis of optically reconfigurable gate arrays, Reviewed

    M. Watanabe, F. Kobayashi

    World Scientific and Engineering Academy and Society Transactions on Signal Processing   11 ( 2 )   1457 - 1464   2006.11

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  • Characteristics Improvement of PLLs Using Phase Interpolation Reviewed

    INOUE Manabu, KOBAYASHI Fuminori, WATANABE Minoru

    Transactions of the Society of Instrument and Control Engineers   42 ( 10 )   1175 - 1180   2006.10

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    Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propose a new PLL using phase interpolation based on a counter with a high-frequency internal clock. The PLL can compare phases more than once a cycle of reference and input, thus reducing jitter and improving responsiveness. Also we optimize implementation of phase interpolation, to improve circuit size and maximum operating frequency, even if the circuit compares phases many time a cycle.

    DOI: 10.9746/sicetr1965.42.1175

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  • A logic synthesis and place and route environment for ORGAs Reviewed

    M. Watanabe, F. Kobayashi

    International Conference on engineering of reconfigurable systems and algorithms   237 - 238   2006.7

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  • A High-Density Dynamic Optically Reconfigurable Gate Array VLSI Reviewed

    WATANABE Minoru, KOBAYASHI Fuminori

    The IEICE transactions on information and systems   J89-D ( 6 )   1082 - 1090   2006.6

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    Other Link: http://hdl.handle.net/10228/4570

  • Shield effect analysis for a gate array on an Optically Reconfigurable Gate Array Reviewed

    M. Watanabe, F. Kobayashi

    International Conference on engineering of reconfigurable systems and algorithms   239 - 240   2006.6

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  • Differential Reconfiguration Architecture suitable for a Holographic Memory Reviewed

    M. Watanabe, M. Miyano, F. Kobayashi

    International Conference on engineering of reconfigurable systems and algorithms   198 - 203   2006.6

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  • Dynamic optically reconfigurable gate array Reviewed

    M Watanabe, F Kobayashi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   45 ( 4B )   3510 - 3515   2006.4

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    DOI: 10.1143/JJAP.45.3510

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  • A 1,632 gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS   3985   268 - 273   2006

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  • A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays Reviewed

    Minoru Watanabe, Ryuji Fujime, Fuminori Kobayashi

    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II   94 - +   2006

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    DOI: 10.1109/MWSCAS.2006.382216

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  • Over-sampling PLL for low-jitter and responsive clock synchronization Reviewed

    Manabu Inoue, Furninori Kobayashi, Minoru Watanabe

    2006 INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES,VOLS 1-3   809 - +   2006

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    DOI: 10.1109/ISCIT.2006.339842

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  • Optically Reconfigurable Gate Arrays vs. ASICs Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS   1164 - +   2006

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    DOI: 10.1109/APCCAS.2006.342348

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  • Hybrid sample rate converter with 110dB SNR and 1/10 less logic gates Reviewed

    Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe

    2006 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY   432 - 436   2006

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    DOI: 10.1109/EIT.2006.252121

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  • Reconfiguration speed adjustment technique for ORGAs with a holographic memory Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS   917 - 922   2006

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    DOI: 10.1109/FPL.2006.311344

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  • An optically differential reconfigurable gate array with a holographic memory Reviewed

    Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi

    20th International Parallel and Distributed Processing Symposium, IPDPS 2006   2006   2006

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    DOI: 10.1109/IPDPS.2006.1639478

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  • Power consumption advantage of a dynamic optically reconfigurable gate array Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    20th International Parallel and Distributed Processing Symposium, IPDPS 2006   2006   2006

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    DOI: 10.1109/IPDPS.2006.1639490

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  • A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 mu m CMOS technology Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS   108 - +   2006

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  • A 51,272-gate-count Dynamic Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology Reviewed

    M. Watanabe, F. Kobayashi

    International Conference on Solid State Devices and Materials,   336 - 337   2005.9

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  • Fourier/Filter Hybrid Sampling Rate Converter Reviewed

    M. Inoue, F. Kobayashi, M. Watanabe

    SICE Annual Conference   176 - 179   2005.8

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  • A dynamic optically reconfigurable gate array using dynamic method Reviewed

    M. Watanabe, F. Kobayashi

    International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science   50 - 58   2005.2

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  • An Optically Differential Reconfigurable Gate Array VLSI chip with a dynamic reconfiguration circuit Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005   2005   145   2005

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    DOI: 10.1109/IPDPS.2005.105

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  • A 16,000-gate-count optically reconfigurable gate array in a standard 0.35 mu m CMOS technology Reviewed

    M Watanabe, F Kobayashi

    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS   1214 - 1217   2005

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    DOI: 10.1109/ISCAS.2005.1464812

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  • A zero-overhead dynamic optically reconfigurable gate array Reviewed

    M Watanabe, F Kobayashi

    FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS   297 - 298   2005

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    DOI: 10.1109/FPT.2005.1568569

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  • An improved dynamic optically reconfigurable gate array Reviewed

    M Watanabe, F Kobayashi

    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS   136 - 141   2005

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    DOI: 10.1109/ISVLSI.2005.16

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  • A 16,000-gate-count Optically Reconfigurable Gate Array in a standard 0.35μm CMOS technology Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    Proceedings - IEEE International Symposium on Circuits and Systems   1213 - 1217   2005

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    DOI: 10.1109/ISCAS.2005.1464812

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  • Rapid reconfiguration of an optically differential reconfigurable gate array with pulse lasers Reviewed

    M Miyano, M Watanabe, F Kobayashi

    FPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings   287 - 288   2005

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    DOI: 10.1109/FPT.2005.1568564

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  • Optically differential reconfigurable gate array using an optical system with VCSELs Reviewed

    M Miyano, M Watanabe, F Kobayashi

    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS   274 - 275   2005

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    DOI: 10.1109/ISVLSI.2005.54

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  • Sampling rate conversion by Fourier interpolation Reviewed

    M Inoue, F Kobayashi, M Watanabe

    SICE 2004 ANNUAL CONFERENCE, VOLS 1-3   1613 - 1616   2004

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  • An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation Reviewed

    M Watanabe, F Kobayashi

    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS   735 - 738   2004

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    DOI: 10.1109/ICVD.2004.1261015

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  • Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors Reviewed

    M Watanabe, F Kobayashi

    ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS   311 - 311   2004

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  • An optical reconfiguration circuit for optically reconfigurable gate arrays Reviewed

    M Watanabe, F Kobayashi

    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS   529 - 532   2004

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    DOI: 10.1109/MWSCAS.2004.1354044

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  • Testing method for optical connections using gate array structure in ORGAs Reviewed

    M Watanabe, F Kobayashi

    ERSA '04: THE 2004 INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS   299 - 299   2004

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  • A high-density optically reconfigurable gate array using dynamic method Reviewed

    M Watanabe, F Kobayashi

    FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS   3203   261 - 269   2004

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    DOI: 10.1007/978-3-540-30117-2_28

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  • An optically differential reconfigurable gate array using a 0.18 mu m CMOS process Reviewed

    M Watanabe, F Kobayashi

    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS   281 - 284   2004

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    DOI: 10.1109/SOCC.2004.1362436

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  • An Optically Reconfigurable Gate Array VLSI with Partial Reconfiguration Capability Reviewed

    WATANABE Minoru, KOBAYASHI Fuminori

    The Transactions of the Institute of Electronics, Information and Communication Engineers C   J86-C ( 8 )   869 - 877   2003.8

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  • FPGA implementation of Finite Physical Quantity Neural Network Reviewed

    T. Sotohebo, M. Watanabe, F. Kobayashi

    Journal of Robotics and Mechatronics   15 ( 2 )   136 - 142   2003.4

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  • Configuration for an optically differential reconfigurable gate array Reviewed

    M Miyano, M Watanabe, F Kobayashi

    SICE 2003 ANNUAL CONFERENCE, VOLS 1-3   1984 - 1987   2003

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  • A finite physical quantity neural network VLSI with a learning capability Reviewed

    M Watanabe, F Kobayashi

    SICE 2003 ANNUAL CONFERENCE, VOLS 1-3   1988 - 1991   2003

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  • Design of an Optically Differential Reconfigurable Gate Array VLSI chip with optically and electrically controlled logic blocks Reviewed

    M Watanabe, F Kobayashi

    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS   287 - 288   2003

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    DOI: 10.1109/SOC.2003.1241524

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  • An optically differential reconfigurable gate array with a dynamic reconfiguration circuit Reviewed

    Minoru Watanabe, Fuminori Kobayashi

    Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003   2003

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    DOI: 10.1109/IPDPS.2003.1213349

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  • A neural network model using finite physical quantities and its realization on LSIs Reviewed

    M Watanabe, F Kobayashi

    SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5   1863 - 1864   2002

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    DOI: 10.1109/SICE.2002.1196607

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  • Motion image compression circuit using the silicon retina as active sensor Reviewed

    M Amagasaki, F Kobayashi, M Watanabe, T Yagi

    SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5   1859 - 1860   2002

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    DOI: 10.1109/SICE.2002.1196605

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  • An optically differential reconfigurable gate array and its power consumption estimation Reviewed

    M Watanabe, F Kobayashi

    2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS   197 - 202   2002

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    DOI: 10.1109/FPT.2002.1188682

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  • A compressed implementation of neural network with finite physical quantities on FPGAs Reviewed

    T Sotohebo, M Watanabe, F Kobayashi

    SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5   1861 - 1862   2002

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    DOI: 10.1109/SICE.2002.1196606

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  • ニューラルネットワークVLSI

    渡邊 実, 小林 史典

    計測と制御 = Journal of the Society of Instrument and Control Engineers   40 ( 12 )   893 - 896   2001.12

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    DOI: 10.11499/sicejl1962.40.893

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    Other Link: https://jlc.jst.go.jp/DN/JALC/00155220780?from=CiNii

  • An optical energy neural networkwith self-organizing capability Reviewed

    M. Watanabe, A. Itoh, F. Kobayashi

    17th annual conference of International Conference on Circuits/Systems Computers and Communications   2   1292 - 1295   2001.7

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  • DIGITAL ASSOCIATIVE MEMORY NEURAL-NETWORK WITH OPTICAL LEARNING CAPABILITY Reviewed

    M WATANABE, J OHTSUBO

    OPTICS COMMUNICATIONS   113 ( 1-3 )   31 - 38   1994.12

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    DOI: 10.1016/0030-4018(94)90588-6

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Books

  • FPGAの原理と構成

    渡邊 実( Role: Joint author)

    オーム社  2016.4 

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  • High-Performance Computing Using FPGAs

    ( Role: Joint author)

    Springer  2013.6 

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  • 「高速な木探索回路を実現する」,ディジタル・デザイン・テクノロジ

    渡邊 実( Role: Joint author)

    CQ出版  2012.10 

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  • Advances in Solid State Circuit Technologies

    ( Role: Joint author)

    IN-TECH  2010.4 

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  • Parallel and Distributed Computing

    ( Role: Joint author)

    IN-TECH  2010.1 

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  • New Developments in Liquid Crystals

    ( Role: Joint author)

    IN-TECH  2009.11 

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MISC

  • [招待講演]福島第一原子力発電所の廃炉向け耐放射線デバイスの開発状況について Invited

    渡邊 実

    ムーンショット研究会「スケーラブルな高集積量子誤り訂正システムの開発」   2025.5

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  • [特別招待講演]福島第一原子力発電所の廃炉向け耐放射線FPGAの開発状況について Invited

    渡邊 実

    電子情報通信学会,コミュニケーションシステム研究会   2025.3

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  • Clock distribution method on FPGAs without any dedicated clock tree

    小倉歩武, 渡邊実, 渡邊誠也

    電子情報通信学会技術研究報告(Web)   124 ( 329(VLD2024 76-102) )   2025

  • Radiation degradation evaluation of the configuration circuit on a dynamic optically reconfigurable gate array

    大橋聖司, 渡邊実, 渡邊誠也

    電子情報通信学会技術研究報告(Web)   124 ( 329(VLD2024 76-102) )   2025

  • 耐放射線光再構成型ゲートアレイのバッテリー駆動に向けた性能評価

    島村侑希, 渡邊 実, 渡邊誠也

    第68回宇宙科学技術連合講演会   2024.11

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  • 耐放射線プログラマブルデバイス向けJTAG

    永峰直樹, 渡邊 実, 渡邊誠也

    第68回宇宙科学技術連合講演会   2024.11

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  • リペアラブル耐放射線FPGAへの回路実装

    細谷亮太, 渡邊 実, 渡邊誠也

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  • 光再構成型ゲートアレイVLSIにおけるスイッチングマトリクスを利用したクロック分配法

    小倉歩武, 渡邊 実, 渡邊誠也

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  • 脈流電圧で動作可能な光再構成型ゲートアレイ

    辻野 将, 渡邊 実, 渡邊誠也

    情報フォトニクス研究討論会   2024.7

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  • 光再構成型ゲートアレイの三重構成回路の実証

    米地巨豊, 渡邊 実, 渡邊誠也

    情報処理学会 第86回全国大会   1A-03 - 1A-03   2024.3

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  • FPGAに実装する耐放射性AI

    DING HAITAO, 渡邊 実, 渡邊 誠也

    第9回次世代次世代イニシアティブ廃炉技術カンファレンス   2024.3

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  • 異なるレーザ波長を用いたレーザ干渉露光光学系の構築による液晶・高分子複合体材料へのホログラフィックメモリ作製

    荻原 昭文, 渡邊 実

    応用物理学会春季学術講演会   2024.3

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  • 光再構成アーキテクチャを用いたウエハースケールVLSIの実現性

    高田睦士, 渡邊 実, 渡邊 誠也

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  • 液晶ホログラフィックメモリを持つ耐放射線光再構成型ゲートアレイへの並列構成試験

    後藤彩絵, 渡邊 実, 荻原昭文, 渡邊誠也

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2023.11

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  • MISCプロセッサの光再構成型ゲートアレイVLSIへの実装と最大動作周波数評価

    今井颯真, 渡邊 実, 渡邊誠也

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2023.11

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  • 光再構成型ゲートアレイVLSIのγ線による放射線劣化特性の評価

    山田 果歩, 渡邊 実, 渡邊 誠也

    第67回宇宙科学技術連合講演会   2023.10

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  • 光再構成型ゲートアレイの放射線試験向けモニタリングシステム

    関岡空己, 渡邊 実, 渡邊誠也

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2023.9

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  • 水晶発振器を用いない光再構成型ゲートアレイへの順序回路の実装

    高月信太朗, 渡邊 実, 渡邊誠也

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2023.9

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  • 光再構成型ゲートアレイの低電圧動作評価

    島村侑希, 渡邊 実, 渡邊誠也

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  • マルチコンテキストスクラビングによる順序回路実装

    安藤 駆, 渡邊 実, 渡邊誠也

    情報処理学会第85回全国大会   2023.3

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  • 液晶・高分子材料への波長多重記録によるホログラフィックメモリの作成

    荻原昭文, 渡邊 実

    第70回応用物理学会春季学術講演会   03-172   2023.3

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  • 脈流電源を用いた光再構成型ゲートアレイ

    辻野 将, 渡邊 実, 渡邊誠也

    情報処理学会第85回全国大会   2023.3

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  • 耐放射線イメージセンサのトータルドーズ耐性

    第66回宇宙科学技術連合講演会   2022.11

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  • 宇宙機器向けマルチコンテキストスクラビング

    安藤 駆, 渡邊 実, 渡邊 誠也

    第66回宇宙科学技術連合講演会   2022.11

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  • パネルタイトル「FPGAデザインコンテスト」,パネルディスカッション 「自律型モビリティシステムとドメイン特化型ハードウェアやFPGA技術の未来」 Invited

    渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2022.9

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  • 光再構成型ゲートアレイVLSIの290 Mradまでのトータルドーズ耐性試験

    山田 果歩, 岡崎 武志, 渡邊 実, 渡邊 誠也

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2022.6

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  • 完全並列構成が可能な光再構成型ゲートアレイVLSI

    後藤 彩絵,渡邊 実,渡邊 誠也

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)   2022.6

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  • FSLによる3値化CNNのFPGA実装

    尾崎 洸人, 渡邊 誠也, 名古屋 彰, 渡邊 実

    パルテノン研究会   2021.12

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  • Performance analysis of Mono Instruction Set Computer using VTR

    117 ( 221 )   43 - 46   2017.9

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  • Hardware acceleration for holographic memories on optically reconfigurable gate arrays

    117 ( 221 )   31 - 36   2017.9

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  • High-speed optically scrubbing using a multi-context

    117 ( 46 )   105 - 109   2017.5

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  • Optically reconfigurable gate array with an optical input

    116 ( 53 )   67 - 70   2016.5

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  • Fault tolerance of an inversion configuration method on an optically configurable gate array

    115 ( 343 )   5 - 8   2015.12

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  • High-speed scrubbing on optically reconfigurable gate array

    115 ( 109 )   131 - 134   2015.6

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  • Radiation tolerance of a holographic memory part on an optically reconfigurable gate array

    MORIWAKI Retsu, ITO Hiroyuki, MAEKAWA Akira, WATANABE Minoru, OGIWARA Akifumi

    IEICE technical report   114 ( 223 )   19 - 22   2014.9

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    Optically reconfigurable gate arrays (ORGAs) have been developed as a type of dynamically reconfigurable gate array. ORGAs have a high-speed reconfiguration capability along with numerous reconfiguration contexts. Moreover, ORGAs have a high fault tolerance for radiation. Thig paper presents radiation tolerance of a holographic memory of an ORGA by using a gamma radiation source.

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  • Parallel-operation-oriented optically reconfigurable gate array

    FUJIMORI Takumi, WATANABE Minoru

    IEICE technical report   114 ( 223 )   47 - 50   2014.9

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    We have been developing Optically Reconfigurable Gate Amays (ORGAs) to realize a faster dynamic reconfiguration than that of the other reconfigurable devices. An ORGA consists of a laser array, a holographic memory and a gate array VLSI as a three-layer structure. Such ORGA can achieve faster reconfiguration than Field Programmable Gate Anays (FPGAs) by using a two-dimensional optical connection. In addition, the ORGA can have a lot of configuration contexts inside a holographic memory. On the other hand, we have proposed a parallel-operation-oriented FPGA architecture sharing a common configuration memory. This paper presents a new parallel-operation-oriented optically reconfigurable gate array.

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  • Dependability-increasing demonstration of an optically differential reconfigurable gate array

    SEO Masato, WATANABE Minoru

    IEICE technical report   113 ( 325 )   83 - 86   2013.11

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    Recently, FPGAs are widely used in various systems. However, an FPGA is vulnerable to effects of high-energy charged particles so that it is rarely used for space applications under a radiation-rich space environment. Therefore, we have been developing an Optically Reconfigurable Gate Array (ORGA). An Optically Reconfigurable Gate Array has a high radiation tolerance. This paper presents a more advanced radiation tolerant method by using differential reconfiguration scheme.

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  • A radiation tolerance improvement for optically reconfigurable gate array using a negative logic Implementation

    57   5p   2013.10

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  • Optically reconfigurable gate array with a variable spot-size configuration context

    AKAGI Kouta, WATANABE Minoru

    IEICE technical report   113 ( 221 )   109 - 112   2013.9

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) to realize a faster dynamic reconfiguration than that of the other reconfigurable devices by using optical components. An ORGA consists of a laser array, a holographic memory, and a gate array-VLSI as a three-layer structure. An ORGA can achieve fast reconfiguration by using a two-dimensional optical connection. In addition, an ORGA can have a lot of configuration contexts inside a holographic memory. Therefore, an ORGA can realize a large virtual gate by exploiting a high-speed dynamic reconfiguration. This paper proposes a more advanced variable spot-size configuration in order to increase its gate density and presents an evaluation result.

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  • An optically reconfigurable gate array using a temperature dependable holographic memory

    MORIWAKI Retsu, WATANABE Minoru, OGIWARA Akifumi

    IEICE technical report   113 ( 52 )   37 - 40   2013.5

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    Optically reconfigurable gate arrays (ORGAs) have been developed as a type of dynamically reconfigurable gate array that can achieve a high-speed reconfiguration and numerous reconfiguration contexts. An ORGA consists of laser array, holographic memory, and an optically reconfigurable gate array VLSI. An ORGA has a radiation tolerance. However, a previous polymer-dispersed liquid crystal holographic memory cannot work at a high-temperature condition. So, we have fabricated a temperature-tolerant holographic memory using a holographic polymer-dispersed liquid crystal. This paper presents a new optically reconfigurable gate array using the temperature-tolerant holographic memory.

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  • D-18-3 A TWO CONTEXT RECONFIGURATION ON A MEMS OPTTICALLY RECONFIGURABLE GATE ARRAY

    Yamaji Yuichiro, Watanabe Minoru

    Proceedings of the IEICE General Conference   2013 ( 1 )   197 - 197   2013.3

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  • 0.18μm CMOS process dynamic optically reconfigurable gate array VLSI

    KUBOTA Takayuki, WATANABE Minoru

    IEICE technical report   112 ( 325 )   23 - 27   2012.11

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) to realize a faster dynamic reconfiguration than that of the other reconfigurable devices. An ORGA consists of laser arrays, a holographic memory and gate arrays-VLSI as a three-layer structure. An ORGA can achieve fast reconfiguration by using a two-dimensional optical connection. In addition, the ORGA can have a lot of configuration contexts inside a holographic memory. Therefore, an ORGA can realize a large virtual gate by exploiting a high-speed dynamic reconfiguration. This paper presents evaluation results of a newly fabricated 0.18μm CMOS process dynamic ORGA.

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  • A 16-gray-scale image recognition on a dynamically reconfigurable vision

    KAMIKUBO Yuki, WATANABE Minoru, KAWAHITO Shoji

    IEICE technical report. Signal processing   112 ( 246 )   19 - 23   2012.10

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    Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such system requires many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Realizing such high-speed real-time image recognition operation is difficult because of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigurable vision architecture has been developed. This paper presents a more advanced dynamically reconfigurable vision architecture that can recognize 16-gray-scale images.

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  • Power consumption analysis of a mono instruction set computer architecture

    ITO Hiroyuki, WATANABE Minoru

    112 ( 247 )   35 - 38   2012.10

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  • Superimposing configuration acceleration method of an optically reconfigurable gate array including a speed adjustment bit

    YOZA Takashi, WATANABE Minoru

    IEICE technical report   112 ( 203 )   67 - 71   2012.9

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    In recent years, demand fbr realizing robust embedded devises used in space is increasing daily. Under a space environment, embedded devices suffer from many high-energy charged particles. Therefore, we have been developing optically reconfigurable gate arrays (ORGAs) which are very robust against such high-energy charged particles. Up to now, we have demonstrated that a configuration speed adjustment method can optimize each reconfiguration speed of ORGAs. However, we have never confirmed whether the method can function correctly when configuration contexts are superimposed. Therefor, this paper demonstrates that the superimposing configuration acceleration method including a speed adjustment bit can be used.

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  • Gray-level image detection of a dynamically reconfigurable vision-chip architecture

    KAMIKUBO Yuki, WATANABE Minoru, KAWAHITO Shoji

    IEICE technical report   112 ( 203 )   85 - 88   2012.9

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    Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such system requires many template images to be read out dynamically from memory. They must then be sent to a processor quickly. However, realizing such high-speed real-time image recognition operation is difficult because of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigurable vision architecture that can recognize binarized images has been presented.however, to date, dynamically reconfigurable vision architecture that can recognize gray-level images has never been presented. Therefore, this paper presents an experimentation related to a more advanced dynamically reconfigurable vision architecture that can recognize 4-gradation gray-level images.

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  • New optically reconfigurable gate array VLSI to enable a negative logic implementation

    MORIWAKI Retsu, WATANABE Minoru

    IEICE technical report. Dependable computing   111 ( 462 )   43 - 47   2012.2

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    Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed reconfiguration and to provide numerous reconfiguration contexts. For an acceleration method by reducing the number of bright bits, we have developed a new ORGA VLSI-chip. This paper presents reconfiguration acceleration results on the new ORGA-VLSI chip.

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  • New optically reconfigurable gate array VLSI to enable a negative logic implementation

    2012 ( 8 )   1 - 5   2012.2

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  • New optically reconfigurable gate array VLSI to enable a negative logic implementation

    2012 ( 8 )   1 - 5   2012.2

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  • Recovery experiments from a laser array failure in an optically reconfigurable gate array using a reconfiguration speed-adjustment analog bit

    YOZA Takashi, WATANABE Minoru

    IEICE technical report   111 ( 399 )   157 - 161   2012.1

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    In recent years, developments of embedded devices are required for space satellites, space rockets, and so on. However, a device under a space radiation environment needs to have a robustness for such high-energy charged particles. So, we have been developing optically reconfigurable gate arrays (ORGAs) which have a robust ability for such high-energy charged particles because their configuration contexts are stored in a holographic memory. Up to now, we have proposed a configuration speed adjustment method for ORGAs that optimizes each reconfiguration speed. However, we have never confirmed whether the method can be used or not under a turn-on laser failure. Therefore, this paper demonstrates that the configuration speed adjustment method can be used under such a failure mode.

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  • 0.18μm process Optically Reconfigurable Gate Array VLSI

    WATANABE Takahiro, WATANABE Minoru

    IEICE technical report   111 ( 399 )   153 - 156   2012.1

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    We have been developing a type of fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. Therefore, this device can virtually implement large gates onto a programmable gate array with a dynamic reconfiguration. This paper presents a new 0.18 μm process ORGA-VLSI and comparison results of the new 0.18 μm process ORGA-VLSI with a conventional 0.35 process ORGA-VLSI.

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  • Recovery experiment from a laser array failure in a Dynamic Optically Reconfigurable Gate Array

    YOZA Takashi, WATANABE Minoru

    IEICE technical report. Circuits and systems   111 ( 377 )   109 - 114   2012.1

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    Recently, demand of field programmable gate array (FPGA) uses for space applications is being increased since an FPGA can be reconfigured remotely. However, since under a space environment, high-energy charged particles break FPGA's configuration contexts, FPGA can not be used robustly. Therefore, we have been developing optically reconfigurable gate arrays (ORGAs) which consist of a laser array, a holographic memory, and a programmable gate array VLSI with a photodiode array. The ORGAs are reliable against space radiations since the ORGAs can use a damaged configuration context. Up to now, we have proposed a recovery method for a turn-on laser failure mode in an ORGA. However, the recovery method has never been applied for a dynamic ORGA that use photodiode memory architecture. Therefore, this paper presents that the recovery method is also useful on a dynamic ORGA.

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  • 0.18 μm process Optically Reconfigurable Gate Array VLSI

    2012 ( 30 )   1 - 4   2012.1

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  • A configuration speed adjustment method on ORGAs

    YOZA Takashi, WATANABE Minoru

    111 ( 323 )   13 - 17   2011.11

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  • Dynamically reconfigurable vision-chip architecture using a lens array

    KAMIKUBO Yuki, WATANABE Minoru, KAWAHITO Shoji

    Technical report of IEICE. ICD   111 ( 258 )   83 - 87   2011.10

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    In recent years, development of a high-speed image processing system is required for autonomous robots, cars, and so on. Since such embedded system must execute image processing operations at 1000 frames/s, there are issues in transferring image information between a processor chip and a memory chip and in processing it. Up to now, some vision chips including processing elements have been developed. However, such vision chip can execute only simple image operations and its performance is insufficient. Therefore, we have been developing a dynamically reconfigurable vision-chip architecture. This paper presents the experimental results of a dynamically reconfigurable vision-chip architecture using a lens array.

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  • Dynamically reconfigurable vision-chip architecture using a lens array

    2011 ( 15 )   1 - 5   2011.10

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  • Optically reconfigurable gate array using a phase hologram

    WATANABE Takahiro, WATANABE Minoru

    IEICE technical report   111 ( 37 )   1 - 5   2011.5

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    Demand for FPGAs that are usable under a space radiation environment is increasing daily. However, such high energy charged particles break a configuration context on FPGAs so that hardware itself is not robust in addition to software operations. On the other hand, Optically reconfigurable gate array (ORGA) architecture achieves not only high performance but also extreme robustness for such high-energy charged particles. This paper presents experimental results of optical reconfiguration using a phase modulation type holographic memory.

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  • A 256-context optically reconfiguration using a DigitalMirrorDevice

    YAMAJI Yuichiro, WATANABE Minoru

    IEICE technical report   111 ( 31 )   121 - 125   2011.5

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    We have been developing optically reconfigurable gate arrays that combines a holographic memory and a programmable gate array VLSI. The optically reconfigurable gate array enables nanosecond-order rapid dynamic reconfigurations. Up to now, a MEMS (Micro Electro Mechanical Systems) optically reconfigurable gate array using a MEMS device as a holographic memory has been proposed. This paper presents a demonstration result of a 256 configuration context MEMS optically reconfigurable gate array.

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  • MEMS allowable alignment errors of a MEMS dynamic optically reconfigurable gate array

    MORITA Hironobu, WATANABE Minoru

    IEICE technical report   110 ( 361 )   151 - 156   2011.1

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    In recent years, large processing power is required for various applications. On the other hand, miniaturization of transistors is close to physical limitation. Therefore, we have been developing Optically Reconfigurable Gate Array (ORGA) that consists of a holographic memory, a laser array, and a gate array VLSI. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. In addition to it, we have been developing a MEMS optically reconfigurable gate array. In this architecture, a MEMS holographic memory can be rewritten electrically and remotely. This paper clarifies the allowable alignment errors of the MEMS optically reconfigurable gate array.

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  • An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array

    GUNDJALAM Amarjargal, WATANABE Minoru

    IEICE technical report   110 ( 315 )   55 - 60   2010.11

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) to realize a high-speed dynamic reconfiguration capability. Among such researches, we have proposed a dynamic ORGA architecture that can achieve a high gate count VLSI by removing the static configuration memory and using the junction capacitance of photodiodes as dynamic random access memory. We have conducted dynamic partial reconfiguration experiments for the Dynamic Optically Reconfigurable Gate Array (DORGA) architecture. Since the dynamic architecture uses photodiodes as dynamic random access memory to store a configuration context, the retention time varies according to the repetition rate of partial dynamic reconfiguration procedures. Thus, we have analyzed the affection.

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  • Applications of optically reconfigurable gate arrays

    WATANABE Minoru

    IEICE technical report   110 ( 204 )   67 - 71   2010.9

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    Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed dynamic reconfiguration. The ORGA is an optoelectronic device that comprises laser sources, an optical holographic memory, and a programmable gate array VLSI. This paper presents applications of a SISC (MISC) processor concept and embedded systems used in space, which are based on the ORGA architecture.

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  • A MEMS addressing technique in optically reconfigurable gate arrays

    MORITA Hironobu, WATANABE Minoru

    IEICE technical report   110 ( 204 )   73 - 77   2010.9

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    In recent years, while large processing power for various applications is being required, miniaturization of transistors has been being progressed in order to increase the performance of integrated circuits. However, now such miniaturization is facing physical limitation. Therefore, we have been developing Optically Reconfigurable Gate Array (ORGA) that consists of a holographic memory, a laser array, and a gate array VLSI. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. On the other hand, conventional ORGAs require a lot of lasers depending on the number of configuration contexts. Therefore, this paper presents a MEMS addressing technique to reduce the number of addressing lasers.

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  • MEMS Optically Reconfigurable Gate Array with 64 configuration contexts

    YAMAJI Yuichiro, WATANABE Minoru

    IEICE technical report   110 ( 179 )   141 - 144   2010.8

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) that combine a holographic memory and a gate array VLSI. The ORGA enables nanosecond-order dynamic reconfigurations. Up to now, a holographic memory on an ORGA was programmed before the ORGA functions and the holographic memory worked as a read-only memory while ORGA functions. However, in order to increase the number of dynamic reconfiguration contexts, the holographic memory should be rewritten while ORGA functions. Therefore, we have introduced an electrically rewritable MEMS device onto an ORGA. This paper shows 64 configuration context MEMS ORGA architecture and its experimental results.

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  • Recovery method for a laser array failure on Optical Reconfigurable Gate Arrays

    WATANABE Takahiro, WATANABE Minoru

    IEICE technical report   110 ( 179 )   135 - 140   2010.8

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    Demand for FPGAs that are usable under a space radiation environment is increasing daily. However, such high energy charged particles break a configuration context on an FPGA so that hardware itself is not robust in addition to software operations. On the other hand, Optically reconfigurable gate array (ORGA) architecture achieves not only high performance but also extreme robustness for such high-energy charged particles. However, the ORGA has an unallowable failure mode, which is a turn-off failure mode of Lasers on a Laser array. Therefore, this paper presents a proposal of a recovery method for the turn-off failure mode in an ORGA and presents its demonstration results.

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  • Four-point template matching operations on a dynamically reconfigurable vision-chip architecture

    NAKADA Hironari, WATANABE Minoru

    IEICE technical report   110 ( 179 )   145 - 148   2010.8

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    In recent years, development of a high-speed image processing system is required for autonomous robots and cars, and so on. Since such embedded system must execute image processing operations at 1000 frames/s, there are issues in transferring image information and processing it. Up to now, some vision chips including processing elements have been developed. However, such vision chip can execute only simple operations and its performance is insufficient. Therefore, we have been developing a dynamically reconfigurable image processing device. This paper presents the experimental results of 4-point template matching operations on a dynamically reconfigurable image processor architecture.

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  • Image sensor using dynamic reconfiguration

    YASUDA Maki, WATANABE Minoru

    IEICE technical report   109 ( 469 )   83 - 86   2010.3

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    In recent years, development of a high-speed image processing system is required for autonomous robots and cars, and so on. Since such embedded system must execute image processing operations at 1000 frames/s, there are issues in transferring image information and processing it. Up to now, some vision chips including processing elements have been developed. However, such vision chip can execute only simple operations and its performance is insufficient. Therefore, we have been developing a dynamically reconfigurable image processor device. This paper presents a dynamically reconfigurable image processor architecture and some experimental results.

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  • Defect tolerance for a differential reconfiguration strategy

    MORITA Hironobu, WATANABE Minoru

    IEICE technical report   109 ( 469 )   77 - 81   2010.3

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    In recent years, large processing power for image processing and the other field processing is required. The improvement of the processing power is demanded. On the other hand, up to now, miniaturization of transistors has been being progressed in order to increase the performance of integrated circuits. However, now such miniaturization is facing physical limitation. Therefore, we have been developing Optically Reconfigurable Gate Array (ORGA) that consists of a holographic memory, a laser array, and a gate array VLSI. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. This paper presents a differential reconfiguration technique that allows fast reconfiguration with high defect tolerance.

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  • Block-by-block reconfiguration of a dynamic optically reconfigurable gate array

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   109 ( 405 )   19 - 23   2010.1

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    We have been developing a fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs). Also, we have proposed a dynamic ORGA architecture that can realize a large gate count gate array. This paper presents a demonstration result of block-by-block partial reconfiguration for the dynamic ORGA architecture.

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  • A remote dynamic optically reconfigurable gate array using a fiber array

    UENO Yumiko, WATANABE Minoru

    IEICE technical report   109 ( 395 )   167 - 170   2010.1

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    Up to now, Optically Reconfigurable Gate Arrays(ORGAs)have been developed to realize fast reconfiguration and numerous reconfiguration contexts. The ORGA consists of a hologram memory, a laser array, and a gate array VLSI. The ORGA is a new type programmable gate array that is dynamically reconfigured with a lot of configuration contexts stored on a holographic memory. However, conventional ORGA architectures have never realized a remote programming capability. So, a new remotely reconfigurable gate array architecture that enables remote reconfiguration using optical fiber networks has been developed with a standard ORGA-VLSI. Moreover, in this experiment, a dynamic ORGA has been adopted to the remote architecture. This paper presents the demonstration results of the architecture.

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  • A programmable optically reconfigurable gate array with a silver-halide holographic memory

    KUBOTA Shinya, WATANABE Minoru

    IEICE technical report   109 ( 395 )   175 - 179   2010.1

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    Recently, although demands of larger scale and large function for integrated circuits are increased, the progress of VLSI technologies is slowing down. Therefore, optically reconfigurable gate arrays(ORGAs)that can realize dynamic reconfiguration have been developed as an alternative technology of current integrated circuits. The ORGAs consists of a holographic memory, a laser array, and a gate array VLSI. The ORGAs can dynamically be reconfigured by using such optical components. Moreover, a programmable ORGA that can be reprogrammed by a writer has been developed. This paper presents the first experimental results of a programmable optically reconfigurable gate array using a silver-halide holographic memory as a reflective holographic memory.

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  • Compensation method for photodiode characteristics variation using an analog configuration context

    AOYAMA Yuji, WATANABE Minoru

    IEICE technical report   109 ( 395 )   171 - 174   2010.1

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    Recently, various fast reconfigurable devices have been developed. Among such researches, we have been developing optically reconfigurable gate arrays(ORGAs)that can be reconfigured with optical components in a perfectly parallel. Up to now, we have proposed a dynamic optically reconfigurable architecture that uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memory. However, a VLSI of the dynamic optically reconfigurable architecture has a lot of photodiodes and its outputs are directly connected to programming points of a programmable gate array. So, such photodiode characteristics variation and optical component variation cause collisions of circuit-outputs. Therefore, this paper proposes a compensation method for photodiode characteristics variation using an analog configuration context. Also, this paper presents experimental results to confirm its availability.

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  • A remote optically reconfigurable gate array with 4 configuration contexts

    UENO Yumiko, WATANABE Minoru

    IEICE technical report   109 ( 336 )   117 - 120   2009.12

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    Up to now, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize fast reconfiguration and numerous reconfiguration contexts. The ORGA consists of a hologram memory, a laser array, and a gate array VLSI. The ORGA is a new type VLSI that a programmable gate array is dynamically reconfigured with a lot of configuration contexts on a holographic memory. However, conventional ORGA architectures have never realized a remote programming capability. Therefore, we have developed a new remotely reconfigurable gate array architecture that enables remote reconfiguration using optical fiber networks. This paper demonstrates a more advanced system, a for-context remote optically reconfigurable gate array architecture.

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  • Optical buffering technique under space radiation environment

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   109 ( 320 )   13 - 18   2009.11

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    Embedded devices used for spacecraft, satellites, and space stations are vulnerable to effects of high-energy charged particles. For such embedded devices, reconfigurable devices are expected. When a part of a reconfigurable device is damaged, the configuration context can be changed remotely by using wireless communication. However, configuration contexts also suffer from space radiation while configuration data are transferred with wireless communication and are retained on an EEPROM or a SRAM(EEPROM/SRAM). So, this paper presents an optical buffering technique for a programmable gate array under a space radiation environment. The technique enables rapid recovery of a programmable device that has been damaged by high-energy charged particles. It uses incorrect configuration data including some error bits that have already been damaged by particles while the configuration data are transferred with wireless communication and are retained on an EEPROM/SRAM.

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  • An inversion/non-inversion dynamic optical reconfiguration architecture using a MEMS

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   109 ( 320 )   7 - 12   2009.11

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    We have been developing fast reconfigurable devices, an Optically Reconfigurable Gate Arrays(ORGAs). Among such researches, we have proposed an inversion/non-inversion dynamic architecture that allows fast reconfiguration and large gate count realization. This paper presents effectiveness of the inversion/non-inversion dynamic architecture using a MEMS holographic memory.

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  • Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array

    KUBOTA Shinya, WATANABE Minoru

    IEICE technical report   109 ( 316 )   101 - 105   2009.11

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    Recently, although demands of larger scale and large function for integrated circuits are increased, the progress of VLSI technologies is slowing down. Therefore, optically reconfigurable gate arrays(ORGAs)that can realize dynamic reconfiguration have been developed as an alternative technology of current integrated circuits. The ORGAs consists of a holographic memory, a laser array, and a gate array VLSI. The ORGAs can be dynamically reconfigured by using such optical components. Among such researches, a programmable ORGA that can be reprogrammed by a writer has been developed. This paper presents influence analysis results of a holographic memory window of a programmable ORGA.

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  • An optimization method of optical reconfigurations using analog contexts

    AOYAMA Yuji, WATANABE Minoru

    IEICE technical report   109 ( 226 )   7 - 10   2009.10

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    Recently, various fast reconfigurable devices have been developed. Among such researches, we have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. Up to now, we have proposed a dynamic optically reconfigurable architecture that uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memory. In this architecture, reconfiguration speed for a circuit implemented on a gate array is different from each other depending on its reconfiguration context pattern. Therefore, this paper proposes an optimization method of optical reconfigurations using analog contexts and presents experimental results.

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  • An optically differential reconfigurable gate array using a Digital Mirror Device

    MORITA Hironobu, WATANABE Minoru

    IEICE technical report   109 ( 226 )   1 - 5   2009.10

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    In recent years, miniaturization of transistors has been being progressed in order to increase the performance of integrated circuits. However, now such miniaturization is facing physical limitation. Therefore, we have been developing Optically Reconfigurable Gate Array (ORGAs) that consist of a holographic memory, a laser array and a gate array VLSI. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. This paper presents experimental results of optical differential reconfigurations using a digital micromirror device (DMD).

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  • A remote optically reconfigurable gate array using fibers

    UENO Yumiko, WATANABE Minoru

    IEICE technical report   109 ( 201 )   63 - 66   2009.9

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    Up to now, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize fast reconfiguration and numerous reconfiguration contexts. The ORGA consists of a hologram memory, a laser array, and a gate array VLSI. The ORGA is a new type VLSI that a programmable gate array is dynamically reconfigured with a lot of configuration contexts stored on a holographic memory. However, conventional ORGA architectures have never realized a remote programming capability. So, this paper proposes a new remotely reconfigurable gate array architecture that enables remote reconfiguration using optical fiber networks and presents the demonstration results of the architecture.

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  • Defect tolerance of a MEMS dynamic optically reconfigurable gate array

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   109 ( 201 )   71 - 76   2009.9

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    Recently, dynamic reconfigurable device has been developed to improve the performance of current VLSIs. Also, we have been developing a fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that consist of a holographic memory, a laser diode array, and a gate array VLSI. Because of a large storage capability of a holographic memory and an optically parallel connection, ORGAs can realize fast dynamic reconfiguration. In addition, we have proposed an ORGA using a digital mirror device (DMD) as holographic memory. A DMD has advantages of fast response ability and high diffraction efficiency. Therefore, a DMD holographic memory is expected to realize dynamic operations of an ORGA's holographic memory. This paper presents experimental results of a defective tolerance of an ORGA with a DMD holographic memory.

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  • A configuration speed acceleration method using negative logic implementation

    MORIWAKI Retsu, WATANABE Minoru

    IEICE technical report   109 ( 201 )   67 - 70   2009.9

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    Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve a high-speed reconfiguration. This paper proposes a negative logic implementation method that optical configurations can be accelerated without any ORGA architecture modification and any increase of laser power.

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  • A writer system not using an imaging lens for 4-contexts programmable optically reconfigurable gate arrays

    KUBOTA Shinya, WATANABE Minoru

    IEICE technical report   109 ( 198 )   109 - 112   2009.9

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    Recently, although demands of larger scale and large function for integrated circuits are increased, the progress of VLSI technologies is slowing down. Therefore, optically reconfigurable gate arrays (ORGAs) that can realize dynamic reconfiguration have been developed as an alternative technology of current integrated circuits. The ORGAs consists of a holographic memory, a laser array, and a gate array VLSI. The ORGAs can be dynamically reconfigured by using such optical components. Among such researches, programmable ORGAs that can be reprogrammed by a writer have been developed. This paper presents the architecture of a 4-context programmable ORGAs and its writer without an imaging lens.

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  • Four-context optical reconfiguration using a Digital Mirror Device

    MORITA Hironobu, WATANABE Minoru

    IEICE technical report   109 ( 174 )   37 - 40   2009.8

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    In recent years, miniaturization of transistors has been being progressed in order to increase the performance of integrated circuits. However, now such miniaturization is facing physical limitation. Therefore, we have been developing Optically Reconfigurable Gate Array (ORGAs) that consist of a holographic memory, a laser array and a gate array VLSI. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. However, to realize higher reconfiguration frequency, higher efficiency holographic memory is required for ORGAs. So, this paper presents the experimental results of four context optical reconfigurations using a digital micromirror device (DMD).

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  • A 36-context dynamic optically reconfigurable gate array

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   109 ( 174 )   41 - 46   2009.8

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    We have been developing optically reconfigurable gate arrays (ORGAs) which have possibilities to realize large virtual gate count and high performance by combining a holographic memory which has a large storage capacity with a programmable gate array. In addition, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high density VLSI by using a photodiode memory architecture. Up to now, we have already developed a 16-context ORGA with a nanosecond-order reconfiguration capability. This paper presents a more advanced 36-context dynamic ORGA.

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  • Fault tolerance of a dynamic optically reconfigurable gate array using a non-volatile volume holographic memory

    MABUCHI Takayuki, MIYAGI Kenji, WATANABE Minoru, OGIWARA Akihumi

    IEICE technical report   109 ( 110 )   109 - 112   2009.6

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    Optically Reconfigurable Gate Arrays (ORGAs) consist of a gate array VLSI, a holographic memory, and a laser array. ORGA can achieve rapid reconfiguration by exploiting optical parallel connections. Moreover, such parallel connections, allow to realize high defect tolerance. This paper presents fault tolerance of a dynamic optically reconfigurable gate array using a non-volatile volume holographic memory.

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  • Optical Reconfiguration using a Digital Micromirror Device

    MORITA Hironobu, WATANABE Minoru

    IEICE technical report   109 ( 110 )   113 - 116   2009.6

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    In recent years, miniaturization of transistors has been being progressed in order to increase the performance of integrated circuits. However, now such miniaturization faces physical limitation. Therefore, we have been developing Optically Reconfigurable Gate Arrays (ORGAs) that consist of a holographic memory, a laser array and a gate array VLSI. The ORGA can be optically reconfigured in a very short time along with a lot of reconfiguration contexts. However, to realize higher reconfiguration frequency, higher efficiency holographic memory is required for ORGAs. So, this paper presents the demonstration of a digital micromirror device (DMD) holographic configuration technique.

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  • A sixteen-context optically reconfigurable gate array

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 455 )   61 - 65   2009.2

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    Optically reconfigurable gate arrays (ORGAs) are being developed to overcome current VLSI technologies in the future. The ORGAs have a possibility to realize a large virtual gate count over current VLSIs and fast dynamic reconfigurations by combining a holographic memory to a programmable gate array VLSI. In addition, we are developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high density VLSI by using a photodiode memory architecture. This paper demonstrates a sixteen-context DORGA architecture.

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  • An optically reconfigurable gate array with a non-volatile holographic memory

    MABUCHI Takayuk, MIYASHIRO Kenji, WATANABE Minoru, OGIWARA Akifumi

    IEICE technical report   108 ( 455 )   67 - 70   2009.2

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    Optically Reconfigurable Gate Arrays (ORGAs) consist of a gate array VLSI, a holographic memory and a laser array that can achieve rapid reconfiguration by using optical parallel connections This paper shows an optically reconfigurable gate array with a non-volatile holographic memory which can be written optically.

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  • A programmable 9-contexts optically reconfigurable gate arrays and its writer

    KUBOTA Shinya, WATANABE Minoru

    2009 ( 7 )   37 - 40   2009.1

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    Recently, optically reconfigurable gate arrays (ORGAs) that can realize dynamic reconfiguration have been developed. The ORGAs consists of a holographic memory, a laser array, and a gate array VLSI. ORGAs are new type VLSIs, the gate arrays of which are optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. However, conventional ORGAs have one important shortcoming. They cannot be reprogrammed after fabrication. Therefore, to improve that shortcoming, we have been developing a programmable optically reconfigurable gate array architecture. So, this paper presents the demonstration of a programmable 9-contexts optically reconfigurable gate arrays and its writer.

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    Other Link: http://id.nii.ac.jp/1001/00061224/

  • Perfect demonstration of a four-context Optically Reconfigurable Gate Array

    MABUCHI Takayuk, WATANABE Minoru

    2009 ( 7 )   41 - 44   2009.1

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    Optically reconfigurable gate arrays (ORGAs) consist of a gate array VLSI, a holographic memory and a laser diode array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. This paper shows the perfect demonstration of a four-context Optically Reconfigurable Gate Array. Also, the experimental results of a superimposing technique are presented.

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    Other Link: http://id.nii.ac.jp/1001/00061225/

  • Comparison evaluation of an inversion / non-inversion dynamic optically reconfiguration architecture

    KATO Shinichi, WATANABE Minoru

    IEICE technical report   108 ( 412 )   45 - 50   2009.1

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) which can be reconfigured optically. The ORGAs consist of a laser array, a hologram memory, a programmable gate array VLSI. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have proposed a dynamic optically reconfigurable gate array using a photodiode memory architecture to realize huge gate count VLSI, an optically differential reconfigurable gate array using a differential reconfiguration strategy to achieve a fast reconfiguration capability, and an inversion/noninversion optically reconfigurable architecture that combines both architectures to realize both advantages of rapid configuration and high gate count. This paper shows the estimation results of the three architectures under a same condition and fast configuration experimental results of the inversion/noninversion optically reconfigurable architecture.

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  • Perfect demonstration of a four-context Optically Reconfigurable Gate Array

    MABUCHI Takayuk, WATANABE Minoru

    IEICE technical report   108 ( 412 )   41 - 44   2009.1

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    Optically reconfigurable gate arrays (ORGAs) consist of a gate array VLSI, a holographic memory and a laser diode array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. This paper shows the perfect demonstration of a four-context Optically Reconfigurable Gate Array. Also, the experimental results of a superimposing technique are presented.

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  • A programmable 9-contexts optically reconfigurable gate arrays and its writer

    KUBOTA Shinya, WATANABE Minoru

    IEICE technical report   108 ( 412 )   37 - 40   2009.1

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    Recently, optically reconfigurable gate arrays (ORGAs) that can realize dynamic reconfiguration have been developed. The ORGAs consists of a holographic memory, a laser array, and a gate array VLSI. ORGAs are new type VLSIs, the gate arrays of which are optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. However, conventional ORGAs have one important shortcoming. They cannot be reprogrammed after fabrication. Therefore, to improve that shortcoming, we have been developing a programmable optically reconfigurable gate array architecture. So, this paper presents the demonstration of a programmable 9-contexts optically reconfigurable gate arrays and its writer.

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  • Comparison evaluation of an inversion / non-inversion dynamic optically reconfiguration architecture

    KATO Shinichi, WATANABE Minoru

    2009 ( 7 )   45 - 50   2009.1

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) which can be reconfigured optically. The ORGAs consist of a laser array, a hologram memory, a programmable gate array VLSI. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have proposed a dynamic optically reconfigurable gate array using a photodiode memory architecture to realize huge gate count VLSI, an optically differential reconfigurable gate array using a differential reconfiguration strategy to achieve a fast reconfiguration capability, and an inversion/noninversion optically reconfigurable architecture that combines both architectures to realize both advantages of rapid configuration and high gate count. This paper shows the estimation results of the three architectures under a same condition and fast configuration experimental results of the inversion/noninversion optically reconfigurable architecture.

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    Other Link: http://id.nii.ac.jp/1001/00061226/

  • Fast optical reconfigurations of a nine-context of ORGA

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 388 )   63 - 67   2009.1

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    Optically reconfigurable gate arrays (ORGAs) have been developed to realize fast reconfigurations and numerous reconfiguration contexts by combining a holographic memory to a programmable gate array. ORGAs have a possibility to realize large virtual gate counts over current VLSIs. In addition to it, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that can realize a high density VLSI by using a photodiode memory architecture. This paper presents a fast reconfiguration capability of a nine-context DORGA architecture.

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  • An improvement method for assembly errors of optical components in optically reconfigurable gate arrays

    MORITA HIRONOBU, WATANABE Minoru

    IEICE technical report   108 ( 388 )   59 - 62   2009.1

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) that consists of a holographic memory, a laser array, and a gate array VLSI. The gate array of the ORGA can be reconfigured optically by using a laser array. However, in these devices, positioning accuracies between a holographic memory and an ORGA-VLSI and between a laser array and the holographic memory were main concerns to manufacture them. Therefore, we have been studying correction techniques using holographic memories with compensation data for each error. This paper presents experimental results of correction techniques of a gate array part, a holographic memory part, and a laser array part.

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  • Performance estimation for a gate array part of a dynamic optically reconfigurable gate array

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   108 ( 347 )   73 - 78   2008.12

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  • Fast optical reconfigurations of a nine-context ODRGA

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 347 )   67 - 72   2008.12

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    Fast reconfigurations and numerous reconfiguration contexts are two important factors of dynamic reconfiguration devices. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize them by combining a holographic memory to a programmable gate array. In addition, we have been developing optically differential reconfigurable gate arrays (ODRGAs) to realize faster reconfigurations. This paper presents reconfiguration capabilities of a nine-context ODRGA architecture.

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  • An emulation experiment of an inversion/non-inversion dynamic optical reconfiguration architecture

    KATO Shinichi, WATANABE Minoru

    IEICE technical report   108 ( 300 )   1 - 4   2008.11

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) consisting of a laser array, a hologram memory, and a gate array VLSI. The ORGA allows fast configuration by exploiting two dimensional optical bus. Furthermore, in order to achieve a larger-scale gate array and faster configuration per laser power, an inversion/non-inversion dynamic optically reconfiguration architecture has been proposed. This paper presents an emulation result of the inversion/non-inversion dynamic optically reconfiguration architecture by using conventional ORGAs.

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  • Assembly accuracy of a holographic memory in an optically reconfigurable gate array

    MORITA HIRONOBU, WATANABE Minoru

    IEICE technical report   108 ( 300 )   5 - 8   2008.11

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) that consists of a holographic memory, a laser array, and a gate array VLSI. The gate array of the ORGA can be reconfigured optically by using a laser array. However, positioning accuracies between a holographic memory and an ORGA-VLSI and between a laser array and the holographic memory were concerns in terms of manufacture of ORGAs. Therefore, this paper presents allowable alignment errors of holographic memory part and a new technique to compensate the error by adjusting holographic memory patterns.

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  • Fault tolerance of the holographic memory in the large scale opptically reconfigurable gate array

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   108 ( 292 )   21 - 25   2008.11

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    Since embedded devices for spacecraft, satellites, and space stations are vulnerable to effects of high-energy charged particles, we have been developing Optically Reconfigurable Gate Arrays (ORGAs) as one of high reliable devices that consist of a holographic memory, a laser diode arrays and a gate array VLSI. Since an ORGAs can be programmed optically and in perfectly parallel, even if its gate array includes defect portions, the gate array can be used by avoiding such defect portions and by programming the same circuit to the other area. This high defective tolerance is based on the holographic memory with a high defective tolerance. This paper presents that a dynamic ORGA can have such high defect tolerance through some experimental results.

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  • A 13.75ns fast holographic reconfiguration

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 292 )   15 - 19   2008.11

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs) to realize a virtual large gate count by exploiting the large strage capacity of a holographic memory. Among of them, we have been developing Optically Differential Reconfigurable Gate Arrays (ODRGAs) to achieve faster reconfiguration per unit laser power. This paper shows a 13.75ns dynamic reconfigurations of an ODRGA.

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  • Fast dynamic optically reconfigurable gate array VLSI

    KATO Shinichi, WATANABE Minoru

    IEICE technical report   108 ( 224 )   61 - 65   2008.9

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    We have been developing Optically Reconfigurable Gate Arrays (ORGAs). An ORGA consists of a laser array, a hologram memory, a gate array VLSI. Such ORGA can optically be reconfigured by using two dimensional optical bus in a very short time. Also, since a holographic memory has a large storage capability, an ORGA can achieve large virtual gates. Up to now, an optically differential reconfigurable gate array to increase reconfiguration frequency with no increase of laser power and a dynamic optically reconfigurable gate array to achieve a high gate count VLSI have been proposed. However, architectures with both advantages have never been developed. Therefore, to realize both advantages of rapid configuration and a high gate count, this paper presents a novel fast dynamic optically reconfigurable gate array VLSI that combines both architectures. In this study, a design of the fast dynamic optically reconfigurable gate array VLSI is presented.

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  • A programmable multi-context optical reconfigurable gate array using a PAL-SLM

    KUBOTA Shinya, WATANABE Minoru

    IEICE technical report   108 ( 224 )   67 - 70   2008.9

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    Recently, fast reconfigurable devices, optically reconfigurable gate arrays (ORGAs) have been develped. The ORGA consits of a holographic memory, a laser array, and a gate array VLSI. However, conventional ORGAs have a demerit that they can not be reprogrammed after its fabrication. Therefore, in order to improve the demerit, this paper presents the architecture of a programmable ORGA with four configuration contexts.

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  • Fast configuration experiments of a large-gate optically reconfigurable gate array

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 224 )   55 - 59   2008.9

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    Optical reconfigurable gate arrays (ORGAs) with a holographic memory have been developed to realize a large virtual gate count VLSI, that is much larger than those of current available VLSIs, by exploiting the large storage capacity of the holographic memory. However, the instantaneous performance of ORGAs depends on the actual gate count of its VLSI part. So, we are developing dynamic optically reconfigurable gate arrays (DORGAs) with a photodiode memory architecture. This paper shows the experimental results of fast reconfigurations using the largest gate count DORGA-VLSI.

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  • A measurement of retention time of a dynamic optically reconfigurable gate array with large gates

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   108 ( 220 )   51 - 55   2008.9

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can optically be reconfigured in a perfectly parallel. In this device, large gates can be achieved by exploiting the large storage capacity of a holographic memory. However, the instantaneous performance of ORGAs depends on the actual gate count of its VLSI part. So, we have fabricated the world's largest gate count dynamic optically reconfigurable gate array VLSI (DORGA-VLSI) using dynamic architecture that uses photodiode as memory. This paper presents an estimation result of retention time of the DORGA-VLSI chip.

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  • An estimation of a large-scale Dynamic Optically Reconfigurable Gate Array VLSI

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   108 ( 192 )   27 - 31   2008.8

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. In this device, gate array's activity can be increased by exploiting such fast dynamic reconfiguration capabilities. This paper presents the world's largest gate count dynamic optically reconfigurable gate array VLSI and its estimation results.

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  • Fast optical reconfigurations of four-context DORGAs

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 192 )   21 - 26   2008.8

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    Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory have been developed to realize large scale circuits as virtual circuits. Also, we have proposed dynamic optically reconfigurable gate arrays (DORGAs) with photodiode memory architecture to realize a high gate density VLSIs. This paper presents the experimental results of a four-context DORGA with a liquid crystal holographic memory.

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  • A multi-context dynamic optically reconfigurable gate array using a silver-halide holographic memory

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   108 ( 48 )   61 - 64   2008.5

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. This device uses a hologram memory for storing many reconfiguration contexts. Up to now, we have already presented experimental results of multi-context implementation on liquid crystal holographic memory. However, in this experiment, in order to realize higher recording density, we introduce a silver-halide holographic memory. This paper presents the experimental results of a multi-context configuration using the silver-halide holographic memory.

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  • Fast optical reconfigurations of four-contexts ORGAs

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   108 ( 48 )   65 - 69   2008.5

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    Recently, Optically Reconfigurable Gate Arrays (ORGAs) with a holographic memory recording a lot of configuration contexts have been developed to enable a rapid reconfiguration. However, the reconfiguration frequency of the first prototype ORGA was insufficient and its gate array can not be executed while being reconfigured. Therefore, we have been developing Optically Differential Reconfigurable Gate Arrays (ODRGAs), a gate array of which can be reconfigured in nanoseconds and can be executed while being reconfigured. So, this paper presents the experimental results of a four-contexts ODRGA system with a liquid crystal hologram.

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  • Fault tolerance analysis for holographic memories in optically reconfigurable gate arrays.

    SHINOHARA Koji, WATANABE Minoru

    2008 ( 2 )   131 - 135   2008.1

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    Recently, optically reconfigurable gate arrays (ORGAs) that enable high information processing speed are being developed. Such optically reconfigurable gate arrays consist of a laser diode array, a holographic memory, and a gate array VLSI, allowing fast reconfigurations and numerous reconfiguration contexts. Since an ORGA-VLSI can be programmed optically and in perfectly parallel, even if its gate array includes defect portions, the gate array can be used by avoiding such defect portions and by programming the same circuit to the other area. However, it is required that a holographic memory to support such programming must be dependable. So, this paper clarifies noise tolerance properties of holographic configurations.

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    Other Link: http://id.nii.ac.jp/1001/00026858/

  • A fast optical reconfiguration experiment of a dynamic optically reconfigurable gate array

    NAKAJIMA Mao, WATANABE Minoru

    2008 ( 2 )   127 - 130   2008.1

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    Recently, in order to realize fast reconfigurations and numerous reconfiguration contexts, Optically Reconfigurable Gate Array (ORGAs) has been developed. Also, we have proposed a dynamic optically reconfigurable gate array (DORGA) architecture that perfectly removes a static configuration memory to store a single configuration context and uses photodiodes as a configuration memory. So, this paper presents experimental results estimating a fast reconfiguration capability of the DORGA architecture.

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  • Analysis of retention time under continuous reconfiguration of a DORGA.

    SETO Daisaku, WATANABE Minoru

    2008 ( 2 )   121 - 125   2008.1

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. In such ORGAs, we have proposed a dynamic optically reconfigurable gate array (DORGA) architecture that uses photodiode as dynamic memory to store a configuration context, achieving large gates. However, it was concerned that when a certain circuit is programmed to a gate array and works on it, and the other configuration is applied into the different gate array area, the configuration of the other area may affect the working circuit and may reduce the retention time of the working circuit. So, the influence was investigated. This paper shows experimental results demonstrating that the DORGA architecture is effective under dynamic reconfigurations.

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  • Fault tolerance analysis for holographic memories in optically reconfigurable gate arrays

    SHINOHARA Koji, WATANABE Minoru

    IEICE technical report   107 ( 415 )   53 - 57   2008.1

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    Recently, optically reconfigurable gate arrays (ORGAs) that enable high information processing speed are being developed. Such optically reconfigurable gate arrays consist of a laser diode array, a holographic memory, and a gate array VLSI, allowing fast reconfigurations and numerous reconfiguration contexts. Since an ORGA-VLSI can be programmed optically and in perfectly parallel, even if its gate array includes defect portions, the gate array can be used by avoiding such defect portions and by programming the same circuit to the other area. However, it is required that a holographic memory to support such programming must be dependable. So, this paper clarifies noise tolerance properties of holographic configurations.

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  • A fast optical reconfiguration experiment of a dynamic optically reconfigurable gate array

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   107 ( 415 )   49 - 52   2008.1

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    Recently, in order to realize fast reconfigurations and numerous reconfiguration contexts, Optically Reconfigurable Gate Array (ORGAs) has been developed. Also, we have proposed a dynamic optically reconfigurable gate array (DORGA) architecture that perfectly removes a static configuration memory to store a single configuration context and uses photodiodes as a configuration memory. So, this paper presents experimental results estimating a fast reconfiguration capability of the DORGA architecture.

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  • Analysis of retention time under continuous reconfiguration of a DORGA

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   107 ( 415 )   43 - 47   2008.1

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. In such ORGAs, we have proposed a dynamic optically reconfigurable gate array (DORGA) architecture that uses photodiode as dynamic memory to store a configuration context, achieving large gates. However, it was concerned that when a certain circuit is programmed to a gate array and works on it, and the other configuration is applied into the different gate array area, the configuration of the other area may affect the working circuit and may reduce the retention time of the working circuit. So, the influence was investigated. This paper shows experimental results demonstrating that the DORGA architecture is effective under dynamic reconfigurations.

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  • 動的再構成のための配置配線の一手法

    日高 亮, 小林 史典, 渡邊 実

    電子情報通信学会技術研究報告. RECONF, リコンフィギャラブルシステム : IEICE technical report   107 ( 341 )   13 - 17   2007.11

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    近年,動的再構成デバイスが実用的に使われ始めているが,時間とともに回路が変化するので,その上に構成する回路の配置配線に,従来の手法は使えない.そこで1つの試みとして,プロセスの微細化に伴う配線遅延の問題を重視してToronto大学のV.Betzらが開発したFPGA用配置配線ツールを,動的再構成向けにカスタマイズすることを行った.

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  • Fast dynamic optical reconfigurations of multi-context ORGAs

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   107 ( 296 )   7 - 12   2007.10

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    Recently, Optically Reconfigurable Gate Arrays (ORGAs) with a holographic memory recording a lot of configuration contexts have been developed to enable a rapid reconfiguration. However, the reconfiguration frequency of the first prototype ORGA was insufficient and its gate array can not be executed while being reconfigured. Therefore, we have been developing Optically Differential Reconfigurable Gate Arrays (ODRGAs), a gate array of which can be reconfigured in nanoseconds and can be executed while being reconfigured. So, this paper presents the experimental results of a multi-context ODRGA architecture with a liquid crystal hologram.

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  • Fast optical configurations using context superimposition

    YAMAGUCHI Naoki, WATANABE Minoru

    IEICE technical report   107 ( 296 )   13 - 16   2007.10

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    Recently, Optically Reconfigurable Gate Arrays (ORGAs) have been developed in order to realize a fast reconfiguration capability. We have been developing an ORGA with a liquid crystal holographic memory including 4 configuration contexts. Among such researches, we have proposed an acceleration method of configuration frequency by superimpositions of the same contexts without any increases of laser power. In this paper, the experimental results of this superimposition method are presented.

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  • An analysis of retention time of a DORGA with a constant irradiation period

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   107 ( 296 )   1 - 6   2007.10

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. Up to now, we have proposed a dynamic optically reconfigurable architecture that uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memory. In this architecture, suitable laser exposure time for each implementation circuit is different from each other. However, the laser exposure time is always designed as a constant. So, the affect for retention time of implementation circuits was concerned. Therefore, this paper presents experimental results of two sample implementation circuits to demonstrate that the architecture is available under such the condition.

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  • Measuremnt for reconfiguration and retention time of a dynamic optically reconfigurable architecture

    SETO Daisaku, WATANABE Minoru

    IEICE technical report   107 ( 225 )   29 - 33   2007.9

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    Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. Previously proposed ORGAs had a static memory function to store a single configuration context. However, the implementation of the static memory function prevented to realize high integration of ORGA-VLSIs. So, we have proposed a dynamic optically reconfigurable architecture that uses photodiodes as dynamic memory to store a configuration context. This paper presents the measurement results of reconfiguration and retention time in the case of combining the dynamic optically reconfigurable architecture with a holographic memory.

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  • A fast optical reconfiguration under an operation of a gate array in an ODRGA-VLSI

    NAKAJIMA Mao, WATANABE Minoru

    IEICE technical report   107 ( 225 )   23 - 27   2007.9

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    Recently, Optically Reconfigurable Gate Arrays (ORGAs) with a holographic memory have been developed to enable rapid reconfiguration. However, since conventional ORGAs used serial transfers between gate arrays and optical receiver arrays, the reconfiguration period was limited to 16μs and operations on a gate array could not be executed while being reconfigured. Therefore, we have been developing Optically Differential Reconfigurable Gate Arrays (ODRGAs) without serial transfers, a gate array of which can be reconfigured in nanoseconds and can be executed while being reconfigured. This paper presents the experimental results of 62.5ns reconfiguration of an ODRGA architecture with a liquid crystal hologram.

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  • Multi-context optically reconfigrable gate array

    YAMAGUCHI Naoki, WATANABE Minoru

    IEICE technical report   107 ( 225 )   19 - 22   2007.9

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    Recently, Optically Reconfigurable Gate Arrays (ORGAs) have been developed in order to realize a fast reconfiguration capability. We have been developing an ORGA with a liquid crystal holographic memory. However, the number of contexts was limited to one. This paper presents experimental results of a multi-context ORGA architecture using a liquid crystal holographic memory.

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  • Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays

    HIDAKA Ryo, WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report   106 ( 246 )   7 - 11   2006.9

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    Optically Differential Reconfigurable Gate Arrays (ODRGAs) have been developed to realize a bit-by-bit reconfiguration capability. The ODRGA architecture allows to decrease the number of irradiations bits included in a context. On the other hand, the intensity of each bit of diffraction light from a holographic memory increases as decreasing the number of irradiation bits included in a context. This paper experimentally presents the advantage of the acceleration of reconfiguration speed and the reduction of power consumption in ODRGA architecture.

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  • An Optically Reconfigurable Gate Array with manufacturing defect tolerance

    HIDAKA Ryo, WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report   106 ( 246 )   1 - 5   2006.9

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    Recently, as VLSI process technologies are progressed, the defective fractions of VLSIs are more increased and the die sizes have to be smaller to decrease the number of defective chips. However, since the need for non-defective large die chips is increased day-by-day, we have developed optically reconfigurable gate arrays (ORGAs) with a parallel programming capablity. This paper presents a high manufacturing defect tolerance of the optically programmable architecture that combines high manufacturing defect tolerance-holographic memory onto an ORGA-VLSI with a parallel programming capablity.

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  • An Optically Reconfigurable Gate Array with a liquid crystal hologram

    NAKADA Yoshiyuki, WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report   106 ( 246 )   13 - 16   2006.9

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    Recently, Optically Reconfigurable Gate Arrays (ORGAs) have been developed in order to realize a fast reconfiguration capability. The ORGA consists of laser sources, an optical memory, and a gate array VLSI. Also, we have been developing a new ORGA that uses a liquid crystal holographic memory as an optical memory. This paper presents the new ORGA architecture with a liquid crystal holographic memory. The performance is clarified experimentally.

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  • Optically Differential Reconfigurable Gate Array

    MIYANO Mototsugu, WATANABE Minoru, KOBAYASHI Fuminori

    The IEICE transactions on information and systems   89 ( 9 )   1935 - 1942   2006.9

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    Other Link: http://hdl.handle.net/10228/4569

  • Characteristics improvement of PLLs using phase interpolation : Circuit optimization of phase interpolation

    INOUE Manabu, KOBAYASHI Fuminori, WATANABE Minoru

    IEICE technical report   105 ( 504 )   13 - 17   2006.1

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    Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propose a new PLL using phase interpolation based on a counter with a high-frequency internal clock. The PLL can compare phases more than once a cycle of reference and input, thus reducing jitter and improving resonsiveness. Also we optimize implementation of phase interpolation, to improve circuit size and maximum operating frequency, even if the circuit compares phases many time a cycle.

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  • Improvement reconfiguration time of an Optically Differential Reconfigurable Gate Array using several VCSELs

    MIYANO Mototsugu, WATANABE Minoru, KOBAYASHI Fuminori

    Technical report of IEICE. ICD   105 ( 184 )   67 - 70   2005.7

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    Optically Reconfigurable Gate Arrays have been developed to enable rapid reconfiguration. We have developed an Optically Differential Reconfigurable Gate Array (ODRGA) to realize the reconfiguration of an arbitrary portion in addition to the optically reconfigurable capability. This paper presents a differential reconfiguration architecture to enable arbitrary partial reconfiguration and the structure and specification of an ODRGA-VLSI. Also the improvemnet results of reconfiguration time by using several Vertical Cavity Surface Emitting Lasers for a reconfiguration irradiation are shown.

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  • 272ゲート規模ODRGA-VLSIの実装評価

    志岐 武宣, 渡邊 実, 小林 史典

    映像情報メディア学会技術報告   29 ( 40 )   61 - 65   2005.7

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  • A-1-19 An Over-Sampling Phase Detector (OSPD) for Reducing PLL Jitters

    Inoue Manabu, Kobayashi Fuminori, Watanabe Minoru

    Proceedings of the Society Conference of IEICE   19 - 19   2005

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  • Evaluation of reconfiguration circuits for Optically Reconfigurable Gate Arrays

    FUJIME Ryuji, WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report. Computer systems   104 ( 476 )   11 - 15   2004.12

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    Recently, dynamically reconfigurable gate arrays have been focused to realize high performance VLSIs like application specific integrated circuits.We have been developing optically reconfigurable gate arrays, combining an optical memory, a gate array VLSI with photodiodes, optical connections between the optical memory and gate array VLSI.Since the gate array VLSI includes extremely large sets of a photodiode and an optical reconfiguration circuit, the performance of optical reconfiguration circuit affects overall VLSI system. This paper shows some types of optical reconfiguration circuits using 0.35μm CMOS process technology. Also, the evaluation results of operation frequency, implementation area, and power consumption are presented.

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  • An Optically Differential Reconfigurable Gate Array VLSI

    SHIKI Takenori, WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report. Computer systems   104 ( 476 )   5 - 9   2004.12

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    Reconfigurable processors based on Field Programmable Gate Arrays (FPGAs) open new computational paradigms since its internal structure can easily be modified according to a given application. However, the reconfiguration time of FPGAs can be significant overhead for reconfigurable applications. An Optically Differential Reconfigurable Gate Array(ODRGA) has large bandwidth optical interconnection and offers high-speed reconfiguration that can not be realized by electrical interconnection. This paper shows a layout of a 153 gate count ODRGA-VLSI chip.

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  • Optically Differential Reconfigurable Gate Array with a Pulse Laser

    MIYANO Mototsugu, WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report. Computer systems   104 ( 476 )   1 - 4   2004.12

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    Optically Reconfigurable Gate Arrays which is one of reconfigurable devices have been developed to enable rapid reconfiguration. We have developed an Optically Differential Reconfigurable Gate Array(ODRGA) to realize the reconfiguration of an arbitrary portion in addition to the optically reconfigurable capability. This paper presents the structure of a fabricated ODRGA-VLSI chip and a differential reconfiguration architecture to enable arbitrary partial reconfiguration. Also shown are the experimental results of reconfiguration onto ODRGA-VLSI chip using a pulse laser and a potential to be reconfigured rapidly.

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  • An Optically Differential Reconfigurable Gate Array

    WATANABE Minoru, KOBAYASHI Fuminori

    2004 ( 102 )   61 - 66   2004.10

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    This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA) using a 0.18μm - 5 Metal CMOS process technology. ODRGA is a type of Field Programmable Gate Arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35μm - 3 Metal CMOS process technology, their gate-density remains unsatisfactory. For that reason, a new ODRGA-VLSI chip with four logic blocks, five switching matrices, and 16 I/O bits was fabricated on a 7.82mm^2 chip using more advanced process technology. This paper presents the detailed design of a fabricated ODRGA-VLSI chip, the optical reconfiguration circuit, the gate array structure, the CAD layout, and an ODRGA-VLSI chip mounted on an estimation board. This study also includes experimental results regarding the reconfiguration period.

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  • A dynamic reconfiguration circuit for Optically Differential Reconfigurable Gate Arrays

    FUJIME Ryuji, WATANABE Minoru, KOBAYASHI Fuminori

    Technical report of IEICE. ICD   103 ( 510 )   7 - 10   2003.12

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    A new dynamic reconfiguration circuit for Optically Differential Reconfigurable Gate Arrays (ODRGAs) is proposed to reduce the area occupied by its reconfiguration circuit on a VLSI chip. A dynamic circuit technique is partially introduced into our previously proposed reconfiguration circut using a static technique and the implementation area of the circuit is reduced 42% compared with that of a static technique. This paper shows a new dynamic reconfiguration circuit, its layout for 0.35 um CMOS process, and HSPICE simulation results.

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  • A neural network using finite physical quantities

    WATANABE Minoru, KOBAYASHI Fuminori

    IEICE technical report. Neurocomputing   101 ( 735 )   115 - 118   2002.3

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    In this paper, a novel neural network model using finite physical quantities is proposed. A quantized learning algorithm and a generation method of negative neurons for the model and the recalling capabilities which was confirmed by simulations are presented.

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  • An optimum implementation of Neural Network on FPGA

    Sotohebo T., Watanabe M., Kobayashi F.

    2002   115 - 115   2002

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Presentations

  • Vitis AIを用いたCNN実装

    後山 晃彦, 渡邊 誠也, 名古屋 彰, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2021.9.10 

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  • Radiation-hardened optically reconfigurable gate array Invited International conference

    Minoru Watanabe

    The Collaborative Conference on Laser  2020.4 

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    Venue:Dubai, UAE,  

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  • Multi-context holographic memory exploiting a wavelength-dependent optimization technique Invited International conference

    Minoru Watanabe, Junya Ishido

    IEEE International Conference on Photonics  2020.3 

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    Venue:Kelantan, Malaysia  

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  • Place and route tool for optically reconfigurable gate arrays with fault cells International conference

    Yuki Takena, Minoru Watanabe

    The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University  2020.3 

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    Venue:Shizuoka University  

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  • Radiation tolerance of a crystal oscillator circuit International conference

    Yuichi Moriya, Minoru Watanabe

    The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University  2020.3 

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    Venue:Shizuoka University  

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  • Implementation of RISC-V Processor on MAX-10 FPGA International conference

    Md Roman Ahmed, Minoru Watanabe

    The 6th International Symposium toward the Future of Advanced Researches in Shizuoka University  2020.3 

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    Venue:Shizuoka University  

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  • Radiation-hardened optically reconfigurable gate array using a multi-wavelength holographic memory International conference

    Junya Ishido, Minoru Watanabe

    IEEE Workshop on Silicon Errors in Logic – System Effects  2020.2 

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    Venue:Stanford University, CA, USA  

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  • 光再構成型ゲートアレイのマルチコンテキストスクラビングの耐放射線試験

    髙木雄介,渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2020.1.24 

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    Venue:慶應義塾大学  

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  • 耐放射線光再構成型ゲートアレイのイメージセンサ応用

    喜夛本凌平,渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2020.1.24 

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    Venue:慶應義塾大学  

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  • マルチコンテキスト高速スクラビング

    髙木雄介,渡邊 実

    第63回宇宙科学技術連合講演会  2019.11.7 

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    Venue:アスティとくしま  

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  • 多重化回路実装におけるソフトエラー耐性評価

    渡邊 将己,渡邊 実

    第63回宇宙科学技術連合講演会  2019.11.7 

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    Venue:アスティとくしま  

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  • 並列処理指向型光再構成型ゲートアレイVLSIにおける回路実装

    伊藤 嘉俊,渡邊 実

    第63回宇宙科学技術連合講演会  2019.11.7 

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    Venue:アスティとくしま  

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  • Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation International conference

    Masaki Watanabe, Minoru Watanabe

    IEEE Asia Pacific Conference on Circuits and Systems  2019.11 

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    Venue:Bangkok, Tailand  

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  • Effect of radiation dose of Gamma-Ray irradiation on volume gratings using liquid crystal composites International conference

    Makishi Toda, Akifumi, Ogiwara, Minoru Watanabe

    Microoptics Conference  2019.11 

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    Venue:Toyama, Japan  

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  • Parallel-operation-oriented optically reconfigurable gate array VLSI International conference

    Hirotoshi Ito, Minoru Watanabe

    IEEE International Conference on Space Optical Systems and Applications  2019.10 

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    Venue:Portland, USA  

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  • 光再構成型ゲートアレイのマルチコンテキスト色構成

    石堂 順也,渡邊 実

    第80回応用物理学会秋季学術講演会  2019.9.21 

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    Venue:北海道大学札幌キャンパス  

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  • 三重実装が可能な光再構成型ゲートアレイVLSI

    吉永 透,渡邊 実

    日本原子力学会 2019年秋の大会  2019.9.13 

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    Venue:富山大学五福キャンパス  

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  • 水晶振動子を用いた発振回路の放射線耐性

    渡邊 将己,旗持 卓美,渡邊 実

    日本原子力学会 2019年秋の大会  2019.9.13 

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    Venue:富山大学五福キャンパス  

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  • 光再構成型ゲートアレイVLSIの放射線による特性劣化の評価

    伊藤 嘉俊,渡邊 実

    2019年電子情報通信学会ソサイエティ大会  2019.9.11 

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  • Total-ionizing-dose degradation analysis of an optoelectronic field programmable gate array International conference

    Hirotoshi Ito, Minoru Watanabe

    IEEE International System-on-Chip Conference  2019.9 

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    Venue:Singapore  

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  • FPGA implementation of a robot control algorithm International conference

    Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano

    International Conference on Emerging Technologies and Factory Automation  2019.9 

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    Venue:Zaragoza, Spain  

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  • A 1.15 Grad total-ionizing-dose tolerance parallel operation oriented optically reconfigurable gate array VLSI International conference

    Takumi Fujimori, Minoru Watanabe

    IEEE International Workshop on Metrology for AeroSpace  2019.6 

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    Venue:Torino, Italy  

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  • An optically reconfigurable gate array workable under a strong gamma radiation environment International conference

    Shinya Fujisaki, Takumi Fujimori, Minoru Watanabe

    IEEE- Workshop on Microelectronics and Electron Devices  2019.4 

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    Venue:Boise State University, USA  

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  • 1 Grad radiation-hardened optoelectronic embedded system International conference

    M. Watanabe

    IEEE Workshop on Silicon Errors in Logic – System Effects  2019.3 

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    Venue:Stanford, California, USA  

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  • ロボット制御アルゴリズムのFPGAへの実装

    髙木雄介, 渡邊 実, 佐野健太郎

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2018.12.6 

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    Language:Japanese  

    Venue:サテライトキャンパスひろしま  

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  • 3重実装・光再構成型ゲートアレイVLSI

    吉永 透, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2018.12.6 

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    Language:Japanese  

    Venue:サテライトキャンパスひろしま  

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  • Soft-error tolerance of an optically reconfigurable gate array VLSI International conference

    T. Fujimori, M. Watanabe

    INTERNATIONAL CONFERENCE ON SYSTEMS ENGINEERING  2018.12 

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  • 耐放射線・光電子デバイス Invited

    渡邊 実

    10回 静岡大-核融合科学研究所連携研究フォーラム  2018.11.30 

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    Venue:静岡大学  

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  • Radiation-hardened motor controller International conference

    T. Hatamochi, M. Watanabe

    Fukushima Research Conference “Radiation Hardness and Smartness in Remote Technology for Nuclear Decommissioning”  2018.11 

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    Venue:Fukushima, Japan  

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  • Many modular redundancy implementation on CPLD International conference

    2018.11 

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    Venue:Fukushima, Japan  

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  • Full-hardware robot controller International conference

    2018.11 

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    Venue:Fukushima, Japan  

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  • An optically reconfigurable gate array using four liquid crystal spatial light modulators

    Y. Takaki, M. Watanabe

    IEEE CPMT Symposium Japan  2018.11 

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    Venue:Kyoto Univ.  

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  • Radiation-hardened power supply unit International conference

    2018.11 

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    Venue:Fukushima, Japan  

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  • Radiation-hardened optically reconfigurable gate array International conference

    2018.11 

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    Venue:Fukushima, Japan  

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  • Triple modular redundancy optically reconfigurable gate array International conference

    2018.11 

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    Venue:Fukushima, Japan  

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  • 光再構成型ゲートアレイVLSIの放射線劣化特性評価

    藤森 卓巳, 渡邊 実

    第63回宇宙科学技術連合講演会  2018.10 

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    Venue:久留米シティープラザ  

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  • 光再構成型ゲートアレイにおける動的再構成

    高木 雄介, 渡邊 実

    第63回宇宙科学技術連合講演会  2018.10 

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    Venue:久留米シティープラザ  

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  • 多重化回路実装におけるソフトエラー耐性の評価

    渡邊 将己, 渡邊 実

    第63回宇宙科学技術連合講演会  2018.10 

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    Venue:久留米シティープラザ  

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  • 超音波センサの耐放射線性能評価

    藤崎 伸也, 渡邊 実

    第63回宇宙科学技術連合講演会  2018.10 

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    Venue:久留米シティープラザ  

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  • Radiation-hardened stabilized power supply unit based on a lithiumion battery International conference

    S. Fujisaki, M. Watanabe

    Radiation and its Effects on Components and Systems conference  2018.9 

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    Venue:Göteborg, Sweden  

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  • Total-Ionizing-Dose Tolerance of the configuration function of MAX3000A CPLDs International conference

    T. Fujimori, M. Watanabe

    Data Workshop  2018.9 

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    Venue:Göteborg, Sweden  

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  • Optically Reconfigurable Gate Array Invited International conference

    M. Watanabe

    DA NEXT BIG THING ROBO  2018.9 

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  • Effects of radiation exposure on volume gratings formed in liquid crystal composites International conference

    A Ogiwara, M. Toda, M. Watanabe, H. Kakiuchida

    2018 KJF International Conference on Organic Materials for Electronics and Photonics  2018.9 

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    Venue:Gifu, Japan  

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  • Ultrasonic sensor system with a 94 Mrad total-ionizing-dose tolerance International conference

    Fujisaki, M. Watanabe

    IEEE International Conference on Semiconductor Electronics  2018.8 

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    Venue:Kuala Lumpur, Malaysia  

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  • A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory International conference

    T. Fujimori, M. Watanabe

    NASA/ESA Conference on Adaptive Hardware and Systems  2018.8 

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    Venue:Edinburgh, UK  

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  • FPGAによる自動車の自動走行コンテストについて

    渡邊 実

    第4回 人工知能とHW/SW協調設計ワークショップ  2018.7 

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    Language:Japanese  

    Venue:てんぶす那覇  

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  • Optically Reconfigurable Gate Array with a triple modular redundancy International conference

    Toru Yoshinaga, Minoru Watanabe

    International Conference on Space Science and Communication  2018.7 

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    Venue:ohor, Malaysia  

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  • High total-ionizing-dose tolerance field programmable gate array International conference

    T. Fujimori, M. Watanabe

    IEEE International Symposium on Circuits and Systems  2018.5 

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  • A 603 Mrad total-ionizing-dose tolerance optically reconfigurable gate array VLSI

    2018.5 

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    Venue:Bali, Indonesia  

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  • An 807 Mrad total dose tolerance of an optically reconfigurable gate array VLSI

    2018.4 

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    Venue:Massachusetts, USA  

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  • 放射線環境でのモータ制御

    旗持卓美, 渡邊実

    電子情報通信学会総合大会  2018.3.23 

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    Venue:東京電機大学  

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  • 光再構成型ゲートアレイVLSIの放射線耐性評価

    藤森卓巳, 渡邊実

    電子情報通信学会総合大会  2018.3.22 

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    Venue:東京電機大学  

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  • 超音波センサの放射線耐性試験

    藤崎伸也, 渡邊実

    電子情報通信学会総合大会  2018.3.21 

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    Venue:東京電機大学  

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  • 光再構成型ゲートアレイの光バスにおけるビットエラーレートの測定

    杉山 和礼, 渡邊実

    電子情報通信学会総合大会  2018.3 

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    Venue:東京電機大学  

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  • FFT implementation using mono-instruction set computer architecture

    2018.2 

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    Venue:Vienna, Austria  

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  • 光再構成型ゲートアレイのトータルドーズ耐性

    藤森卓巳, 渡邊実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2018.1.19 

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    Venue:慶応義塾大学  

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  • FPGA Hardware Accelerator for Holographic Memory Calculations for Optically Reconfigurable Gate Arrays

    2017.11 

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    Venue:Okinawa, Japan  

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  • Holographic memory calculation FPGA accelerator for optically reconfigurable gate array International conference

    2017.11 

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    Venue:Orlando, USA  

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  • Optically reconfigurable gate array driven by a lithium-ion battery

    2017.11 

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    Venue:Kyoto Univ.  

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  • Resistance Evaluation of Holographic Polymer-Dispersed Liquid Crystal Memory for Gamma-Ray Irradiation

    2017.11 

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    Venue:Tokyo, Japan  

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  • 宇宙機器向けホログラムメモリ計算のアクセラレーション

    藤森卓巳, 渡邊 実

    第61回宇宙科学技術連合講演会  2017.10 

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  • VTRを使用したMono Instruction Set Computer の性能解析

    榛葉大樹, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2017.9.25 

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    Venue:(株) ドワンゴ  

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  • 光再構成型ゲートアレイのホログラムメモリ計算のハードウェアアクセラレーション

    藤森卓巳, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2017.9.25 

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    Venue:(株) ドワンゴ  

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  • Radiation Tolerance Demonstration of High-Speed Scrubbing on an Optically Reconfigurable Gate Array International conference

    2017.8 

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    Venue:Munich, Germany  

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  • Asynchronous optical bus for optical VLSIs

    2017.8 

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    Venue:Luton, UK  

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  • Multi-context scrubbing method

    T. Fujimori, M. Watanabe

    IEEE International Midwest Symposium on Circuits and Systems  2017.8 

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  • High-speed scrubbing based on asynchronous optical configuration International conference

    2017.7 

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    Venue:Singapore  

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  • Development of a radiation-hardened embedded system used for robots decommissioning nuclear reactor International conference

    M. Watanabe

    ACTINIDES2017  2017.7 

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  • 500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA International conference

    2017.7 

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    Venue:Pasadena, USA  

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  • Gate Density Advantage of Parallel -Operation-Oriented FPGA Architecture International conference

    National Aerospace & Electronics Conference  2017.6 

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    Venue:Dayton, USA  

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  • 光再構成型ゲートアレイのホログラムメモリ部の耐放射線性能試験

    伊藤芳純, 渡邊 実, 荻原昭文

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2017.5.22 

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    Language:Japanese  

    Venue:登別温泉第一滝本館  

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  • 光再構成型ゲートアレイ向け耐放射線安定化電源

    藤﨑伸也, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2017.5.22 

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    Venue:登別温泉第一滝本館  

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  • マルチコンテキストを用いた高速光スクラビング

    藤森卓巳, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2017.5.22 

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    Venue:登別温泉第一滝本館  

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  • Error injection analysis for triple modular and penta-modular redundancies

    R. Terada, M. Watanabe

    International Symposium on Next-Generation Electronics  2017.5 

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    Venue:Keelung, Taiwan  

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  • 300 Mrad total-ionizing-dose tolerance of a holographic memory on an optically reconfigurable gate array International conference

    2017.5 

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    Venue:Keelung,Taiwan  

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  • Radiation tolerance experiments for a motor controller International conference

    2017.5 

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    Venue:Keelung, Taiwan  

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  • 電源回路の放射線耐性試験

    藤﨑伸也, 渡邊実

    電子情報通信学会総合大会  2017.3.24 

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    Venue:名城大学  

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  • モータコントローラの放射線耐性試験

    旗持卓美, 渡邊実

    電子情報通信学会総合大会  2017.3.23 

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    Venue:名城大学  

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  • 光再構成型ゲートアレイの高速スクラビング手法

    藤森卓巳, 渡邊実

    電子情報通信学会総合大会  2017.3.22 

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  • 液晶ホログラムメモリへの放射線照射による光学特性の影響

    荻原 昭文, 渡邊 実, 伊藤 芳純

    第64回応用物理学会春季学術講演会  2017.3.17 

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    Venue:パシフィコ横浜  

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  • ハードウェアアクセラレータの放射線耐性

    寺田涼, 渡邊実

    電子情報通信学会総合大会  2017.3 

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  • マルチコンテキスト光再構成型ゲートアレイの暗点雑音測定

    榛葉大樹, 渡邊実

    電子情報通信学会総合大会  2017.3 

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  • Photodiode Response Measurement Technique using Low Laser Intensity

    Bharat Ramanathan, Minoru Watanabe

    電子情報通信学会総合大会  2017.3 

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  • ホログラムメモリの放射線耐性評価

    伊藤芳純, 渡邊 実, 荻原昭文

    電子情報通信学会総合大会  2017.3 

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  • Optically reconfigurable gate array platform for Mono-instruction set computer arc International conference

    2017.1 

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    Venue:Las Vegas, USA  

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  • A 200 Mrad radiation tolerance of a polymer-dispersed liquid crystal holographic memory International conference

    2016.12 

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    Venue:Sydney, Australia  

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  • A 300 Mrad total-ionizing dose experiment of lasers used for holographic memories International conference

    2016.11 

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    Venue:Kuala Lumpur, Malaysia  

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  • Compilation time advantage of parallel-operation-oriented optically reconfigurable gate arrays International conference

    2016.11 

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    Venue:Melbourne, Australia  

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  • レーザアレイの放射線耐性評価

    赤部知也, 渡邊実

    第15回情報科学技術フォーラム(FIT2016)  2016.9.9 

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    Venue:富山大学  

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  • ホログラムメモリの放射線耐性試験

    伊藤芳純, 渡邊実, 荻原昭文

    第15回情報科学技術フォーラム(FIT2016)  2016.9.9 

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    Venue:富山大学  

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  • Photodiode sensitivity measurement methodology using a low light intensity for optically reconfigurable gate arrays International conference

    2016.8 

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    Venue:Nagoya, Japan  

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  • Direct optical communication on an optically reconfigurable gate array International conference

    2016.8 

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    Venue:Luton, UK  

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  • Radiation tolerance of a MEMS mirror device International conference

    2016.7 

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    Venue:Singapore  

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  • Demonstrating a holographic memory having 100 Mrad total-ionizing-dose tolerance International conference

    2016.7 

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    Venue:London, UK  

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  • Architecture-independence negative logic implementation for optically reconfigurable gate arrays International conference

    2016.7 

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    Venue:London, UK  

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  • 光再構成型ゲートアレイの光入力

    榛葉大樹, 古川晋也, Ili Shairah, Abdul Halim, 渡邊 実, 小林史典

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2016.5.19 

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    Venue:富士通研究所 岡田記念ホール  

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  • A 180 Mrad Total-Ionizing Dose Experiment for Laser Arrays on Optically Reconfigurable Gate Arrays International conference

    2016.5 

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    Venue:San Diego, USA  

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  • 液晶ホログラムメモリへの角度多重記録におけるレーザ露光条件の改善

    前田雄大, 荻原昭文, 渡邊 実

    第63回応用物理学会春季学術講演会  2016.3 

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  • Full FPGA Game Machine International conference

    2016.1 

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    Venue:Las Vegas, USA  

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  • Reconfiguration performance recovery method on optically reconfigurable gate arrays International conference

    2016.1 

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    Venue:Kolkata, India  

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  • FPGA Trax Solver based on a Neural Network Design International conference

    2015.12 

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    Venue:Queenstown, New Zealand  

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  • 並列処理指向・光再構成型ゲートアレイへのTMR実装

    伊藤芳純, 渡邊 実

    デザインガイア2015 -VLSI設計の新しい大地  2015.12 

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    Venue:長崎県勤労福祉会館  

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  • 光再構成型ゲートアレイの反転コンフィギュレーション手法のフォールトトレランス評価

    榛葉大樹, 渡邊 実

    デザインガイア2015 -VLSI設計の新しい大地  2015.12 

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    Language:Japanese  

    Venue:長崎県勤労福祉会館  

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  • Radiation tolerance experiments of a laser array on an optically reconfigurable gate array International conference

    2015.12 

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  • Optically Reconfigurable Gate Array Prototype System International conference

    Masato Seo, Minoru Watanabe

    The 1st RIS-MJIIT Workshop on Renewable and Sustainable Integrated Systems 2015  2015.12 

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  • Triple modular redundancy on parallel-operation-oriented optically reconfigurable gate arrays International conference

    2015.12 

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    Venue:Bali, Indonesia  

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  • Total-ionizing-dose tolerance analysis of an optically reconfigurable gate array VLSI International conference

    2015.12 

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    Venue:Bali, Indonesia  

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  • Sustainable advantage of a parallel configuration in an optical FPGA

    2015.12 

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    Venue:Nagoya, Japan  

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  • Total-Ionizing Dose Tolerance of the Serial Configuration on Cyclone II FPGA

    2015.10 

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    Venue:New Orleans, USA  

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  • Effect of laser exposure condition on formation of holographic emmory by angle-multiplexing recording using liquid crystal composittes

    2015.10 

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    Venue:Fukuoka, Japan  

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  • Fresnel Lens Radiation Shield for Photodiode International conference

    2015.10 

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    Venue:New Orleans, USA  

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  • Triple Modular Redundancy on Parallel-Operation- Oriented FPGA Architectures for Optical Communications International conference

    2015.10 

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    Venue:New Orleans, USA  

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  • 100 Mrad Total-Ionizing Dose Tolerance Experiment of a Laser Array International conference

    2015.10 

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    Venue:New Orleans, USA  

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  • Investigating the radiation tolerance of a laser array for an optically reconfigurable gate array International conference

    2015.10 

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    Venue:Fukuoka, Japan  

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  • 放射線でダメージを受けた光再構成型ゲートアレイのリカバリー手法

    赤部知也, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2015.9.19 

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    Language:Japanese  

    Venue:愛媛大学  

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  • Formation of Holographic Memory by Angle-multiplexing Recording in Liquid Crystal Composites International conference

    2015.8 

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    Venue:Busan, Korea  

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  • 光再構成型ゲートアレイの高速スクラビング

    藤森卓巳, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2015.6.20 

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    Language:Japanese  

    Venue:京都大学  

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  • Holographic scrubbing technique for a programmable gate array International conference

    2015.6 

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    Venue:Montreal, Canada  

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  • Radiation-hardened Optically Reconfigurable Gate Array Using a Negative Logic Configuration without Necessity of a Dedicated VLSI

    2015.5 

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    Venue:San Diego, USA  

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  • High-resolution configuration of optically reconfigurable gate arrays International conference

    2015.5 

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    Venue:Taipei, Taiwan  

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  • Design of a parallel-operation-oriented FPGA International conference

    2015.5 

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    Venue:Taipei, Taiwan  

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  • 並列処理指向型FPGAアーキテクチャ

    藤森卓巳, 渡邊 実

    再生可能集積システム時限研究会  2015.4.17 

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    Language:Japanese  

    Venue:明治大学  

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  • Total ionizing dose effects of optical components on an optically reconfigurable gate array

    2015.4 

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    Venue:Bochum, Germany  

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  • 光再構成型ゲートアレイにおけるレーザアレイに対する放射線耐性

    赤木 昂太, 渡邊 実

    日本光学会 情報フォトニクス研究グループ・関東学生研究論文講演会  2015.3.10 

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    Venue:静岡大学  

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  • MEMSホログラムメモリの放射線耐性

    藤森 卓巳, 渡邊 実

    日本光学会 情報フォトニクス研究グループ・関東学生研究論文講演会  2015.3.10 

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    Venue:静岡大学  

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  • 光再構成型ゲートアレイのホログラムメモリの放射線耐性

    窪田 貴之, 渡邊 実

    日本光学会 情報フォトニクス研究グループ・関東学生研究論文講演会  2015.3.10 

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    Venue:静岡大学  

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  • 2 並列ゲートアレイをもつ並列処理指向型光再構成型ゲートアレイVLSI

    藤森卓巳, 渡邊 実

    電子情報通信学会・総合大会・ISS特別企画学生ポスターセッション  2015.3 

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  • Parallel-Operation-Oriented Optically Reconfigurable Gate Array International conference

    T. Fujimori, M. Watanabe

    GI/ITG International Conference on Architecture of Computing Systems  2015.3 

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    Venue:Porto, Portugal  

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  • 光再構成型ゲートアレイの並列構成法の放射線耐性に関する一考察

    伊藤宏幸, 森脇 烈, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2015.1.29 

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    Language:Japanese  

    Venue:慶応大学  

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  • Radiation tolerance of optically reconfigurable gate arrays International conference

    2015.1 

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    Venue:Shizuoka, Japan  

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  • Radiation tolerance experiment for a dynamically reconfigurable vision architecture International conference

    M. Watanabe, S. Kawahito

    International Conference on Advances in Computing, Electronics and Electrical Technology  2014.12 

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    Venue:Kuala Lumpur, Malaysia  

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  • 光再構成型ゲートアレイの色構成手法の放射線耐性

    藤森卓巳, 渡邊実

    宇宙科学技術連合講演会  2014.11.14 

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    Venue:長崎ブリックホール  

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  • 光再構成型ゲートアレイの4色カラー構成

    藤森卓巳, 渡邊実

    再生可能集積システム時限研究会  2014.10.18 

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    Language:Japanese  

    Venue:東洋大学  

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  • Dependable Optically Reconfigurable Gate Array Architecture Invited

    M. Watanabe

    International Symposium on Optical Memory  2014.10 

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  • 光再構成型ゲートアレイのホログラムメモリ部の放射線耐性

    森脇烈, 伊藤宏幸, 前川輝, 渡邊実, 荻原昭文

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2014.9.18 

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    Venue:杜の宿(宮島)  

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  • 並列処理指向・光再構成型ゲートアレイVLSI

    藤森卓巳, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2014.9.18 

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    Venue:杜の宿(宮島)  

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  • Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture International conference

    Y. Kamikubo, M. Watanabe, Shoji Kawahito

    IEEE International Symposium on Circuits and Systems  2014.6 

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    Venue:Melbourne, Australia  

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  • A parallel-operation-oriented FPGA architecture

    M. Watanabe

    International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies  2014.6 

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    Venue:Sendai, Japan  

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  • An optically reconfigurable gate array with an angle-multiplexed holographic memory International conference

    R. Moriwaki, H. Maekawa, A. Ogiwara, M. Watanabe

    IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits  2014.5 

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    Venue:Texas, USA  

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  • Radiation tolerance of color configuration on an optically reconfigurable gate array International conference

    T. Fujimori, M. Watanabe

    Reconfigurable Architectures Workshop  2014.5 

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    Venue:Phoenix, USA  

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  • Dependable optically differential reconfigurable gate array International conference

    M. Seo, M. Watanabe

    International Conference on Space Optical Systems and Applications  2014.5 

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    Venue:Kobe, Japan  

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  • Enhanced radiation tolerance of an optically reconfigurable gate array by exploiting an inversion/ non-inversion implementation International conference

    T. Yoza, M. Watanabe

    International Workshop on Applied Reconfigurable Computing, Lecture Notes in Computer Science  2014.4 

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    Venue:Algarve, Portugal  

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  • 色構成手法を用いた光再構成型ゲートアレイの放射線耐性

    藤森卓巳, 渡邊 実

    電子情報通信学会 総合大会 ISS特別企画「学生ポスターセッション」  2014.3.20 

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    Language:Japanese  

    Venue:新潟大学  

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  • 高密度ダイナミック光再構成型ゲートアレイ

    窪田 貴之, 渡邊 実

    電子情報通信学会 総合大会 ISS特別企画「学生ポスターセッション」  2014.3.20 

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    Venue:新潟大学  

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  • 角度多重記録による液晶ホログラムメモリを用いた光再構成試験

    荻原昭文, 前川 輝, 渡邊 実, 森脇 烈

    第61回応用物理学会春季学術講演会  2014.3.18 

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    Venue:青山学院大学  

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  • 光再構成型ゲートアレイへの可変サイズスポット構成手法

    赤木昂太, 渡邊 実

    電子情報通信学会東海支部 卒業研究発表会  2014.3.10 

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    Venue:三重大学  

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  • 光再構成型ゲートアレイへの色構成手法

    藤森卓巳, 渡邊 実

    電子情報通信学会東海支部 卒業研究発表会  2014.3.10 

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    Venue:三重大学  

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  • 差分光再構成型ゲートアレイの放射線耐性向上手法

    瀬尾真人, 渡邊 実

    電子情報通信学会東海支部 卒業研究発表会  2014.3.10 

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    Venue:三重大学  

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  • A high-density optically reconfigurable gate array VLSI using variable holographic memory pattern International conference

    K. Akagi, M. Watanabe

    International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems  2014.3 

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    Venue:Hawaii, USA  

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  • Formation of holographic memory for optically-reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid-crystal composites International conference

    A. Ogiwara, H. Maekawa, M. Watanabe, R. Moriwaki

    Proceedings of SPIE  2014.2 

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    Venue:San Francisco, USA  

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  • FPGA Blokus Duo Solver using a massively parallel architecture International conference

    T. Yoza, R. Moriwaki, Y. Torigai, Y. Kamikubo, T. Kubota, T. Watanabe, T. Fujimori, H. Ito, M. Seo, K. Akagi, Y. Yamaji, M. Watanabe

    nternational Conference on Field-Programmable Technology  2013.12 

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    Venue:Kyoto, Japan  

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  • Many-module redundancy implementation of mono instruction set computers for 3D optical FPGAs International conference

    Y. Shirahashi, M. Watanabe

    IEEE Electrical Design of Advanced Packaging & Systems  2013.12 

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  • Color configuration method for an optically reconfigurable gate array International conference

    T. Fujimori, M. Watanabe

    International Conference on Field-Programmable Technology  2013.12 

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    Venue:Kyoto, Japan  

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  • Mono-instruction set computer architecture on a 3D optically reconfigurable gate array International conference

    H. Ito, M. Watanabe

    IEEE Electrical Design of Advanced Packaging & Systems  2013.12 

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    Venue:Nara, Japan  

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  • 差分光再構成型ゲートアレイの放射線耐性向上実装手法

    瀬尾真人, 渡邊 実

    リコンフィギャラブルシステム研究会  2013.11.28 

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    Venue:鹿児島県文化センター(宝山ホール)  

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  • 負論理回路実装を活用した光再構成型ゲートアレイの放射線耐性の向上手法

    森脇烈, 渡邊実

    宇宙科学技術連合講演会  2013.10.9 

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    Venue:米子コンベンションセンター  

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  • Angle-multiplexing recording of multi-context for optically reconfigurable gate array in holographic memory using liquid crystal composites International conference

    A. Ogiwara, H. Maekawa, M. Watanabe, R. Moriwaki

    Microoptics Conference (MOC’13)  2013.10 

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    Venue:Tokyo, Japan  

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  • A dynamic optically reconfigurable gate array using a blue laser,” International Conference on Photonics International conference

    T. Kubota, M. Watanabe

    International Conference on Photonics  2013.10 

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    Venue:Melaka, Malaysia  

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  • フーリエ変換を用いた光再構成型ビジョンチップによる画像認識

    上窪勇貴, 渡邊実, 川人祥二

    電気関係学会 東海支部連合大会  2013.9.24 

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    Language:Japanese  

    Venue:静岡大学  

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  • 光再構成型ゲートアレイへの色構成手法

    藤森卓巳, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2013.9.19 

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    Language:Japanese  

    Venue:北陸先端科学技術大学院大学  

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  • 光再構成型ゲートアレイへの可変サイズスポット構成手法 International conference

    赤木昂太, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2013.9.19 

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    Language:Japanese  

    Venue:北陸先端科学技術大学院大学  

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  • Image recognition operation on a dynamically reconfigurable vision architecture International conference

    Y. Kamikubo, M. Watanabe, S. Kawahito

    International Conference on Field Programmable Logic and Applications  2013.9 

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    Venue:Porto, Portugal  

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  • A fine-grained dependable optically reconfigurable gate array as a multi-soft-core processor platform International conference

    R. Moriwaki, M. Watanabe

    IEEE 7th International Symposium on Embedded Multicore SoCs  2013.9 

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    Venue:Tokyo, Japan  

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  • 光再構成用コンテキストデータの液晶ホログラムへの角度多重記録

    前川 輝, 荻原昭文, 渡邊 実, 森脇 烈

    応用物理学会秋季学術講演会  2013.9 

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    Language:Japanese  

    Venue:同志社大学  

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  • Fourier Transformation on an Optically Reconfigurable Gate Array International conference

    H. Ito, M. Watanabe

    IEEE International Midwest Symposium on Circuits & Systems  2013.8 

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    Venue:USA  

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  • Formation of Holographic Memory by Recording of Multi-context in Liquid Crystal Composites International conference

    A. Ogiwara, H. Maekawa, M. Watanabe, R. Moriwaki

    Conference on Lasers and Electro-Optics Pacific Rim  2013.7 

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    Venue:Kyoto, Japan  

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  • Configuration on an optically reconfigurable gate array under the maximum 120°C temperature condition International conference

    R. Moriwaki, M. Watanabe, A. Ogiwara

    OptoElectronics and Communications Conference  2013.7 

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    Venue:Kyoto, Japan  

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  • A 7-depth search FPGA Connect6 Solver International conference

    R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, A. Tanigawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe

    nternational Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  2013.6 

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    Venue:Edinburgh, United Kingdom  

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  • A 4-configuration-context optically reconfigurable gate array with a MEMS interleaving method International conference

    Y. Yamaji, M. Watanabe

    NASA/ESA Conference on Adaptive Hardware and Systems  2013.6 

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    Venue:Torino, Italy  

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  • A dependability-increasing demonstration for a 16-configuration context optically reconfigurable gate array International conference

    A. Tanigawa, M. Watanabe

    International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  2013.6 

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    Venue:Edinburgh, United Kingdom  

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  • MEMS interleaving method for optically reconfigurable gate arrays International conference

    Y. Yamaji, M. Watanabe

    IEEE International Conference on Electro/Information Technology  2013.5 

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    Venue:South Dakota, USA  

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  • Dependability-increasing technique on a multi-context optically reconfigurable gate array International conference

    A. Tanigawa, M. Watanabe

    IEEE International Symposium on Circuits and Systems  2013.5 

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    Venue:Beijing, China  

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  • 0.18 μm CMOS process photodiode memory

    T. Kubota, M. Watanabe

    IEEE International Symposium on Circuits and Systems  2013.5 

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    Venue:Beijing, China  

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  • Power consumption of mono-instruction set computers (MISCs) International conference

    H. Ito, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips  2013.4 

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    Venue:Yokohama, Japan  

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  • 2コンテキストMEMS光再構成型ゲートアレイ

    山地勇一郎, 渡邊実

    電子情報通信学会 総合大会  2013.3 

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    Venue:岐阜大学  

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  • Dependability-increasing method of processors under a space radiation environment International conference

    2013.3 

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    Venue:Los Angeles, USA  

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  • Temperature Dependable Holographic Memory Using Holographic Polymer-dispersed Liquid Crystal International conference

    2013.3 

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    Venue:Taipei, Taiwan  

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  • 16コンテキストを活用した光再構成型ゲートアレイの放射線耐性の向上方法

    谷川彰, 渡邊実

    電子情報通信学会 総合大会 ISS特別企画「学生ポスターセッション」  2013.3 

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    Venue:岐阜大学  

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  • MISCディペンダブルシステムのStratix V FPGAへの実装

    白橋侑弥, 渡邊実

    電子情報通信学会 総合大会 ISS特別企画「学生ポスターセッション」  2013.3 

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    Venue:岐阜大学  

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  • 光再構成型ゲートアレイ用液晶ホログラムメモリの温度依存性

    荻原 昭文, 志智 弘, 渡邊実, 森脇 烈

    応用物理学会春季学術講演会  2013.3 

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    Venue:神奈川工科大学  

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  • 4コンテキストMEMS光再構成型ゲートアレイ

    山地勇一郎, 渡邊実

    電子情報通信学会 総合大会 ISS特別企画「学生ポスターセッション」  2013.3 

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    Venue:岐阜大学  

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  • マルチコンテキストを活用した光再構成型ゲートアレイの放射線耐性の向上方法

    谷川彰, 渡邊実

    卒業研究発表会,電子情報通信学会東海支部  2013.3 

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    Language:Japanese  

    Venue:名古屋大学  

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  • 高速動的再構成を活用したディペンダブルシステムの構成手法

    白橋侑弥, 渡邊 実

    卒業研究発表会,電子情報通信学会東海支部  2013.3 

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    Venue:名古屋大学  

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  • モノ・インストラクション・セット・コンピュータの実装

    伊藤宏幸, 渡邊実

    卒業研究発表会,電子情報通信学会東海支部  2013.3 

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    Venue:岐阜大学  

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  • 0.18 μm CMOSプロセスダイナミック光再構成型ゲートアレイVLSI

    窪田貴之, 渡邊実

    卒業研究発表会,電子情報通信学会東海支部  2013.3 

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    Venue:名古屋大学  

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  • 28nmプロセスFPGAへのモノ・インストラクション・セット・コンピュータの実装

    伊藤宏幸, 渡邊実

    静岡地区計測制御研究発表会  2012.12 

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  • 高速動的再構成を活用したディペンダブルシステムの構成手法

    白橋侑弥, 渡邊実

    第56回宇宙科学技連合講演会  2012.11 

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  • 0.18um CMOS プロセスダイナミック光再構成型ゲートアレイVLSI

    窪田貴之, 渡邊実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2012.11 

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    Venue:九州大学医学部百年講堂  

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  • A 9-configuration-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory International conference

    2012.11 

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    Venue:Shizuoka, Japan  

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  • マルチコンテキストを活用した光再構成型ゲートアレイの放射線耐性の向上方法

    谷川彰, 渡邊実

    第56回宇宙科学技連合講演会  2012.11 

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  • 偏光依存性ホログラムメモリを用いた9コンテキスト光再構成型ゲートアレイ

    森脇烈, 渡邊実, 荻原昭文

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2012.11 

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    Venue:九州大学医学部百年講堂  

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  • 光再構成型ビジョンチップによる16諧調グレーレベル画像認識

    上窪勇貴, 渡邊実, 川人祥二

    電子情報通信学会技術研究報告(VLSI設計技術研究会)  2012.10 

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    Venue:岩手県,ホテルルイズ  

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  • モノ・インストラクション・セット・コンピュータ(MISC)の消費電力解析

    伊藤宏幸, 渡邊実

    電子情報通信学会技術研究報告(VLSI設計技術研究会)  2012.10 

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    Venue:岩手県,ホテルルイズ  

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  • Gray-level image recognition on a dynamically reconfigurable vision architecture International conference

    2012.9 

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    Venue:New York, USA  

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  • モノ・インストラクション・セット・コンピュータ(MISC)の並列実装

    伊藤 宏幸, 渡邊 実

    電気関係学会東海支部連合大会  2012.9 

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  • 高速動的再構成型ビジョンチップアーキテクチャによるアナログ画像検出

    上窪勇貴, 渡邊 実, 川人祥二

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2012.9 

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    Venue:立命館大学  

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  • A uniform partitioning method for Mono-Instruction Set Computer (MISC) International conference

    2012.9 

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    Venue:Melbourne, Australia  

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  • 0.18 μmプロセス反転・非反転光再構成型ゲートアレイVLSI

    渡邊 貴弘, 渡邊 実

    電気関係学会東海支部連合大会  2012.9 

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    Venue:豊橋技術科学大学  

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  • 再構成速度調整アナログビットを含む光再構成型ゲートアレイのコンテキスト重ね合わせによる構成高速化手法

    余座貴志, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会  2012.9 

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    Venue:立命館大学  

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  • A 256-configuration-context MEMS optically reconfigurable gate array International conference

    2012.9 

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    Venue:Kyoto, Japan  

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  • 光再構成型ゲートアレイ用マルチコンテキストデータの液晶ホログラム記録

    荻原昭文, 渡邊実

    第73回応用物理学会学術講演会  2012.9 

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    Venue:愛媛大学  

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  • 0.18 um CMOS process high-sensitive differential optically reconfigurable gate array VLSI International conference

    2012.8 

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    Venue:Amherst, USA  

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  • Inversion/Non-Inversion Reconfiguration Scheme for a 0.18 Um CMOS Process Optically Reconfigurable Gate Array VLSI International conference

    2012.8 

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    Venue:Boise, USA  

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  • A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function International conference

    2012.8 

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    Venue:Oslo, Norway  

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  • Detection and compensation methods of alignment errors between a programmable optically reconfigurable gate array and its writer system International conference

    2012.7 

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    Venue:Dayton, USA  

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  • A 4-configuration Context Fiber-linked Optically Reconfigurable Gate Array International conference

    2012.7 

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    Venue:Busan, Korea  

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  • Optical configuration acceleration on a new optically reconfigurable gate array VLSI using a negative logic implementation International conference

    2012.7 

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    Venue:Las Vegas, USA  

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  • A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array International conference

    2012.6 

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    Venue:Nuremberg, Germany  

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  • 0.18 um CMOS process high-sensitive optically reconfigurable gate array VLSI International conference

    2012.5 

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    Venue:Okinawa, Japan  

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  • FPGA Connect6 Solver with Hardware Sort Units International conference

    2012.5 

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    Venue:Okinawa, Japan  

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  • High speed - low power optical configuration on an ORGA with a phase-modulation type holographic memory International conference

    2012.5 

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    Venue:Shanghai, China  

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  • 光再構成型ゲートアレイの再構成速度調整手法とレーザアレイ故障からの復旧試験

    余座貴志, 渡邊 実

    電子情報通信学会東海支部卒業研究発表会  2012.3 

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    Venue:岐阜大学  

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  • 0.18 μm CMOSプロセス差分光再構成型ゲートアレイVLSI

    渡邊貴弘, 渡邊実

    情報処理学会 全国大会  2012.3 

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    Venue:名古屋工業大学  

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  • 光再構成型ゲートアレイへの三重回路実装

    鳥飼勇希, 渡邊 実

    電子情報通信学会東海支部卒業研究発表会  2012.3 

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    Venue:岐阜大学  

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  • Mono-instruction computer on a dynamically reconfigurable gate array International conference

    2012.3 

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    Venue:Beppu, Japan  

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  • Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arrays International conference

    2012.3 

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    Venue:CUHK, Hong Kong  

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  • A full dynamically reconfigurable vision-chip system including a lens-array International conference

    2012.3 

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    Venue:Beppu, Japan  

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  • 0.18μmプロセス光再構成型ゲートアレイVLSI

    渡邊貴弘, 渡邊実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2012.1 

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    Venue:慶応大学  

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  • Dependable optically reconfigurable gate array Invited

    M. Watanabe

    2012 International Workshop on Advanced Nanovision Science  2012.1 

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  • ダイナミック光再構成型ゲートアレイのレーザアレイ故障からの復旧試験

    余座貴志, 渡邊実

    電子情報通信学会技術研究報告(回路とシステム研究会)  2012.1 

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    Venue:九州大学  

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  • Binary MEMS optically reconfigurable gate array for an artificial brain system International conference

    2012.1 

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    Venue:Beppu, Japan  

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  • 再構成速度調整アナログビットを含む光再構成型ゲートアレイのレーザアレイ故障からの復旧試験

    余座貴志, 渡邊 実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会  2012.1 

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    Venue:慶応大学  

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  • An FPGA Connect6 Solver with a Two-Stage Pipelined Evaluation International conference

    2011.12 

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    Venue:New Delhi, India  

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  • Full liquid crystal spatial light modulator writer system for a programmable optically reconfigurable gate array International conference

    2011.11 

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    Venue:Sendai, Japan  

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  • 光再構成型ゲートアレイの再構成速度調整手法

    余座貴志, 渡邊実

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2011.11 

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    Venue:ニューウェルシティ宮崎  

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  • Multi-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory International conference

    2011.11 

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    Venue:Sendai, Japan  

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  • Holographic memory formed by multi-context reconfiguring for optically reconfigurable gate array

    2011.11 

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    Venue:Sendai, Japan  

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  • Triple module redundancy scheme on an optically reconfigurable gate array International conference

    2011.11 

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    Venue:Jeju, Korea  

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  • レンズアレイを使用した高速動的再構成型ビジョンチップアーキテクチャ

    上窪勇貴, 渡邊実

    電子情報通信学会技術研究報告(信号処理研究会)  2011.10 

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    Venue:宮城県 作並温泉  

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  • 光再構成型ゲートアレイに対する多数決レーザ駆動回路

    渡邊貴弘, 渡邊実

    電気関係学会東海支部連合大会  2011.9 

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    Venue:三重大学  

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  • 動的再構成ビジョンチップアーキテクチャ上での並列テンプレートマッチング処理

    山地勇一郎, 中田浩成, 渡邊 実, 川人祥二

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2011.9 

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    Venue:名古屋大学  

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  • モノ・インストラクション・コンピュータの実装

    仁平優基, 渡邊実

    電気関係学会東海支部連合大会  2011.9 

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    Venue:三重大学  

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  • A 144-configuration context MEMS optically reconfigurable gate array International conference

    2011.9 

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    Venue:Taipei, Taiwan  

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  • 光再構成型ゲートアレイへの三重回路実装

    鳥飼勇希, 渡邊実

    電気関係学会東海支部連合大会  2011.9 

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    Venue:三重大学  

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  • Dependable optically reconfigurable gate array with a phase-modulation type holographic memory International conference

    2011.8 

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    Venue:Chania, Crete, Greece  

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  • Novel dynamic module multiple redundancy for optically reconfigurable gate arrays Invited

    M. Watanabe

    IEEE International Midwest Symposium on Circuits & Systems  2011.8 

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  • Dynamic reconfiguration on a dynamically reconfigurable vision-chip architecture

    A. Gundjalam, M. Watanabe

    International Conference on engineering of reconfigurable systems and algorithms  2011.7 

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  • Parallel Template Matching Operations on a Dynamically Reconfigurable Vision-Chip Architecture International conference

    2011.6 

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    Venue:Bordeaux, France  

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  • Optically reconfigurable gate array with a polymer-dispersed liquid crystal holographic memory International conference

    2011.6 

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    Venue:California, USA  

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  • A MEMS writer system embedded for a programmable optically reconfigurable gate array International conference

    2011.6 

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    Venue:London, United Kingdom  

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  • A 16-laser array for an optically reconfigurable gate array International conference

    2011.5 

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    Venue:Santa Monica, USA  

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  • 位相ホログラムを用いたディペンダブル光再構成型ゲートアレイ

    渡邊貴弘, 渡邊実

    LSIとシステムのワークショップ  2011.5 

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    Venue:北九州国際会議場  

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  • A configuration speed acceleration method for a sequential circuit using a negative logic implementation International conference

    2011.5 

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    Venue:Santa Monica, USA  

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  • 位相ホログラムを用いた光再構成型ゲートアレイ

    渡邊貴弘, 渡邊実

    光エレクトロニクス研究会  2011.5 

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  • 256コンテキストMEMS光再構成型ゲートアレイ

    山地勇一郎, 渡邊実

    リコンフィギャラブルシステム研究会  2011.5 

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    Venue:北海道大学  

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  • Reduction method of refresh cycles for a dynamic optically reconfigurable gate array International conference

    2011.4 

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    Venue:Yokohama, Japan  

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  • 宇宙空間用ロバスト・プログラマブルデバイス

    渡邊 貴弘, 渡邊 実

    電子情報通信学会 卒業研究発表会  2011.3 

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  • 動的光再構成型ビジョンチップを用いたテンプレートマッチング

    中田 浩成, 渡邊 実

    電子情報通信学会 卒業研究発表会  2011.3 

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  • MEMS interleaving read operation of a holographic memory for optically reconfigurable gate arrays International conference

    2011.3 

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    Venue:United Kingdom, March  

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  • Programming Options for an Optical FPGA with Clockwise Dynamic Reconfigurability International conference

    2011.3 

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    Venue:Macao, China  

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  • MEMSマルチコンテキスト 光再構成型ゲートアレイ

    山地 勇一郎, 渡邊 実

    電子情報通信学会 卒業研究発表会  2011.3 

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  • プログラマブル光再構成型ゲートアレイとDMDを用いたライター

    久保田,渡邊

    レーザー学会学術講演会第31回年次大会  2011.1 

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    Venue:電気通信大学  

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  • MEMSダイナミック光再構成型ゲートアレイにおけるMEMS組立精度

    森田,渡邊

    電子情報通信学会技術研究報告(VLIS設計研究会)  2011.1 

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    Language:Japanese  

    Venue:慶応大学  

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  • A 64-context MEMS optically reconfigurable gate array International conference

    2010.12 

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    Venue:Beijing, China  

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  • Background light affect of a dynamically reconfigurable vision-chip architecture International conference

    2010.12 

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    Venue:Sendai, Japan  

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  • ホログラム閾値可変によるMEMSダイナミック光再構成型ゲートアレイの動作効率改善法

    森田,渡邊

    第8回情報学ワークショップ(WiNF2010)  2010.12 

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    Venue:名古屋大学  

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  • Othello solver based on a soft-core MIMD processor array International conference

    2010.12 

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    Venue:Beijing, China  

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  • Multi-context programmable optically reconfigurable gate array using a silver-halide holographic memory International conference

    2010.12 

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    Venue:Sendai, Japan  

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  • ホログラムメモリシステムのレーザーアレイ故障の復旧方法

    渡邊貴弘, 渡邊実

    第54回宇宙科学技術連合講演会  2010.11 

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    Venue:静岡県コンベンションアーツセンター「グランシップ」  

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  • A retention time improvement method for a MEMS dynamic optically reconfigurable gate array International conference

    2010.11 

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    Venue:Nagoya, Japan  

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  • ダイナミック光再構成型ゲートアレイの動的部分再構成の性能評価

    グンジャラム アマルジャルガル,渡邊

    電子情報通信学会技術研究報告(電子部品・材料研究会)  2010.11 

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    Venue:九州大学  

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  • High-speed fiber-linked remote reconfiguration International conference

    2010.11 

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    Venue:Fukuoka, Japan  

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  • Template matching operations on a dynamically reconfigurable vision-chip architecture International conference

    2010.10 

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    Venue:Tokyo, Japan  

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  • Development of optically reconfigurable gate arrays Invited

    M. Watanabe

    International Symposium on Optical Memory  2010.10 

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  • Fault tolerance of a holographic storage system International conference

    2010.10 

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    Venue:Tokyo, Japan  

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  • Formation of holographic memory using subwavelength grating mask for optically reconfigurable gate array International conference

    2010.10 

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    Venue:Hsinchu, Taiwan  

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  • Recovery method for a laser array failure on Dynamic Optically Reconfigurable Gate Arrays International conference

    2010.10 

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    Venue:Kyoto, Japan  

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  • Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array International conference

    2010.9 

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    Venue:Las Vegas, USA  

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  • Programmable optically reconfigurable gate array using a silver-halide holographic memory including six configuration contexts International conference

    2010.9 

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    Venue:Tokyo, Japan  

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  • 光再構成型ゲートアレイの応用 Invited

    渡邊 実

    リコンフィギャラブル研究会  2010.9 

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  • 光再構成型ゲートアレイにおけるMEMSアドレッシング技術

    森田,渡邊

    リコンフィギャラブルシステム研究会  2010.9 

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    Venue:静岡大学  

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  • 高速動的光再構成型イメージセンサのよる4点のテンプレートマッチング

    中田, 渡邊実

    機構デバイス研究会  2010.8 

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    Venue:千歳アルカディアプラザ  

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  • A binary MEMS Optically Reconfigurable Gate Array International conference

    2010.8 

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    Venue:Yamagata, Japan  

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  • 偏光依存性ホログラムメモリの偏光スイッチングを用いた光再構成試験

    間渕,渡邊, 荻原,小林

    平成22年度電気関係学会東海支部連合大会  2010.8 

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    Venue:中部大学  

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  • Relationship between alignment errors of optical components and power consumption in optoelectronic devices International conference

    2010.8 

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    Venue:Tokyo, Japan  

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  • 64コンテキストMEMS光再構成型ゲートアレイ

    山地, 渡邊実

    機構デバイス研究会  2010.8 

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    Venue:千歳アルカディアプラザ  

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  • Dynamically reconfigurable vision chip architecture International conference

    2010.8 

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    Venue:Milano, Italy  

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  • 銀塩ホログラムを用いた4コンテキスト・プログラマブル光再構成型ゲートアレイ

    久保田,渡邊

    平成22年度電気関係学会東海支部連合大会  2010.8 

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    Venue:中部大学  

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  • 光再構成型ゲートアレイのレーザアレイ故障の復旧方法

    渡邊貴弘, 渡邊実

    機構デバイス研究会  2010.8 

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    Venue:千歳アルカディアプラザ  

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  • Excellent Fault Tolerance of a MEMS Optically Differential Reconfigurable Gate Array International conference

    2010.8 

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    Venue:Sapporo, Japan  

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  • Influence Analysis of a Holographic Memory Window of a Programmable Optically Reconfigurable Gate Array International conference

    2010.8 

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    Venue:Seattle, USA  

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  • Fiber remote configuration for a dynamic optically reconfigurable gate array International conference

    2010.7 

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    Venue:Sapporo, Japan  

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  • Partial block-by-block reconfiguration for a dynamic optically reconfigurable gate array

    D. Seto, M, Watanabe

    International Conference on engineering of reconfigurable systems and algorithms  2010.7 

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  • Programmable optically reconfigurable gate array using a silver-halide holographic memory International conference

    2010.7 

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    Venue:Sapporo, Japan  

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  • Recovery method for a turn-off failure mode of a laser array on an ORGA International conference

    2010.6 

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    Venue:California, USA  

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  • A four-context optically reconfigurable gate array using a laser array attachment International conference

    2010.6 

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    Venue:Tsukuba, Japan  

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  • Acceleration method of optical reconfigurations using analog configuration contexts International conference

    2010.6 

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    Venue:California, USA  

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  • 明点ビット数の最小化による順序回路の高速構成手法

    森脇,渡邊

    LSIとシステムのワークショップ  2010.5 

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    Venue:北九州国際会議場  

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  • ダイナミック光再構成型ゲートアレイのばらつき補正技術

    青山,渡邊

    LSIとシステムのワークショップ  2010.5 

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    Venue:北九州国際会議場  

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  • A 100-Context Optically Reconfigurable Gate Array

    2010.5 

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    Venue:Paris, France  

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  • Configuration power reduction effect of an ORGA with analog configuration contexts International conference

    2010.4 

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    Venue:Yokohama, Japan  

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  • Power reduction method using negative logic implementation

    R. Moriwaki, M. Watanabe

    IEEE Symposium on Low-Power and High-Speed Chips  2010.4 

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  • 動的再構成を用いたイメージセンサ

    保田,渡邊

    画像工学研究会  2010.3 

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    Venue:東北大学  

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  • 液晶を用いた光再構成型ゲートアレイ用異方性ホログラムメモリの作製

    荻原,越智, 渡邊実, 間渕,小林

    第57回応用物理学関係連合講演会  2010.3 

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    Venue:東海大学湘南キャンパス  

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  • MEMS dynamic optically reconfigurable gate array usable under a space radiation environment International conference

    2010.3 

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    Venue:Bangkok, Thailand  

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  • 偏光依存性ホログラムメモリを用いた光再構成試験

    間渕,越智, 渡邊, 荻原,小林

    第57回応用物理学関係連合講演会  2010.3 

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    Venue:東海大学湘南キャンパス  

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  • ダイナミック光再構成型ゲートアレイのレーザー故障回避

    瀬戸,渡邊

    第57回応用物理学関係連合講演会  2010.3 

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    Venue:東海大学湘南キャンパス  

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  • 差分光再構成手法に対する不良耐性

    森田,渡邊

    画像工学研究会  2010.3 

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    Venue:東北大学  

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  • ダイナミック光再構成ゲートアレイのブロック再構成

    瀬戸,渡邊

    集積回路研究会  2010.1 

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    Venue:東芝本社  

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  • 銀塩ホログラムを用いたプログラマブル光再構成型ゲートアレイ

    久保田,渡邊

    VLSI設計技術研究会  2010.1 

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    Venue:慶応義塾大学  

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  • アナログコンテクストを用いたフォトダイオード特性の補正手法

    青山,渡邊

    VLSI設計技術研究会  2010.1 

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    Venue:慶応義塾大学  

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  • 光ファイバーを用いたリモートダイナミック光再構成型ゲートアレイ

    上野,渡邊

    VLSI設計技術研究会  2010.1 

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    Venue:慶応義塾大学  

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  • A lens-less imaging holographic memory writer system for a programmable optically reconfigurable gate array International conference

    2009.12 

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    Venue:Varanasi, INDIA  

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  • 宇宙放射線に対して高い耐性を持つ光バッファリング手法

    中島,渡邊

    リコンフィギャラブルシステム研究会  2009.12 

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    Venue:高知文化プラザ  

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  • 4コンテキスト・リモート光再構成型ゲートアレイ

    上野,渡邊

    集積回路研究会  2009.12 

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    Venue:静岡大学  

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  • プログラマブル光再構成型ゲートアレイのホログラム窓の影響解析

    久保田,渡邊

    VLSI設計技術研究会  2009.12 

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    Venue:高知文化プラザ  

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  • MEMSを用いた反転・非反転ダイナミック光再構成型ゲートアレイ

    瀬戸,渡邊

    リコンフィギャラブルシステム研究会  2009.12 

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    Venue:高知文化プラザ  

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  • MEMS inversion/non-inversion dynamic optically reconfigurable gate array International conference

    2009.12 

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    Venue:Tokyo,Japan  

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  • 36-context dynamic optically reconfigurable gate array International conference

    2009.12 

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    Venue:Tokyo, Japan  

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  • 100コンテキスト光再構成型ゲートアレイ

    中島,渡邊

    第10回計測自動制御学会システムインテグレーション部門 講演会  2009.12 

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    Venue:芝浦工業大学  

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  • An optical configuration acceleration method using negative logic implementation International conference

    2009.12 

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    Venue:Varanasi, INDIA  

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  • Fault tolerance analysis of MEMS holographic memory for DORGAs International conference

    2009.11 

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    Venue:Nagoya, Japan  

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  • A 36-context optically reconfigurable gate array International conference

    2009.11 

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    Venue:Busan, Korea  

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  • Fiber remote configuration for an optically reconfigurable gate array International conference

    2009.11 

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    Venue:Busan, Korea  

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  • MEMS Optically Differential Reconfigurable Gate Array International conference

    2009.11 

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    Venue:Xi’an, China  

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  • ディジタルミラーデバイスを用いた差分光再構成型ゲートアレイ

    森田,渡邊

    電子情報通信学会技術研究報告(信号処理研究会)  2009.10 

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    Venue:福井県 芦原温泉  

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  • Formation of volume holographic memory using liquid-crystal composites for optically reconfigurable gate array

    2009.10 

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    Venue:Tokyo, Japan  

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  • アナログコンテキストを用いた光再構成の最適化手法

    青山,渡邊

    電子情報通信学会技術研究報告(信号処理研究会)  2009.10 

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    Venue:福井県 芦原温泉  

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  • A 13.75 ns holographic reconfiguration of an optically differential reconfigurable gate array International conference

    2009.9 

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    Venue:Kyoto, Japan  

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  • MEMSダイナミック光再構成型ゲートアレイの不良耐性

    瀬戸,渡邊

    電子情報通信学会技術研究報告(VLSI設計技術研究会)  2009.9 

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    Venue:大阪大学  

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  • 光ファイバを用いたリモート光再構成型ゲートアレイ

    上野,渡邊

    電子情報通信学会技術研究報告(VLSI設計技術研究会)  2009.9 

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    Venue:大阪大学  

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  • レンズ結像系を用いない4コンテキストプログラマブル光再構成型ゲートアレイ用ライター

    久保田,渡邊

    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会)  2009.9 

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  • 負論理回路実装による光再構成の高速化手法

    森脇,渡邊

    電子情報通信学会技術研究報告(VLSI設計技術研究会)  2009.9 

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    Venue:大阪大学  

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  • レンズ結像系を用いないプログラマブル光再構成型ゲートアレイ用ライター

    久保田,渡邊

    宇宙科学技術連合講演会  2009.9 

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    Venue:宇都宮大学  

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  • MEMSを使用した光再構成技術

    森田,渡邊

    宇宙科学技術連合講演会  2009.9 

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    Venue:京都大学  

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  • MEMSを用いたダイナミック光再構成型ゲートアレイ

    瀬戸,渡邊

    電気関係学会東海支部連合大会  2009.9 

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  • 36コンテキスト光再構成形ゲートアレイにおける高速再構成

    中島,渡邊

    電気関係学会東海支部連合大会  2009.9 

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  • 不揮発性液晶ホログラムメモリを用いた光再構成型ゲートアレイの不良耐性

    間渕,宮城, 渡邊,荻原

    宇宙科学技術連合講演会  2009.9 

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    Venue:京都大学  

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  • MEMS Optically Reconfigurable Gate Array International conference

    2009.8 

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    Venue:Prague, Czech Republic  

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  • デジタルミラーデバイスを用いた4コンテキスト光再構成

    森田,渡邊

    電子情報通信学会技術研究報告(光エレクトロニクス研究会)  2009.8 

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    Venue:東北大学  

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  • Fault tolerance of a dynamic optically reconfigurable gate array with a one-time writable volume holographic memory International conference

    2009.8 

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    Venue:Cancun, Mexico  

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  • A multi-context programmable optically reconfigurable gate array without a beam splitter International conference

    2009.8 

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    Venue:Cancun, Mexico  

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  • 36コンテキストダイナミック光再構成形ゲートアレイ

    中島,渡邊

    電子情報通信学会技術研究報告(レーザ・量子エレクトロニクス研究会)  2009.8 

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    Venue:東北大学  

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  • 不揮発性液晶ホログラムメモリを用いたダイナミック光再構成型ゲートアレイの故障耐性

    間渕,宮城, 渡邊,荻原

    電子情報通信学会技術研究報告(回路とシステム研究会)  2009.7 

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    Venue:釧路市生涯学習センター  

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  • Defect tolerance of an optically reconfigurable gate array with a one-time writable volume holographic memory International conference

    2009.7 

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    Venue:San Francisco, USA  

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  • A sixteen-context dynamic optically reconfigurable gate array International conference

    2009.7 

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    Venue:San Francisco, USA  

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  • A multi-context programmable optically reconfigurable gate array International conference

    2009.7 

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    Venue:Las Vegas, USA  

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  • Optically reconfigurable gate array with a one-time writable holographic memory International conference

    2009.7 

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    Venue:Las Vegas, USA,  

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  • Alignment compensation method for an optically reconfigurable gate array International conference

    2009.7 

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  • A sixteen-context optically reconfigurable gate array

    2009.7 

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    Venue:Boston, USA  

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  • Inversion/non-inversion implementation for an 11,424 gate-count dynamic optically reconfigurable gate array VLSI International conference

    2009.7 

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    Venue:Samos, Greece  

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  • デジタルミラーデバイスを用いた光再構成

    森田,渡邊

    電子情報通信学会技術研究報告(回路とシステム研究会)  2009.7 

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    Venue:釧路市生涯学習センター  

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  • A programmable dynamic optically reconfigurable gate array International conference

    2009.6 

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    Venue:Toulouse, France  

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  • A nine-context programmable optically reconfigurable gate array with semiconductor lasers

    2009.5 

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    Venue:Boston, USA  

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  • 光再構成型ゲートアレイの組み立て誤差・総合補正手法

    森田,渡邊

    LSIとシステムのワークショップ  2009.5 

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    Venue:北九州国際会議場  

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  • 斜め入射光源を用いたプログラマブル光再構成型ゲートアレイ

    久保田,渡邊

    LSIとシステムのワークショップ  2009.5 

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    Venue:北九州国際会議場  

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  • Fast reconfiguration experiments of an optically differential reconfigurable gate array with 9 configuration contexts

    2009.5 

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    Venue:Taipei, Taiwan  

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  • 不揮発性液晶ホログラムメモリを用いたダイナミック光再構成型ゲートアレイ

    間渕,宮城, 渡邊,荻原

    LSIとシステムのワークショップ  2009.5 

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    Venue:北九州国際会議場  

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  • Power reduction effect of an inversion/non-inversion dynamic optically reconfigurable gate array International conference

    2009.4 

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    Venue:Yokohama, Japan  

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  • Dynamic optically reconfigurable gate array with high defect tolerance International conference

    2009.4 

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    Venue:Yokohama, Japan  

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  • 11,424ゲートダイナミック光再構成型ゲートアレイへの多数決回路実装

    瀬戸,渡邊

    第56回応用物理学関係連合講演会  2009.3 

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    Venue:筑波大学  

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  • Fast optical reconfigurations of a nine-context DORGA International conference

    2009.3 

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    Venue:Karlsruhe, Germany  

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  • 16コンテキスト光再構成型ゲートアレイ

    中島,渡邊

    電子情報通信学会技術研究報告(CAS)  2009.3 

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    Venue:岐阜長良川温泉国際会議場  

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  • 不揮発性液晶ホログラムメモリを用いた光再構成型ゲートアレイ

    間渕,宮城, 渡邊,荻原

    電子情報通信学会技術研究報告(CAS)  2009.3 

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    Venue:岐阜長良川温泉国際会議場  

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  • プログラマブル・ダイナミック光再構成型ゲートアレイ

    久保田,渡邊

    第56回応用物理学関係連合講演会  2009.3 

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    Venue:筑波大学  

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  • An estimation of an inversion/non-inversion dynamic optically reconfigurable gate array VLSI International conference

    2009.2 

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    Venue:Tokyo, Japan  

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  • Configuration experiments for an optically reconfigurable gate array with a silver-halide holographic memory International conference

    2009.2 

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    Venue:Tokyo, Japan  

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  • A triple-module redundancy for an optically reconfigurable gate array

    2009.2 

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    Venue:Tokyo, Japan  

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  • An 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array with a Photodiode Memory Architecture International conference

    2009.1 

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    Venue:Yokohama, Japan  

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  • 高速動的再構成が可能な光再構成型ゲートアレイ Invited

    渡邊 実

    レーザー学会学術講演会第29回年次大会  2009.1 

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  • An analogue reconfiguration period adjustment technique for optically reconfigurable gate arrays

    2008.12 

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    Venue:Taipei, Taiwan  

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  • An 11,424 gate dynamic optically reconfigurable gate array VLSI International conference

    2008.12 

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    Venue:Taipei, Taiwan  

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  • An Optical Configuration of an 11,424 Gate-count Dynamic Optically Reconfigurable Gate Array using a VCSEL International conference

    2008.12 

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    Venue:Nagoya, Japan  

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  • ダイナミック光再構成型ゲートアレイのゲートアレイ部の性能評価

    瀬戸,渡邊

    電子情報通信学会技術研究報告(ICD)  2008.12 

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    Venue:東工大(大岡山)  

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  • Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI International conference

    2008.12 

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    Venue:Taipei, Taiwan  

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  • 9コンテキスト差分光再構成型ゲートアレイの高速再構成試験

    中島,渡邊

    電子情報通信学会技術研究報告(ICD)  2008.12 

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    Venue:東工大(大岡山)  

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  • Programmable Optically Reconfigurable Gate Array Architecture using a PAL-SLM International conference

    2008.12 

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    Venue:Nagoya, Japan  

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  • 大規模光再構成型ゲートアレイにおけるホログラムメモリの不良耐性

    瀬戸,渡邊

    電子情報通信学会技術研究報告(SDM)  2008.11 

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    Venue:機械振興会館  

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  • 宇宙放射線に対して高い耐性を持つ光再構成型ゲートアレイの高速再構成試験

    中島,渡邊

    第52回宇宙科学技術連合講演会  2008.11 

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    Venue:淡路夢舞台国際会議場  

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  • 完全並列プログラミングが可能なダイナミック光再構成型ゲートアレイ

    瀬戸,渡邊

    第52回宇宙科学技術連合講演会  2008.11 

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    Venue:淡路夢舞台国際会議場  

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  • 光再構成型ゲートアレイのホログラム部の組み立て精度について

    森田,渡邊

    電子情報通信学会技術研究報告(RECONF)  2008.11 

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    Venue:北九州学術研究都市  

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  • Multi-speed configuration for ORGAs International conference

    2008.11 

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    Venue:Hyogo, Japan  

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  • A 9-context Optically Reconfigurable Gate Array

    2008.11 

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    Venue:Busan, Korea  

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  • 反転・非反ダイナミック転光再構成アーキテクチャのエミュレーション試験

    加藤,渡邊

    電子情報通信学会技術研究報告(RECONF)  2008.11 

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    Venue:北九州学術研究都市  

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  • Allowable alignment errors of components in an optically reconfigurable gate array International conference

    2008.11 

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    Venue:Hyogo, Japan  

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  • 13.75ns高速ホログラム光再構成

    中島,渡邊

    電子情報通信学会技術研究報告(SDM)  2008.11 

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    Venue:機械振興会館  

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  • 9 コンテキスト光再構成型ゲートアレイ

    間渕,渡邊

    情報フォトニクス研究グループ研究会  2008.9 

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    Venue:寸又峡公民館  

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  • 再構成時間の最適化が可能なダイナミック光再構成型ゲートアレイ

    間渕,渡邊

    第69回応用物理学会学術講演会  2008.9 

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    Venue:中部大学  

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  • 高速ダイナミック光再構成型ゲートアレイ VLSI

    加藤,渡邊

    電子情報通信学会技術研究報告(VLD)  2008.9 

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    Venue:金沢商工会議所会館  

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  • Analysis of retention time under multi-configuration on a DORGA International conference

    2008.9 

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    Venue:Newport Beach, USA  

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  • 大規模光再構成型ゲートアレイにおける高速再構成試験

    中島,渡邊

    電子情報通信学会技術研究報告  2008.9 

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  • PAL-SLMを用いたプログラマブルなマルチコンテキスト光再構成型ゲートアレイ

    久保田,渡邊

    電子情報通信学会技術研究報告  2008.9 

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    Venue:金沢商工会議所会館  

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  • 光再構成型ゲートアレイにおけるマルチスピード再構成

    中島,渡邊

    第69回応用物理学会学術講演会  2008.9 

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    Venue:中部大学  

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  • 光再構成型ゲートアレイへの多数決回路の実装

    野田,渡邊

    第69回応用物理学会学術講演会  2008.9 

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    Venue:中部大学  

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  • PAL-SLM を用いたプログラマブルな光再構成型ゲートアレイとライター

    久保田,渡邊

    第69回応用物理学会学術講演会  2008.9 

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    Venue:中部大学  

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  • ゼロオーバーヘッド・高速ダイナミック光再構成型ゲートアレイ VLSI

    加藤,渡邊

    第69回応用物理学会学術講演会  2008.9 

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    Venue:中部大学  

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  • 光再構成型ゲートアレイの組み立て精度

    森田,渡邊

    情報フォトニクス研究グループ研究会  2008.9 

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    Venue:寸又峡公民館  

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  • 反転・非反転ダイナミック光再構成アーキテクチャのゼロオーバーヘッド・ノンゼローバーヘッドVLSI の比較評価

    加藤,渡邊

    情報フォトニクス研究グループ研究会  2008.9 

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    Venue:寸又峡公民館  

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  • 大規模ゲート光再構成型ゲートアレイの保持時間の測定

    瀬戸,渡邊

    電子情報通信学会技術研究報告  2008.9 

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    Venue:岡山大学  

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  • Optical configuration using a silver-halide holographic memory including four configuration contexts

    D. Seto, M, Watanabe

    International Conference on Solid State Devices and Materials  2008.9 

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  • 光再構成型ゲートアレイの組み立て許容誤差

    森田,渡邊

    第69回応用物理学会学術講演会  2008.9 

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    Venue:中部大学  

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  • 4コンテキストDORGAにおける高速再構成

    中島,渡邊

    電子情報通信学会技術研究報告  2008.8 

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    Venue:東北大学  

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  • Multi optical configuration using spreading beams International conference

    N. Yamaguchi, M. Watanabe

    IEEE International Midwest Symposium on Circuits & Systems  2008.8 

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  • 大規模ダイナミック光再構成型ゲートアレイVLSIの評価

    瀬戸,渡邊

    電子情報通信学会技術研究報告  2008.8 

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    Venue:東北大学  

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  • A 770ns holographic reconfiguration of a four-contexts DORGA International conference

    2008.7 

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    Venue:Las Vegas, USA  

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  • MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration --- Proposal and a 6502 Perspective --- International conference

    2008.7 

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    Venue:Las Vegas, USA  

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  • A dynamic holographic reconfiguration on a four-context ODRGA International conference

    2008.7 

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    Venue:Leuven, Belgium  

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  • An inversion/non-inversion dynamic optically reconfigurable gate array Invited

    M. Watanabe, M. Nakajima

    World Scientific and Engineering Academy and Society International Conference on CIRCUITS  2008.7 

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  • A double or triple module redundancy model exploiting dynamic reconfigurations International conference

    2008.6 

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    Venue:Noordwijk, Netherlands  

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  • 4コンテキスト光再構成型ゲートアレイによる高速再構成

    中島真央, 渡邊 実

    リコンフィギャラブルシステム研究会  2008.5 

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    Venue:会津大学  

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  • 銀塩ホログラムメモリを用いたマルチコンテキスト・ダイナミック光再構成型ゲートアレイ

    瀬戸大作, 渡邊 実

    リコンフィギャラブルシステム研究会  2008.5 

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    Venue:会津大学  

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  • Defect tolerance of holographic configurations in ORGAs International conference

    2008.4 

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    Venue:Miami, USA  

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  • A dynamic optically reconfigurable gate array with a silver-halide holographic memory International conference

    2008.4 

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    Venue:Montpellier, France  

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  • A 937.5 ns multi-context holographic configuration with a 30.75 us retention time International conference

    2008.4 

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    Venue:Miami, USA  

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  • 2つのVCSELレーザを用いたマルチコンテキスト光再構成型ゲートアレイ

    山口,渡邊

    第55回応用物理学関係連合講演会  2008.3 

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    Venue:日本大学理工学部  

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  • マルチコンテキスト光再構成型ゲートアレイにおける高速再構成

    中島,渡邊

    第55回応用物理学関係連合講演会  2008.3 

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    Venue:日本大学理工学部  

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  • 銀塩ホログラムを使用したダイナミック光再構成型ゲートアレイの保持時間の解析

    瀬戸,渡邊

    第55回応用物理学関係連合講演会  2008.3 

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    Venue:日本大学理工学部  

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  • 光再構成型ゲートアレイの組み立て誤差補正手法

    森田,渡邊

    電子情報通信学会技術研究報告(CAS)  2008.1 

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    Venue:ホテルマリックス(宮崎)  

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  • An optical reconfiguration system with four-contexts

    N. Yamaguchi, M. Watanabe

    International Conference on VLSI Design  2008.1 

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  • 反転・非反転ダイナミック光再構成アーキテクチャの比較評価

    加藤,渡邊

    電子情報通信学会技術研究報告(RECONF)  2008.1 

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    Venue:慶応義塾大学(日吉)  

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  • 4コンテキスト光再構成型ゲートアレイの実証

    間渕,渡邊

    電子情報通信学会技術研究報告(RECONF)  2008.1 

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    Venue:慶応義塾大学(日吉)  

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  • ダイナミック光再構成型ゲートアレイの高速再構成試験

    中島,渡邊

    電子情報通信学会技術研究報告  2008.1 

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  • ダイナミック光再構成アーキテクチュアの連続再構成における保持時間の解析

    瀬戸,渡邊

    電子情報通信学会技術研究報告  2008.1 

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  • An acceleration and optimization method for optical reconfigurations International conference

    2008.1 

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  • 光再構成ゲートアレイのホログラムメモリに対する不良耐性解析

    篠原,渡邊

    電子情報通信学会技術研究報告  2008.1 

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  • 9コンテキスト・プログラマブル光再構成型ゲートアレイとライター

    久保田,渡邊

    電子情報通信学会技術研究報告(RECONF)  2008.1 

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    Venue:慶応義塾大学(日吉)  

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  • 9コンテキスト光再構成ゲートアレイによる高速再構成

    中島,渡邊

    電子情報通信学会技術研究報告(CAS)  2008.1 

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    Venue:ホテルマリックス(宮崎)  

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  • Reconfigurations of a dynamic optically reconfigurable architecture under a constant laser exposure International conference

    2007.12 

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  • DORGA holographic memory architecture

    M. Watanabe, S. Fukagawa, F. Kobayashi

    IEEE International Conference on Microelectronics  2007.12 

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  • Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture International conference

    2007.12 

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  • A 62.5 ns holographic reconfiguration for an optically differential reconfigurable gate array International conference

    2007.12 

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  • 動的再構成のための配置配線の一手法

    日高, 小林,渡邊

    電子情報通信学会技術研究報告  2007.11 

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  • 照射時間を一定としたダイナミック光再構成型ゲートアレイの保持時間の解析

    瀬戸,渡邊

    電子情報通信学会技術研究報告  2007.10 

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  • ダイナミック光再構成アーキテクチュアの再構成時間と保持時間の測定

    瀬戸,渡邊

    情報通信学会技術研究報告  2007.10 

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  • マルチコンテキスト光再構成型ゲートアレイによる高速動的光再構成

    中島,渡邊

    電子情報通信学会技術研究報告  2007.10 

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  • コンテキスト重ね合わせによる高速光再構成

    山口,渡邊

    電子情報通信学会技術研究報告  2007.10 

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  • A 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI International conference

    2007.9 

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  • ODRGA-VLSIのゲートアレイ動作時における高速再構成

    中島,渡邊

    電子情報通信学会技術研究報告  2007.9 

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  • マルチコンテキスト光再構成型ゲートアレイ

    山口,渡邊

    電子情報通信学会技術研究報告  2007.9 

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  • Scaling Rule of Optically Differential Reconfigurable Gate Array VLSIs International conference

    2007.8 

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  • 272 gate count optically differential reconfigurable gate array VLSI International conference

    2007.6 

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  • Optimization of reconfiguration speed control bits for an Optically Reconfigurable Gate Array International conference

    2007.6 

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  • Holographic memory reconfigurable VLSI International conference

    2007.5 

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  • Power Consumption Reduction Method of Dynamic Optically Reconfigurable Gate Array VLSIs International conference

    2007.4 

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  • A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays International conference

    2007.3 

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  • Superimposing technique of reconfiguration contexts International conference

    2007.2 

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  • Superimposing technique of reconfiguration contexts for increasing reconfiguration speed International conference

    2007.1 

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    Venue:Hawaii, USA  

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  • A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI International conference

    2007.1 

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    Venue:Yokohama, Japan  

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  • Optically Reconfigurable Gate Arrays vs.ASICs

    2006.12 

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    Venue:Waterfront, Singapore  

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  • Over-Sampling PLL for Low-Jitter and Responsive Clock Synchronization International conference

    2006.10 

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    Venue:Bangkok, Thailand  

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  • A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays International conference

    2006.8 

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    Venue:San Juan, Puerto Rico  

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  • A reconfiguration speed adjustment technique for ORGAs with a holographic memory

    2006.8 

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    Venue:Madrid, Spain  

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  • A logic synthesis and place and route environment for ORGAs

    2006.6 

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    Venue:Las Vegas, USA  

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  • Shield effect analysis for a gate array on an Optically Reconfigurable Gate Array International conference

    2006.6 

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    Venue:Las Vegas, USA  

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  • Differential Reconfiguration Architecture suitable for a Holographic Memory International conference

    2006.6 

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    Venue:Las Vegas, USA  

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  • Hybrid Sample Rate Converter with 110dB SNR and 1/10 Less Logic Gates International conference

    2006.5 

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    Venue:East Lansing, USA  

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  • An optically differential reconfigurable gate array with a holographic memory International conference

    2006.4 

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    Venue:Rhodes Island, Greece  

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  • Power consumption advantage of a dynamic optically reconfigurable gate array

    2006.4 

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    Venue:Rhodes Island, Greece  

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  • A 1,632 gate-count zero-overhead Dynamic Optically Reconfigurable Gate Array VLSI International conference

    2006.3 

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    Venue:Delft, Netherland  

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  • A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35um CMOS Technology International conference

    2006.1 

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    Venue:Yokohama, Japan  

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  • 光再構成型ゲートアレイの製造不良耐性

    日高, 渡邊実, 小林

    電子情報通信学会技術研究報告  2006 

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  • High manufacturing defect- tolerance optically programmable architecture Invited

    M. Watanabe, F. Kobayashi

    World Scientific and Engineering Academy and Society International Conference on circuits, systems, electronics, control & signal processing  2006 

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  • 液晶ホログラムを用いた光再構成型ゲートアレイ

    中田, 渡邊実, 小林

    電子情報通信学会技術研究報告  2006 

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  • 差分光再構成型ゲートアレイの再構成時間・消費電力の最適化手法

    日高, 渡邊実, 小林

    電子情報通信学会技術研究報告  2006 

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  • ダイナミック光再構成型ゲートアレイ

    深川, 渡邊実, 小林

    第11回計測自動制御学会九州支部講義会予稿  2006 

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  • 位相補間によるPLLの特性改善 ~ 位相補間回路の最適化 ~

    井上,小林, 渡邊実

    電子情報通信学会技術研究報告  2006 

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  • 位相補間によるPLLの特性改善:ジッタ低減のための高精度補間

    井上,小林, 渡邊実

    第11回計測自動制御学会九州支部講義会予稿  2006 

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  • ゼロオーバーヘッド・ダイナミック光再構成型ゲートアレイ

    後藤, 渡邊実, 小林

    第11回計測自動制御学会九州支部講義会予稿  2006 

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  • デジタルオーディオの統合開発環境 -RHDLによるFPGA開発-

    山口,小林, 渡邊実

    第11回計測自動制御学会九州支部講義会予稿  2006 

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  • 動的再構成システム開発環境

    櫻井,小林, 渡邊実

    第11回計測自動制御学会九州支部講義会予稿  2006 

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  • A zero-overhead Dynamic Optically Reconfigurable Gate Array

    2005.12 

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    Venue:Singapore  

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  • Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers International conference

    2005.12 

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    Venue:Singapore  

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  • A 51,272-gate-count Dynamic Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology International conference

    2005.9 

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    Venue:Kobe, Japan  

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  • Fourier/Filter Hybrid Sampling Rate Converter International conference

    2005.8 

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    Venue:Okayama, Japan  

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  • Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors

    M. Watanabe, F. Kobayashi

    International Conference on engineering of reconfigurable systems and algorithms  2005.5 

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  • A 16,000-gate-count Optically Reconfigurable Gate Array in a standard 0.35um CMOS Technology International conference

    2005.5 

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    Venue:Kobe, Japan  

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  • Optically Differential Reconfigurable Gate Array using an optical system with VCSEL International conference

    2005.5 

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    Venue:Tampa, USA  

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  • An improved dynamic optically reconfigurable gate array International conference

    2005.5 

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    Venue:Tampa, USA  

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  • An Optically Differential Reconfigurable Gate Array VLSI chip with a dynamic reconfiguration circuit International conference

    2005.4 

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    Venue:Denver, USA  

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  • A dynamic optically reconfigurable gate array using dynamic method International conference

    2005.2 

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    Venue:Algarve, Portugal  

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  • 光再構成型ゲートアレイの検査手法

    松尾, 渡邊実, 小林

    第24回計測自動制御学会九州支部学術講演会予稿  2005 

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  • 272ゲート規模ODRGA-VLSIの実装評価

    志岐, 渡邊実, 小林

    電子情報通信学会技術研究報告  2005 

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  • 複数のVCSELを用いたODRGAの再構成速度改善

    宮野, 渡邊実, 小林

    電子情報通信学会技術研究報告  2005 

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  • PLLジッタ低減のためのオーバ・サンプリング位相比較器

    井上,小林, 渡邊実

    電子情報通信学会・2005ソサイエティ大会  2005 

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  • 位相補間によるPLLの特性改善

    井上,小林, 渡邊実

    第24回計測自動制御学会九州支部学術講演会予稿  2005 

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  • 光再構成ゲートアレイのプログラム支援環境

    櫻井,小林, 渡邊実

    第24回計測自動制御学会九州支部学術講演会予稿  2005 

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  • 動的再構成によるシステム実現

    渡邊実, 小林

    第6回システムインテグレーション部門講演会  2005 

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  • 光再構成型ゲートアレイの再構成回路の評価

    藤目, 渡邊実, 小林

    第24回計測自動制御学会九州支部学術講演会予稿  2005 

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  • 0.18umプロセスによる差分光再構成型ゲートアレイVLSI

    志岐, 渡邊実, 小林

    第24回計測自動制御学会九州支部学術講演会予稿  2005 

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  • フィルタ/Fourierハイブリッド型サンプルレートコンバータ

    福井,小林, 渡邊実

    第24回計測自動制御学会九州支部学術講演会予稿  2005 

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  • An Optically Differential Reconfigurable Gate Array using a 0.18 um CMOS process International conference

    2004.9 

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    Venue:Santa Clara, USA  

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  • A high-density optically reconfigurable gate array using dynamic method International conference

    2004.8 

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    Venue:Antwerp, Belgium  

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  • Sampling rate conversion by Fourier interpolation International conference

    2004.8 

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    Venue:Sapporo, Japan  

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  • An optical reconfiguration circuit for optically reconfigurable Gate Arrays International conference

    2004.7 

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    Venue:Hiroshima, Japan  

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  • Testing method for optical connections using gate array structure in ORGAs International conference

    2004.6 

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    Venue:Las Vegas, USA  

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  • An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation International conference

    2004.1 

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    Venue:Mumbai, India  

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  • 差分光再構成型ゲートアレイVLSI

    志岐, 渡邊実, 小林

    電子情報通信学会技術研究報告  2004 

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  • 差分型光再構成ゲートアレイの領域分割照射

    宮野, 渡邊実, 小林

    電子情報通信学会技術研究報告  2004 

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  • 0.18umプロセスによる差分光再構成型ゲートアレイ

    渡邊実, 小林

    電子情報通信学会技術研究報告  2004 

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  • 差分型光再構成ゲートアレイの照射領域と再構成速度の評価

    宮野, 渡邊実, 小林

    第8回システムLSIワークショップ  2004 

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  • VCSELを用いた差分型光再構成ゲートアレイ

    宮野, 渡邊実, 小林

    電子情報通信学会・集積光デバイス技術時限研究専門委員会  2004 

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  • ダイナミック差分光再構成型ゲートアレイ

    植田, 渡邊実, 小林

    第23回計測自動制御学会九州支部学術講演会  2004 

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  • 光再構成型ゲートアレイの検査手法

    松尾, 渡邊実, 小林

    第23回計測自動制御学会九州支部学術講演会予稿  2004 

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  • パルスレーザを用いた差分型再構成ゲートアレイ

    宮野, 渡邊実, 小林

    電子情報通信学会技術研究報告  2004 

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  • 光再構成型ゲートアレイの再構成回路の評価

    藤目, 渡邊実, 小林

    電子情報通信学会技術研究報告  2004 

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  • 差分型光再構成ゲートアレイの光再構成タイミング解析

    宮野, 渡邊実, 小林

    第23回計測自動制御学会九州支部学術講演会予稿  2004 

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  • 光再構成型ゲートアレイのプログラミング環境

    山角,小林, 渡邊実

    第23回計測自動制御学会九州支部学術講演会予稿  2004 

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  • フーリエ補間によるサンプリング・レート変換

    井上,小林, 渡邊実

    第23回計測自動制御学会九州支部学術講演会予稿  2004 

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  • Design of an Optically Differential Reconfigurable Gate Array VLSI chip with optically and electrically controlled logic blocks International conference

    2003.9 

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    Venue:Portland, USA  

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  • A finite physical quantity neural network VLSI with a learning capability International conference

    2003.8 

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    Venue:Fukui , Japan  

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  • Configuration for an Optically Differential Reconfigurable Gate Array International conference

    2003.8 

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    Venue:Fukui , Japan  

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  • An Optically Differential Reconfigurable Gate Array with a dynamic reconfiguration circuit

    2003.4 

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    Venue:Nice, France  

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  • 差分光再構成型ゲートアレイに使用するダイナミック再構成回路

    藤目, 渡邊実, 小林

    電子情報通信学会技術研究報告  2003 

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  • 差分型光再構成ゲートアレイの連続再構成

    宮野, 渡邊実, 小林

    第22回計測自動制御学会九州支部学術講演会予稿  2003 

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  • 差分型光再構成ゲートアレイの回路実装評価

    宮野, 渡邊実, 小林

    第7回システムLSIワークショップ  2003 

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  • 差分型光再構成ゲートアレイの開発支援システム

    中村, 小林, 渡邊実

    第22回計測自動制御学会九州支部学術講演会予稿  2003 

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  • 差分型光再構成ゲートアレイVLSI部の遅延シミュレーション

    志岐, 渡邊実, 小林

    第22回計測自動制御学会九州支部学術講演会予稿  2003 

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  • An optically differential reconfigurable gate array and its power consumption estimation International conference

    2002.12 

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    Venue:Hong Kong  

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  • A Compressed Implementation of Neural Network with Finite Physical Quantities on FPGAs International conference

    2002.8 

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    Venue:Osaka, Japan  

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  • A Neural Network Model using Finite Physical Quantities and its Realization on LSIs International conference

    2002.8 

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    Venue:Osaka, Japan  

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  • Motion Image Compression Circuit using the Silicon Retina as Active Sensor International conference

    2002.8 

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    Venue:Osaka, Japan  

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  • 有限な物理量を用いたニューラルネットワークモデルのLSI実装

    渡邊実, 小林

    第21回計測自動制御学会九州支部学術講演会予稿  2002 

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  • 有限な物理量を用いたニューラルネットワーク

    渡邊実, 小林

    電子情報通信学会技術研究報告  2002 

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  • 時間領域におけるサンプリングレート変換

    三浦, 小林, 渡邊実

    第21回計測自動制御学会九州支部・学術講演会予稿集  2002 

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  • 有限な物理量を用いたニューラルネットワークモデルのVLSI実装

    渡邊実, 小林

    第6回システムLSIワークショップ  2002 

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  • An optical energy neural networkwith self-organizing capability International conference

    2001.7 

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    Venue:Tokushima, Japan  

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  • FPGAを利用したニューラルネットワークのハードウエア実現

    外枦保, 渡邊実, 小林

    第40回計測自動制御学会予稿集  2001 

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  • 新型エネルギーニューラルネットワークモデルのハードウエア実現

    渡邊実, 外枦保, 小林

    第40回計測自動制御学会予稿集  2001 

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  • ニューラルネットワークの回路実現 :再構成による可変パラメータアーキテクチャー

    外枦保, 渡邊実, 小林

    第5回システムLSIワークショップ  2001 

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  • 光再構成型ゲートアレイ

    松本, 渡邊実, 小林

    第5回システムLSIワークショップ  2001 

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  • 知能化工作機械のためのセンサー内蔵型計測工具

    千, 小林, 渡邊実

    第20回計測自動制御学会九州支部学術講演会予稿集  2001 

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  • シリコン網膜アクティブセンサによる動画像圧縮回路

    尼崎, 小林, 渡邊実, 八木

    第20回計測自動制御学会九州支部学術講演会予稿集  2001 

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  • エネルギーニューラルネットワークモデルを用いた負ニューロン生成方法

    渡邊実, 小林

    第20回計測自動制御学会九州支部学術講演会予稿集  2001 

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  • SIMD型アーキテクチュアにおける規則的不均一演算実装の手法

    松永, 小林, 渡邊実, 石川, 廣津

    第40回計測自動制御学会予稿集  2001 

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  • 光再構成型ゲートアレイとその応用

    緒方, 渡邊実, 小林

    第40回計測自動制御学会予稿集  2001 

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  • アナログビジョンチップのための適応型前処理回路

    大都, 小林, 渡邊実, 八木

    第19回計測自動制御学会九州支部学術講演会予稿集  2000 

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  • 多層エネルギー制限型ニューラルネットワークシステム

    渡邊実, 小林

    第19回計測自動制御学会九州支部学術講演会予稿集  2000 

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  • ニューラルネットワークの論理圧縮手法とそのLSI化

    渡邊実, 小林

    第39回計測自動制御学会学術講演会予稿集  2000 

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  • 光再構成型ゲートアレイと応用

    緒方, 渡邊実, 小林

    第19回計測自動制御学会九州支部学術講演会予稿集  2000 

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  • デジタルビジョンチップによる並列特徴抽出

    松永, 小林, 渡邊実, 廣津

    第19回計測自動制御学会九州支部学術講演会予稿集  2000 

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  • 2値マトリックスを持つ光アソシアトロンの階層化

    渡邊実, 大坪

    第41回応用物理学会予稿集  1994 

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  • 光RAMとLCTVを用いた光アソシアトロンの学習想起システムの検討

    渡邊実, 大坪

    第40回応用物理学会予稿集  1993 

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  • FLCとLCTVを用いた光アソシアトロンの学習

    渡邊実, 大坪, 竹森

    第40回応用物理学会予稿集  1993 

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  • 微小レンズアレイとLCTVを用いた光アソシアトロン

    渡邊実, 荻原, 大坪

    第39回応用物理学会予稿集  1992 

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▼display all

Awards

  • Best Paper Award

    2024.8   International Electronics Symposium (IES), IEEE  

    Minoru Watanabe

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  • 社会貢献賞

    2023.3   岡山大学  

    渡邊実, 渡邊誠也

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  • 学生奨励賞

    2023.3   情報処理学会第85回全国大会  

    辻野 将

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  • 教育功労賞

    2022.3   電子情報通信学会   FPGA自動運転競技大会によるディジタルシステム教育の普及

    渡邊実

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  • Best Paper Award

    2022.1   IEEE Annual Computing and Communication Workshop and Conference (IEEE)  

    A. Ushiroyama

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  • Best Paper Award

    2022.1   IEEE Annual Computing and Communication Workshop and Conference (IEEE)  

    M. Watanabe

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  • 優秀プレゼンテーション賞

    2021.12   パルテノン研究会   FSLによる3値化CNNのFPGA実装

    尾崎洸人

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  • 学生研究奨励賞

    2019.6   社団法人電子情報通信学会東海支部  

    髙木雄介

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  • VDEC デザインアワード 優秀賞

    2018.9   東京大学 大規模集積システム設計教育センター   耐放射線FPGA

    藤森卓巳

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  • 学生研究奨励賞

    2018.6   社団法人電子情報通信学会東海支部  

    榛葉大樹

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  • First Place in the FPGA Design Competition

    2017.7   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, Y. Ito, R. Terada, S. Fujisaki, T. Hatamochi, H. Shinba, M. Watanabe

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  • 学生研究奨励賞

    2017.6   社団法人電子情報通信学会東海支部  

    伊藤芳純

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  • Best Paper Award

    2017.1   IEEE Annual Computing and Communication Workshop and Conference  

    Minoru Watanabe

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  • First Place of FPGA Design Competition

    2016.12   International Conference on Field-Programmable Technology  

    T. Fujimori, Y. Ito, R. Terada, S. Fujisaki, T. Hatamochi, H. Shinba, M. Watanabe

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  • エンベデッド部門 優勝

    2016.9   第7回 相磯秀夫杯 デザインコンテスト(FIT2016 第15回情報科学技術フォーラム イベント企画)  

    藤森卓巳, 伊藤芳純, 渡邊実

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  • 一般部門 優勝

    2016.9   第7回 相磯秀夫杯 デザインコンテスト(FIT2016 第15回情報科学技術フォーラム イベント企画)  

    藤森卓巳, 伊藤芳純, 渡邊実

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  • First Place of the Limited Category in the FPGA Design Competition

    2016.7   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, Y. Ito, T. Akabe, M. Watanabe

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  • Excellent Oral Presentation Award

    2016.7   International Conference on Mechanical and Aerospace Engineering (IEEE)  

    Minoru Watanabe

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  • First Place of the Unlimited Category in the FPGA Design Competition

    2016.7   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, Y. Ito, T. Akabe, M. Watanabe

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  • 学生研究奨励賞

    2016.6   社団法人電子情報通信学会東海支部  

    赤部知也

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  • First Place in FPGA Design Competition 2015

    2015.12   International Conference on Field-Programmable Technology  

    T. Fujimori, T. Akabe, Y. Ito, K. Akagi, S. Furukawa, A. Tanibata, M. Watanabe

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  • Best Student Paper Award

    2015.12   IEEE International Conference on Aerospace Electronics and Remote Sensing Technology  

    Yoshizumi Ito

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  • 一般部門 優勝

    2015.9   第6回 相磯秀夫杯 デザインコンテスト(FIT2015 第14回情報科学技術フォーラム イベント企画)  

    藤森卓巳, 赤部知也, 伊藤芳純, 瀬尾真人, 赤木昂太, 古川晋也, 渡邊実

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  • エンベデッド部門 優勝

    2015.9   第6回 相磯秀夫杯 デザインコンテスト (FIT2015 第14回情報科学技術フォーラム イベント企画)  

    藤森卓巳, 赤部知也, 伊藤芳純, 瀬尾真人, 赤木昂太, 古川晋也, 渡邊実

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  • First Place in The MathWorks Blokus Duo Design Contest

    2015.6   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, M. Seo, K. Akagi, S. Furukawa, H. Ito, M. Watanabe

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  • 学生研究奨励賞

    2015.6   社団法人電子情報通信学会東海支部  

    瀬尾真人

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  • Second Prize in FPGA Design Contest 2014

    2014.12   IEEE International Conference on Field-Programmable Technology  

    T. Mabuchi, T. Watanabe, R. Moriwaki, Y. Aoyama, A. Gundjalam, Y. Yamaji, H. Nakada, M Watanabe

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  • Third Prize in FPGA Design Contest 2014

    2014.12   International Conference on Field-Programmable Technology  

    T. Fujimori, R. Moriwaki, M. Seo, K. Akagi, H. Ito, T. Kubota, S. Furukawa, M. Watanabe

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  • 学生研究奨励賞

    2014.6   社団法人電子情報通信学会東海支部  

    藤森 卓巳

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  • Champion of the Regulation League in FPGA Design Contest 2014 AISO CUP

    2014.6   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, M. Seo, K. Akagi, R. Moriwaki, T. Yoza, Y. Torigai, M. Watanabe

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  • Winner of the Open League in FPGA Design Contest 2014 AISO CUP

    2014.6   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, M. Seo, K. Akagi, R. Moriwaki, T. Yoza, Y. Torigai, M. Watanabe

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  • HDL Champion of the Regulation League in FPGA Design Contest 2014 AISO CUP

    2014.6   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    T. Fujimori, M. Seo, K. Akagi, R. Moriwaki, T. Yoza, Y. Torigai, M. Watanabe

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  • Best Student Paper Award

    2014.5   International Conference on Space Optical Systems and Applications  

    M. Seo

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  • Best Paper Award

    2014.4   International Workshop on Applied Reconfigurable Computing  

    T. Yoza, M. Watanabe

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  • Presentation Master Award

    2014.3   International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems  

    K. Akagi, M. Watanabe

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  • 優秀卒業研究発表賞

    2014.3   電子情報通信学会 東海支部 卒業研究発表会  

    瀬尾真人

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  • 卓越研究者

    2014.1   静岡大学  

    Watanabe Minoru

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  • First Place in FPGA Design Contest 2013 AISO CUP HDL

    2013.12   IEEE International Conference on Field-Programmable Technology  

    T. Yoza, R. Moriwaki, Y. Torigai, Y. Kamikubo, T. Kubota, T. Watanabe, T. Fujimori, H. Ito, M. Seo, K. Akagi, Y. Yamaji, M. Watanabe

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  • First Place in ICFPT Design Competition 2013

    2013.12   IEEE International Conference on Field-Programmable Technology  

    T. Yoza, R. Moriwaki, Y. Torigai, Y. Kamikubo, T. Kubota, T. Watanabe, T. Fujimori, H. Ito, M. Seo, K. Akagi, Y. Yamaji, M. Watanabe

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  • 優勝(第3回相磯秀夫杯FPGAデザインコンテスト)

    2013.9   電子情報通信学会・リコンフィギャラブルシステム研究会  

    森脇烈, 余座貴志, 渡邊貴弘, 鳥飼勇希, 上窪勇貴, 山地勇一郎, 窪田貴之, 伊藤宏幸, 渡邊実

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  • Best Poster Award

    2013.6   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    M. Watanabe

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  • 学生研究奨励賞

    2013.6   社団法人電子情報通信学会東海支部  

    余座貴志

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  • 優秀ポスター賞

    2013.3   電子情報通信学会・総合大会「ISS特別企画・学生ポスターセッション」  

    山地勇一郎

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  • First Place in ICFPT Design Competition

    2012.12   IEEE International Conference on Field-Programmable Technology  

    R. Moriwaki, T. Yoza, Y. Kamikubo, Y. Torigai, A. Tanikawa, T. Kubota, H. Ito, Y. Shirahashi, M. Watanabe

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  • First Place in FPGA Design Contest

    2012.6   International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies  

    R. Moriwaki, T. Yoza, T. Watanabe, Y. Kamikubo, Y. Torigai, Y. Shirahashi, H. Ito, T. Kubota, A. Tanikawa, Y. Yamaji, Y. Aoyama, M. Seo, M. Watanabe

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  • 学生研究奨励賞

    2012.6   社団法人電子情報通信学会東海支部  

    山地勇一郎

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  • 学生奨励賞

    2012.3   情報処理学会・全国大会  

    渡辺貴弘

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  • テレコムシステム技術学生賞

    2012.3   財団法人 電気通信普及財団  

    久保田 慎也

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  • 社会人基礎力準大賞 社会人基礎力育成グランプリ2012決勝大会

    2012.2   日本経済新聞社,経済産業省  

    上野 由美子, 渡辺 貴弘, 仁平優基, 森脇烈, 山地勇一郎, 上窪勇貴, 鳥飼勇希, 余座貴志, 青山裕司, 渡邊 実

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  • First Place in ICFPT Design Competition 2011

    2011.12   IEEE International Conference on Field-Programmable Technology  

    T. Watanabe, R. Moriwaki, Y. Yamaji, Y. Kamikubo, Y. Torigai, Y. Nihira, T. Yoza, Y. Ueno, Y. Aoyama, M. Watanabe

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  • 優秀賞 社会人基礎力育成グランプリ・関東地区大会

    2011.11   日本経済新聞社(経済産業省)  

    上野 由美子, 渡辺 貴弘, 仁平優基, 森脇烈, 山地勇一郎, 上窪勇貴, 鳥飼勇希, 余座貴志, 青山裕司, 渡邊 実

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  • デザインガイヤポスター賞

    2011.11   デザインガイア(電子情報通信学会・情報処理学会)  

    余座 貴志

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  • 優勝 第1回相磯秀夫杯FPGAデザインコンテスト

    2011.11   電子情報通信学会・リコンフィギャラブルシステム研究会  

    渡辺貴弘, 森脇烈, 山地勇一郎, 上窪勇貴, 鳥飼勇希, 仁平優基, 余座貴志, 上野由美子, 青山裕司, 渡邊実

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  • 国際会議研究発表者賞

    2011.10   電子情報通信学会・東海支部  

    森脇 烈

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  • SLDM研究会優秀発表学生賞

    2011.8   社団法人情報処理学会システムLSI設計技術研究会  

    森田 裕宣

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  • 学生研究奨励賞

    2011.6   社団法人電子情報通信学会東海支部  

    森脇 烈

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  • 優秀卒業研究発表賞

    2011.3   社団法人 電子情報通信学会東海支部  

    渡邊 貴弘

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  • 電気学会東海支部長賞

    2011.3   社団法人 電気学会東海支部  

    渡邊 貴弘

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  • テレコムシステム技術学生賞

    2011.3   財団法人 電気通信普及財団  

    間渕 隆之

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  • 奨励賞

    2011.1   計測自動制御学会 中部支部  

    間渕 隆之

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  • 連合大会奨励賞

    2011.1   電気関係学会東海支部連合大会  

    間渕 隆之

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  • 優秀学生顕彰 優秀賞

    2010.12   日本学生支援機構  

    渡邊 貴弘

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  • 優秀賞

    2010.12   第8回 情報学ワークショップ(WiNF 2010)   ホログラム閾値可変によるMEMSダイナミック光再構成型ゲートアレイの動作効率改善法

    森田 裕宣, 渡邊実

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  • SLDM研究会優秀発表学生賞

    2010.9   社団法人情報処理学会システムLSI設計技術研究会  

    久保田 慎也

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  • Best Paper Award

    2010.6   NASA/ESA Conference on Adaptive Hardware and Systems   Recovery method for a turn-off failure mode of a laser array on an ORGA

    D. Seto, M. Watanabe

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  • 学生研究奨励賞

    2010.6   社団法人電子情報通信学会東海支部  

    森田 裕宣

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  • 学生論文奨励賞

    2010.5   情報処理学会東海支部  

    瀬戸 大作

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  • IEEE学生奨励賞

    2010.1   電気関係学会東海支部連合大会  

    中島 真央

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  • 連合大会奨励賞

    2010.1   電気関係学会東海支部連合大会  

    瀬戸 大作

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  • 奨励賞

    2010.1   計測自動制御学会 中部支部  

    中島 真央

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  • デザインガイアポスタ賞

    2009.12   デザインガイア  

    瀬戸 大作

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  • Best Poster

    2009.11   IEEE International Symposium on Micro-NanoMechatronics and Human Science   Fault tolerance analysis of MEMS holographic memory for DORGAs

    D. Seto, M. Watanabe

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  • 学生研究奨励賞

    2009.6   社団法人電子情報通信学会東海支部  

    中島 真央

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  • IEEE Nagoya Section Excellent Student Award

    2009.3   IEEE Nagoya Section  

    S.Kato

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  • 最優秀卒業研究発表賞

    2009.3   社団法人電子情報通信学会東海支部  

    加藤 進一

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  • Best System Integration Award

    2008.12   IEEE International Symposium on System Integration   Optically Reconfigurable Gate Array

    M. Watanabe, D. Seto, S. Kubota

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  • 第133回SLDM研究会優秀発表学生賞

    2008.8   社団法人情報処理学会システムLSI設計技術研究会  

    瀬戸 大作

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  • 学生研究奨励賞

    2008.6   社団法人電子情報通信学会東海支部  

    瀬戸 大作

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  • IEEE Nagoya Section Excellent Student Award

    2008.3   IEEE Nagoya Section  

    D. Seto

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  • 計測自動制御学会九州支部奨励賞

    2006   計測自動制御学会   ダイナミック光再構成型ゲートアレイ

    深川, 渡邊,小林

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  • 2005ベストセッション講演賞

    2005.12   システムインテグレーション,計測自動制御学会   動的再構成によるシステムの実現

    Minoru Watanabe, Fuminori Kobayashi

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  • 計測自動制御学会九州支部奨励賞

    2005   第24回計測自動制御学会九州支部学術講演会   位相補間によるPLLの特性改善

    井上, 小林,渡邊

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  • 計測自動制御学会九州支部奨励賞

    2005   計測自動制御学会九州支部学術講演会   0.18umプロセスによる差分光再構成型ゲートアレイVLSI

    志岐, 渡邊,小林

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  • Finalist Commendation, The Takeda Techno-Entrepreneurship Award

    2001.12   Takeda Foundation   Development of an optically reconfigurable gate array and implementation of a reconfigurable processor

    M. Watanabe, F. Kobayashi, J. Ohtsubo, T. Otsuji

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Research Projects

  • 高放射線耐性を有する無線データ伝送用チップセットの要素開発(ベースバンド回路開発)

    2024.09 - 2027.03

    英知を結集した原子力科学技術・人材育成推進事業 課題解決型廃炉研究プログラム(1億2000万円) 

    宮原 正也, 渡邊 実, 芝崎 友則

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    Authorship:Coinvestigator(s) 

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  • 耐放射線集積回路における吸収線量に応じたクロックスキュー最適化法

    Grant number:24H00693  2024.04 - 2027.03

    日本学術振興会  科学研究費助成事業  基盤研究(A)

    渡邊 実

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    Authorship:Principal investigator 

    Grant amount:\47190000 ( Direct expense: \36300000 、 Indirect expense:\10890000 )

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  • VLSIの高エネルギー中性子への耐用評価

    Grant number:NIFS22KIIA002  2024.04 - 2025.03

    核融合科学研究所  2024年度一般共同研究 

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  • Development of hardware design system for high-speed dynamically reconfigurable devices

    Grant number:23K11032  2023.04 - 2026.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (C)

    渡邊 誠也, 渡邊 実

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    Grant amount:\4680000 ( Direct expense: \3600000 、 Indirect expense:\1080000 )

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  • 耐放射線プロセッサを用いた組み込みシステムの開発

    2022.11 - 2025.03

    日本原子力研究開発機構  英知を結集した原子力科学技術・人材育成推進事業 国際協力型廃炉研究プログラム(日英原子力共同研究)6000万円(予定) 

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  • -

    Grant number:22K18415  2022.06 - 2025.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Research (Pioneering)  Grant-in-Aid for Challenging Research (Pioneering)

    渡邊 実

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    Grant amount:\25870000 ( Direct expense: \19900000 、 Indirect expense:\5970000 )

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  • VLSIの高エネルギー中性子への耐用評価

    2022.04 - 2023.03

    核融合科学研究所  一般共同研究 

    渡邊 実

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  • Multi-context scrubbing for radiation-hardened optoelectronic devices with 1 Grad TID tolerance

    Grant number:21H03407  2021.04 - 2024.03

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\17030000 ( Direct expense: \13100000 、 Indirect expense:\3930000 )

    光再構成を活用してゲートアレイの故障個所を特定する機能の研究を実施した。故障個所を特定する機能は最後まで壊れることが許されないので冗長化実装を研究した。冗長化については3重化実装と、5重回路実装について検討をした。多数決を行うセルは3重化実装も、5重化実装も両セルともカスタム設計し、最適化実装を行った。そして、これらのセルを利用して故障個所を特定する機能を実装した。3重回路実装に比べて、5重回路実装ではより強い耐性を実現することができるが、5重回路実装の専有面積が大きくなりすぎることから、最終的には故障個所を特定する機能に対しては3重回路実装を適用することにした。そして、故障個所を特定する機能を実装した耐放射線光再構成型ゲートアレイVLSIの設計を完了した。また、マルチコンテキストスクラビング向けの光学系テストベンチの設計と試作を完了させた。ホログラムメモリの計算に必要となるソフトウエアの設計を終え、ホログラムメモリの試作も実施し、マルチコンテキストスクラビング向けのホログラムメモリの製作が正しく行えることまで確認を終えた。今年度のマルチコンテキストスクラビングの実装評価は設計した光再構成型ゲートアレイをベースにシミュレーションにより実施した。恒久故障を疑似的にゲートアレイ上に起こし、それでも順序回路を含むマルチコンテキストスクラビングが正常に動作することを確認した。次年度以降は光再構成型ゲートアレイVLSIを試作し、実試験にて評価を進めていく予定である。

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  • 核融合炉プラズマ診断用VLSIの高エネルギー中性子への耐用評価

    Grant number:NIFS21KLPA002  2021.04 - 2022.03

    核融合科学研究所  一般共同研究 

    渡邊 実

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    Authorship:Principal investigator 

    Grant amount:\130000 ( Direct expense: \130000 )

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  • 再臨界前の中性子線増に即応可能な耐放射線FPGAシステムの開発 International coauthorship

    2019.11 - 2021.03

    日本原子力研究開発機構  英知を結集した原子力科学技術・人材育成推進事業 国際協力型廃炉研究プログラム(日英原子力共同研究) (2000万円/2019年度、2000万円/2020年度、2000万円/2021年度) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\60000000 ( Direct expense: \46153846 、 Indirect expense:\13846153 )

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  • 耐放射線動的再構成型プロセッサの研究開発

    2019.05 - 2021.03

    中部電力 原子力安全技術研究所  原子力に係る公募研究 (1100万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\1100000 ( Direct expense: \10000000 、 Indirect expense:\1000000 )

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  • 耐放射線光電子融合デバイスへのマルチコンテキストスクラビングの実装

    2019.04 - 2021.03

    総務省  戦略的情報通信研究開発推進制度(SCOPE) (303万2130円(間接経費69万9722円含む)/2019年度,1300万円/2020年度、1300万円/2021年度) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\3032130 ( Direct expense: \2332408 、 Indirect expense:\699722 )

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  • 核融合炉向け耐放射線組み込みシステムの研究

    2019.04 - 2020.03

    自然科学研究機構 核融合科学研究所  一般共同研究 (18万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\180000 ( Direct expense: \180000 )

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  • 廃炉作業ロボット向け耐放射線組み込みシステムの開発

    2016.04 - 2019.03

    文部科学省  英知を結集した原子力科学技術・人材育成推進事業 廃炉加速化研究プログラム(国内研究)(1955万8777円/2016年度、1909万5651円/2017年度、1969万4695円/2018年度) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\58349123 ( Direct expense: \44883940 、 Indirect expense:\13465183 )

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  • 宇宙機器向けシールドレス耐放射線プログラマブルデバイスの研究開発

    2015.04 - 2018.03

    日本学術振興会  基盤研究(B) (1807万円(間接経費417万円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\18070000 ( Direct expense: \13900000 、 Indirect expense:\4170000 )

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  • 耐放射線FPGA(Field Programmable Gate Array)の研究開発

    2014.05 - 2016.03

    中部電力 原子力安全技術研究所  原子力に係る公募研究 (1000万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\10000000 ( Direct expense: \10000000 )

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  • 動的再構成型ビジョンVLSIの研究開発

    2014.05 - 2015.03

    静岡大学電子工学研究所  共同研究プロジェクト (28万5000円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • MEMS、ホログラムメモリを用いた光電子プロセッサ技術の研究

    2013.11 - 2014.11

    浜松科学技術研究振興会  科学技術試験研究助成 (40万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 動的再構成型ビジョンチップの研究開発

    2013.07 - 2014.03

    静岡大学電子工学研究所  共同研究プロジェクト (67万円) 

    渡邊 実

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  • 回折限界を打破する偏光ホログラムメモリシステムの研究開発

    2013.04 - 2016.03

    日本学術振興会  挑戦的萌芽研究 (390万円(間接経費90万円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\3900000 ( Direct expense: \3000000 、 Indirect expense:\900000 )

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  • 動的再構成型ビジョンVLSI

    2012.05 - 2013.03

    静岡大学電子工学研究所  共同研究プロジェクト (85万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 3次元光電子機械プログラマブルデバイスの開発と動的回路実装技術の確立

    2012.04 - 2015.03

    日本学術振興会  基盤研究(B) (1794万円(間接経費414万円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\17940000 ( Direct expense: \13800000 、 Indirect expense:\4140000 )

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  • ディペンダブル光FPGAの研究開発

    2012.04 - 2013.03

    総務省  戦略的情報通信研究開発推進制度(SCOPE) 【ICTイノベーション創出型研究開発】 (1863万6800円(間接経費430万800円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 高放射線環境下向け光電子組み込みシステムの開発

    2012.04 - 2013.03

    大川情報通信基金  (100万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 動的再構成型ビジョンVLSI

    2011.05 - 2012.03

    静岡大学電子工学研究所  共同研究プロジェクト (100万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • MEMS・ホログラムを用いたリアルタイム視覚情報処理システム

    2011.04 - 2013.03

    日本学術振興会  挑戦的萌芽研究 (377万円(間接経費87万円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • ホログラムストレージデバイス向けMEMS・レーザアレイ・アドレッシング技術

    2011.04 - 2012.03

    JST  大学特許価値向上支援 (350万円(間接経費73万7000円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 動的再構成型ビジョンチップの研究開発

    2010.05 - 2011.03

    静岡大学電子工学研究所  共同研究プロジェクト (75万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • プログラマブル・光再構成型ゲートアレイとライターの研究開発

    2008.04 - 2011.03

    日本学術振興会  基盤研究(C) ( 455万円(間接経費105万円含む)) 

    渡邊 実

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  • フーリエ補間による省回路サンプルレート変換器

    2008.04 - 2011.03

    日本学術振興会  基盤研究(C) (総額:377万円(間接経費87万円含む)、分担額:65万円(間接経費15万円含む)) 

    小林 史典

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    Grant type:Competitive

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  • MEMS・レーザーアレイによる高速動的光再構成型ゲートアレイの研究開発

    2008.04 - 2011.03

    文部科学省  新学術領域研究(研究課題提案型) (3380万円(間接経費780万円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 高速動的光再構成型プロセッサの研究開発

    2008.04 - 2011.03

    総務省  戦略的情報通信研究開発推進制度(SCOPE) 若手ICT研究者育成型研究開発(B) (1811万4200円(間接経費418万200円含む)) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 自律再構成可能な高信頼性ホログラムVLSIの研究開発

    2008.04 - 2009.03

    熊谷科学技術振興財団  (80万円) 

    渡邊 実

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  • 3次元光電子融合デバイスのノンアライメント実装技術の研究開発

    2007.10 - 2008.09

    電子回路基板技術振興財団  (100万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 光VLSIにおける配線を利用した光シールド技術の開発

    2006.04 - 2008.03

    日本学術振興会  若手研究(B) (350万円) 

    渡邊 実

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  • 部分再構成可能な高密度光再構成型ゲートアレイの開発

    2004.04 - 2007.03

    JST  育成研究 (8789万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • ダイナミック差分再構成型ゲートアレイ

    2004.04 - 2006.03

    日本学術振興会  若手研究(B) (370万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 組み込みシステム用再構成可能システム

    2002.04 - 2007.03

    文部科学省  知的クラスタ創成事業 (1億193万円(分担研究への配分額:2781万円)) 

    笹尾 勤

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    Grant type:Competitive

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  • 光再構成型ゲートアレイと再構成型プロセッサの実装

    2002.04 - 2003.03

    福岡県産業・科学技術振興財団  地域研究開発促進拠点支援事業 (250万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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  • 光再構成型ゲートアレイ

    2001.04 - 2002.03

    福岡県産業・科学技術振興財団  テーマ探索・シーズ発掘事業研究 (45万円) 

    渡邊 実

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    Authorship:Principal investigator  Grant type:Competitive

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Class subject in charge

  • iELST Advanced Study A (2025academic year) special  - その他

  • iELST Advanced Study B (2025academic year) special  - その他

  • Compilers (2025academic year) Third semester  - 月7~8,金1~2

  • Compilers (2025academic year) Third semester  - 月7~8,金1~2

  • Computer Architecture I (2025academic year) Fourth semester  - 水3~4,金5~6

  • Computer Architecture II (2025academic year) Fourth semester  - 水1~2,木3~4

  • Computer Architecture I (2025academic year) Fourth semester  - 水3~4,金5~6

  • Computer Architecture II (2025academic year) Fourth semester  - 火1~2,水5~6

  • Computer Hardware (2025academic year) Third semester  - 月1~2,木1~2

  • Computer Hardware (2025academic year) Third semester  - 月1~2,木1~2

  • Advanced Processor Engineering (2025academic year) Late  - 火3~4

  • Advanced Processor Engineering (2025academic year) Late  - 火3~4

  • Introduction to Information Technology Advanced Track (2025academic year) 1st semester  - 水1~2

  • Inquiry-Based Learning in Information Technology (2025academic year) 1st and 2nd semester  - [第1学期]木7~8, [第2学期]水5~6

  • Engineering English (2025academic year) Late  - その他

  • Advanced Study (2025academic year) Other  - その他

  • Technical Writing 1 (2025academic year) Prophase  - その他

  • Technical Writing 2 (2025academic year) Late  - その他

  • Advanced Research in Computer Hardware (2025academic year) Late  - その他

  • Seminar in Computer Engineering (2025academic year) Other  - その他

  • Seminar in Computer Engineering (2025academic year) Year-round  - その他

  • Compiler (2024academic year) Third semester  - 月7~8,金1~2

  • Compilers (2024academic year) Third semester  - 月7~8,金1~2

  • Compilers (2024academic year) Third semester  - 月7~8,金1~2

  • Computer Architecture I (2024academic year) Fourth semester  - 水3~4,金5~6

  • Computer Architecture II (2024academic year) Fourth semester  - 水1~2,木3~4

  • Computer Architecture I (2024academic year) Fourth semester  - 水3~4,金5~6

  • Computer Architecture II (2024academic year) Fourth semester  - 水1~2,木3~4

  • Computer Hardware (2024academic year) Third semester  - 月1~2,木1~2

  • Computer Hardware (2024academic year) Third semester  - 月1~2,木1~2

  • Advanced Processor Engineering (2024academic year) Late  - 火3~4

  • Advanced Processor Engineering (2024academic year) Late  - 火3~4

  • Engineering English (2024academic year) Late  - その他

  • Engineering English (2024academic year) Late  - その他

  • Advanced Study (2024academic year) Other  - その他

  • Technical Writing 1 (2024academic year) Prophase  - その他

  • Technical Writing 2 (2024academic year) Late  - その他

  • Technical Writing (2024academic year) Prophase  - その他

  • Technical Presentation (2024academic year) Late  - その他

  • Advanced Research in Computer Hardware (2024academic year) Late  - その他

  • Seminar in Computer Engineering (2024academic year) Year-round  - その他

  • Specific Research of Electronics and Information Systems Engineering (2024academic year) Year-round  - その他

  • Compiler (2023academic year) Third semester  - 月7~8,金1~2

  • Compilers (2023academic year) Third semester  - 月7~8,金1~2

  • Compilers (2023academic year) Third semester  - 月7~8,金1~2

  • Computer Architecture I (2023academic year) Third semester  - 月1~2,火7~8

  • Computer Architecture II (2023academic year) Fourth semester  - 水3~4,金5~6

  • Computer Architecture I (2023academic year) Third semester  - 月1~2,火7~8

  • Computer Architecture II (2023academic year) Fourth semester  - 水3~4,金5~6

  • Computer Hardware (2023academic year) Second semester  - 月1~2,木5~6

  • Computer Hardware (2023academic year) Second semester  - 月1~2,木5~6

  • Advanced Processor Engineering (2023academic year) Prophase  - その他

  • Advanced Processor Engineering (2023academic year) Prophase  - その他

  • Engineering English (2023academic year) Late  - その他

  • Engineering English (2023academic year) Late  - その他

  • Advanced Study (2023academic year) Other  - その他

  • Technical Writing 1 (2023academic year) Prophase  - その他

  • Technical Writing 2 (2023academic year) Late  - その他

  • Technical Writing (2023academic year) Prophase  - その他

  • Technical Presentation (2023academic year) Late  - その他

  • Advanced Research in Computer Hardware (2023academic year) Late  - その他

  • Advanced Research in Computer Hardware (2023academic year) Late  - その他

  • Seminar in Computer Engineering (2023academic year) Year-round  - その他

  • Seminar in Computer Engineering (2023academic year) Year-round  - その他

  • Specific Research of Electronics and Information Systems Engineering (2023academic year) Year-round  - その他

  • Compiler (2022academic year) Third semester  - 月5~6,金1~2

  • Compilers (2022academic year) Third semester  - 月5~6,金1~2

  • Compilers (2022academic year) Third semester  - 月5~6,金1~2

  • Computer Architecture I (2022academic year) Third semester  - 火7~8,木5~6

  • Computer Architecture II (2022academic year) Fourth semester  - 月3~4,水3~4

  • Computer Architecture II (2022academic year) Fourth semester  - 月3~4,水3~4

  • Computer Architecture I (2022academic year) Third semester  - 火7~8,木5~6

  • Computer Architecture II (2022academic year) Fourth semester  - 月3~4,水3~4

  • Computer Hardware (2022academic year) Second semester  - 月1~2,木5~6

  • Computer Hardware (2022academic year) Second semester  - 月1~2,木5~6

  • Advanced Processor Engineering (2022academic year) Prophase  - 火5~6,木3~4

  • Engineering English (2022academic year) Late  - その他

  • Technical Writing (2022academic year) Prophase  - その他

  • Technical Presentation (2022academic year) Late  - その他

  • Advanced Research in Computer Hardware (2022academic year) Late  - その他

  • Seminar in Computer Engineering (2022academic year) Year-round  - その他

  • Specific Research of Electronics and Information Systems Engineering (2022academic year) Year-round  - その他

  • Compiler (2021academic year) Third semester  - 月5,月6,金1,金2

  • Compilers (2021academic year) Third semester  - 月5,月6,金1,金2

  • Compilers (2021academic year) Third semester  - 月5,月6,金1,金2

  • Computer Architecture I (2021academic year) Third semester  - 月3,月4,木3,木4

  • Computer Architecture II (2021academic year) Fourth semester  - 月3,月4,水3,水4

  • Computer Architecture II (2021academic year) Fourth semester  - 月3,月4,水3,水4

  • Computer Architecture II (2021academic year) Fourth semester  - 月3,月4,水3,水4

  • Computer Architecture II (2021academic year) Fourth semester  - 月3,月4,水3,水4

  • Computer Architecture I (2021academic year) Third semester  - 月3,月4,木3,木4

  • Computer Hardware (2021academic year) Second semester  - 月5,月6,木5,木6

  • Advanced Processor Engineering (2021academic year) Prophase  - 火5~6,木3~4

  • Engineering English (2021academic year) Late  - その他

  • Technical Writing (2021academic year) Prophase  - その他

  • Technical Presentation (2021academic year) Late  - その他

  • Advanced Research in Computer Hardware (2021academic year) Late  - その他

  • Seminar in Computer Engineering (2021academic year) Year-round  - その他

  • Specific Research of Electronics and Information Systems Engineering (2021academic year) Year-round  - その他

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