Faculty Profiles - FUNABIKI Nobuo

MISC - FUNABIKI Nobuo

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A proposal of a two-stage discrete optimization method for the maximum clique problem

Nobuo Funabiki, Teruo Higashino

Proc. of International Symposium on Nonlinear Theory and Its Applications 1999

チャネル割当問題を対象とした拡張マキシマムニューラルネットワーク解法の提案

池永勝芳, 船曵信生, 竹中要一

電子情報通信学会論文誌A 1999

貪欲法とGAを併用したデータ転送路資源最適化問題解法の提案

四方康人, 船曵信生, 北道淳司

電子情報通信学会論文誌A 1999

A non-feedback neuron filter algorithm for separated board-level routing problems in FPGA-based logic emulation systems

Yoichi Takenaka, Nobuo Funabiki

Proc. of IEEE International Joint Conference on Neural Networks 1999

A gradual neural network approach for broadcast scheduling in packet radio networks

Nobuo Funabiki, Yoichi Takenaka, Teruo Higashino

Proc. of IEEE International Joint Conference on Neural Networks 1999

A Neuron Filter Algorithm for Board-Level Routing Problems in FPGA-Based Logic Emulation Systems

TAKENAKA Yoichi, FUNABIKI Nobuo

IEICE technical report. Nonlinear problems 98 ( 443 ) 23 - 29 1998.12

Language：English Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we propose a non-feedback neuron filter algorithm in the neural network. for the board-level routing problem (BLRP) in an FPGA-based logic emulation system. For a rapid prototyping of large scale digital systems, multiple FPGA's provide an efficient logic emulation system, where signals or nets between design partitions embedded on different FPGA's are connected through crossbars. We propose a new neuron filter algorithm to satisfy the two constraints of the problem simultaneously. The simulation results in randomly generated benchmark size instances show that our neuron filter algorithm with the thinning out application provides the better routing capability with the shorter computation time.

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A proposal of a three-stage greedy neural-network algorithm for FPGA routing problems

EGAWA Shinji, KURODA Eiji, KITAMICHI Junji, FUNABIKI Nobuo

IEICE technical report. Computer systems 98 ( 291 ) 69 - 75 1998.9

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we propose a three-stage routing algorithm for two-dimensional Field-Programmable Gate Arrays (FPGAs) by combining the greedy algorithm and the neural network algorithm. The three-stage algorithm consists of the route-candidate extraction stage, the greedy routing stage, and the neural network routing stage to achieve the high routability. The first stage extracts necessary route-candidates composed of a sequence of routing segments for every net. The second stage selects one of the candidates and assigns one track for each net so as to avoid short circuits. The final stage rearranges locations of shorter nets by the second stage to reduce the necessary tracks. We evaluate the performance of our algorithm by solving nine randomly generated instances, where the simulation results show that our three-stage algorithm achieves the high performance by used together.

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A proposal of a three - stage greedy neural - network algorithm for FPGA routing problems

EGAWA SHINJI, KURODA EIJI, KITAMICHI JUNJI, FUNABIKI NOBUO

IPSJ SIG Notes 1998 ( 87 ) 121 - 127 1998.9

Language：Japanese Publisher：Information Processing Society of Japan (IPSJ)

In this paper, we propose a three-stage routing algorithm for two-dimensional Field-Programmable Gate Arrays (FPGAs)by combining the greedy algorithm and the neural network algorithm. The three-stage algorithm consists of the route-candidate extraction stage, the greedy routing stage, and the neural network routing stage to achieve the high routability. The first stage extracts necessary route-candidates composed of a sequence of routing segments for every net. The second stage selects one of the candidates and assigns one track for each net so as to avoid short circuits. The final stage rearranges locations of shorter nets by the second stage to reduce the necessary tracks. We evaluate the performance of our algorithm by solving nine randomly generated instances, where the simulation results show that our three-stage algorithm achieves the high performance by used together.

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A Maxumum Neural Network Algorithm for a Channel Assignment Problem in Cellular Radio Networks

IKENAGA Katsuyoshi, FUNABIKI Nobuo, TAKENAKA Yoichi, KITAMICHI Junji

IEICE technical report. Nonlinear problems 97 ( 592 ) 85 - 92 1998.3

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we propose a neural network algorithm using the maximum neuron model for the static channel assignment problem in cellular radio networks under the minimization of mutual interferences. The goal of this problem is to minimize the total interferences between calls subject to the constraint that all requested calls must be accepted. Our algorithm uses the expanded maximum neuron model to satisfy the constraint. In order to improve the solution quality, the regular interval assignment is adopted into a cell with the largest demands. In addition, the shaking term, the hill-climbing term, and the omega function are used together in the motion equation. We verify the performance through simulations using benchmark problems, where our algorithm finds better solutions than the existing algorithms.

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A Performance Evaluation of Digital Neural Network Algorithms for Stable Marriage Problems

TAJIMA Shigeto, FUNABIKI Nobuo, KITAMITI Junji

IEICE technical report. Nonlinear problems 97 ( 592 ) 77 - 84 1998.3

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we evalute the performance of digital neural network algorithms using three neuron models (binary neuron model, hysteresis binary neuron model, and maximum neuron model) and three computation methods (synchronous parallel computation method, N-parallel computation method, and sequential computation method) for the stable marriage problem. The goal of the problem is to find N stable pairs of N men and N women under given preference lists. A pair becomes unstable when there is an unpaired couple of a man and a woman who prefers each other to their actual partners. The simulation results through randomly generated instances show that the performance of the maximum neuron model on the sequential computation method surpasses the other methods in terms of the convergence properly and the solution quality.

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An Application of Convex Hull to Genetic Algorithm for Traveling Salesman Problem

TAKENAKA Yoichi, FUNABIKI Nobuo

Technical report of IEICE. SS 97 ( 521 ) 17 - 24 1998.1

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we propose an application of the "visiting order restriction theorem" to Pal's algorithm, a genetic algorithm for the traveling salesman problem (TSP). The visiting order restriction theorem gives a necessary condition for the shortest tour of TSP on the Euclidean plane by using the convex hull. The convex hull of a set of points S on a plane is defined as the smallest convex polygon that encloses S. The O (|S|log|S|)-time algorithm has been known to find the convex hull of a set of points S. The genetic algorithm, which simulates the process of the natural selection, is known as one of best approximate algorithms for TSP. In our method, the initial tours are produced to satisfy the necessary condeition for the shortest path in order to improve the solution quality. The simulation results using benchmark problems show our genetic algorithm finds shorter tours than P'al's algorithm at the large size benchmark problems.

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A gradual neural-network algorithm for jointly time-slot/code assignment problems in packet radio networks

Nobuo Funabiki, Junji Kitamichi

IEEE Transactions on Neural Networks 9 ( 6 ) 1523 - 1528 1998

Language：English

A gradual neural network (GNN) algorithm is presented for the jointly time-slot/code assignment problem (JTCAP) in a packet radio network in this paper. The goal of this newly defined problem is to find a simultaneous assignment of a time-slot and a code to each communication link, whereas time-slots and codes have been independently assigned in existing algorithms. A time/code division multiple access protocol is adopted for conflict-free communications, where packets are transmitted in repetition of fixed-length time-slots with specific codes. GNN seeks the time-slot/code assignment with the minimum number of time-slots subject to two constraints: 1) the number of codes must not exceed its upper limit and 2) any couple of links within conflict distance must not be assigned to the same time-slot/code pair. The restricted problem for only one code is known to be NP-complete. The performance of GNN is verified through solving 3000 instances with 100-500 nodes and 100-1000 links. The comparison with the lower bound and a greedy algorithm shows the superiority of GNN in terms of the solution quality with the comparable computation time. © 1998 IEEE.

DOI： 10.1109/72.728402

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An evolutionary neural network approach for module orientation problems

Nobuo Funabiki, Junji Kitamichi, Seishi Nishikawa

IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics 28 ( 6 ) 849 - 855 1998

Language：English

A novel neural network approach called "Evolutionary Neural Network (ENN)" is presented for the module orientation problem. The goal of this NP-complete problem is to minimize the total wire length by flipping circuit modules with respect to their vertical and/or horizontal axes of symmetry. In order to achieve high quality VLSI systems, it is strongly desired to solve the problem as quickly as possible in the design cycle. Based on the concept of the genetic algorithm, the evolutionary initialization scheme on neuron states is introduced so as to provide a high quality solution within a very short time. The performance of ENN is compared with three heuristic algorithms through simulations on 20 examples with up to 500 modules. The results show that ENN can find the best solutions in the shortest time. © 1998 IEEE.

DOI： 10.1109/3477.735394

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A Formal Method of Proving Invariants for Synchronous Sequential Circuits with Plural Controllers

SAITOH YOSHIKATSU, TAKENAKA TAKASHI, KITAMICHI JUNJI, FUNABIKI NOBUO

IPSJ SIG Notes 97 ( 119 ) 41 - 48 1997.12

Language：Japanese Publisher：Information Processing Society of Japan (IPSJ)

In this paper, we propose a formal method of proving invariants for synchronous sequential circuits with plural controllers in high level design. The invariant is the relationship among registers and signals that the user asserts. The circuit design consists of several finite state machines (controllers) and datapath. The invariants can be set at arbitrary finite states by user. The execution conditions, operations in datapath, and invariants are described with variables and functions over Boolean, integer, and abstract data type defined by user. The invariants are proved on the assumption that several invariants, datapath, execution conditions, and lemmas for user-defined functions are correct. This proof uses the structural induction on finite states. On proving invariants, the system a product controller which is equivalent to each controllers and proves by structural induction with the product controller. We eliminate unreachable states on generating the product controller. The sufficient conditions of expressions to prove are proved with a decision algorithm for the truth of Presburger sentence. We evaluate the proposed method for verifying the correctness of the PCI bus interface circuit design.

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A Neural Network for One-Shot Scheduling Problems in Multicast Packet Switching Systems

BABA Takayuki, FUNABIKI Nobuo, NISHIKAWA Seishi

The Transactions of the Institute of Electronics,Information and Communication Engineers. A 80 ( 11 ) 1973 - 1981 1997.11

A Proposal of a Neuro-GA Hybrid Algorithm for Data Transfer Binding Problems

SHIKATA Yasuhito, FUNABIKI Nobuo, KITAMICHI Junji, NISHIKAWA Seishi

Technical report of IEICE. SS 97 ( 261 ) 23 - 30 1997.9

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

High-level synthesis from behavioral descriptions for VLSI systems is devided into three sub-problems. In this paper, we propose an approximation algorithm using a neural network and a genetic algorithm for the data transfer binding problem which is one of the sub-problems. Our algorithm adopts the bus-oriented interconnection style. The simulation results through benchmark instances show that the proposed algorithm is superior to existing algorithms in terms of the solution quality, although it is inferior in computational time.

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A neural network approach for multilayer over-the-cell channel routing problems

Nobuo Funabiki, Seishi Nishikawa

Neurocomputing 16 ( 4 ) 319 - 332 1997.9

Language：English Publisher：Elsevier Sci B.V.

A new algorithm for multilayer over-the-cell channel routing problems using two neural networks is presented in this paper. In the multilayer over- the-cell channel routing problem, signal nets may be placed not only in the multilayer channel between two cells, but also on the multilayer routing area over the cells. The goal of our algorithm is to route all the given nets in both routing areas with the minimum number of tracks in the channel. Our algorithm consists of four steps: (1) extracting nets for the over-the-cell routing, (2) routing nets in the multilayer over-the-cell muting area by the neural network, (3) transforming nets for the channel routing and (4) routing nets in the multilayer channel by the neural network. The performance of our algorithm was verified through seven benchmark problems with 1-4 layers for the over-the-cell and 2-8 layers for the channel. The simulation results support the flexibility of our algorithm in the multilayer over-the-cell channel routing problem.

DOI： 10.1016/S0925-2312(97)00039-8

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The Stability of Discrete Neural Network for Combinational Optimization

UMETANI Shunji, FUNABIKI Nobuo, NISHIKAWA Seishi

IEICE technical report. Neurocomputing 97 ( 201 ) 1 - 8 1997.7

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we study the convergence property of the Hopfield neural network using the binary neuron model named Discrete Neural Network (DNN). First, we present that DNN converges to a local minimum when the following two conditions are satisfied; (1)DNN has no self-interaction, and (2)the state of each neuron is updated asynchronously. Then, we discuss the behaviour of DNN if either condition is not satisfied so that we explain the cause of oscillatory behaviour.

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A proposal of a greedy neural network algorithm for route assignment problems in multihop radio networks

BABA Takayuki, FUNABIKI Nobuo, NISHIKAWA Seishi

IEICE technical report. Theoretical foundations of Computing 97 ( 157 ) 41 - 48 1997.7

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In a multihop radio network, packets are transmitted from source nodes to destination nodes by activating several links between nodes. Each node can either send a packet to, or receive a packet from, at most one of its adjacent nodes simultaneously. In order to minimize the transmission time for given requests, the route assignment problem must be solved to assign a transmission route for each request, and the link activation problem must be solved to find a link activation schedule. The route assignment problem is decomposed into two sub-problems: the candidate extraction problem and the route selection problem. In this paper, we introduce a new cost function for the route assignment problem, propose the plural candidates extraction method for the candidate extraction problem, and propose the greedy neural network algorithm for the route selection problem. Through simulations up to 500-node networks, we verify that our algorithm finds better solutions in shorter time and with smaller space than the existing algorithms.

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A proposal of "Neuron Filter" for Hopfield-type Neural Networks through Traveling Salesman Problems

TAKENAKA Yoichi, FUNABIKI Nobuo, NISHIKAWA Seishi

IEICE technical report. Neurocomputing 96 ( 583 ) 287 - 294 1997.3

Language：Japanese Publisher：The Institute of Electronics, Information and Communication Engineers

In this paper, we propose "Neuron Filter" as restricting the neural region to satify some constraints in order to improve the performance of Hopfield-type neural networks. Neuron Filter processes neuron states to satisfy constraints of combinatorial optimization problems. Neuron Filter is classified into "Maximum Neuron" and "Neuron Mask". Maximum Neuron feedbacks the outputs for the state update computations of neural networks, while Neuron Mask does not feedback them. This paper presents the definition of Neuron Filter and the introduction into the neural network through the travelling salesman problem. We verify the performance by solving benchmark problems, where the simulation results show Neuron Filter improves the performance of the neural network.

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