研究者詳細 - 横平　徳美

論文 - 横平　徳美

分割表示 149 件中 101 - 120 件目／全件表示 >>

An Optimal Path Selection Algorithm for Static and Mobile Multicast Routing Problems 査読

S.Tajima, M.Fujii, N.Funabiki, T.Yokohira, K.Tsunemura, T.Higashino

International Conference on Information Networking 2002 2002年

A Minimal-state Processing Search Alogorithm for satisfiability problems 査読

Proc. IEEE International Conference on System, Man, and Cybernetics pp.2769-2774 2001年10月

ネットワークのリンクスケジューリングへのグラフ彩色アプローチ査読

田島滋人, 舩曵信生, 東野輝夫, 横平徳美, 中西透

電子情報通信学会技術研究報告, COMP2001-71 2001年

モバイル・マルチキャストルーティング問題に対する最適パス選択解法の提案査読

常村和史, 田島滋人, 藤井雅和, 中田明夫, 横平徳美, 舩曵信生, 東野輝夫

マルチメディア通信と分散処理ワークショップ講演集 2001年

EDDコネクション受付制御方式における遅延余裕の一割当法－最悪リンク遅延に比例した割当て－査読

横平徳美, 岡本卓爾

電子情報通信学会論文誌 2001年

Universal Test Complexity of Field-Programmable Gate Arrays 査読

Tokumi Yokohira

Proc. Fourth Asian Test Symposium (ATS ''95) pp.259-265 2000年6月

LAN，MANにおける波長分割多重パケット交換網の最適化査読

横平徳美, 岡本卓爾

電子情報通信学会論文誌 2000年

Testing for the Programming Circuit of SRAM-Based FPGAs 査読

The Transactions of the IEICE E82D ( 6 ) 1051 - 1057 1999年6月

Quantitative Analysis of Knee-Joint Spasticity by Pendulum Test 査読

Kazuaki Jikuya, Tokumi Yokohira, Takuji Okamoto, Ken Akashi

Proc. The 4th Asia-Pacific Conference on Medical and Biological Engineering p.122 1999年

ルーチングマトリクスを有するFPGAの配線領域の検査法査読

道西博行, 横平徳美, 岡本卓爾

電子情報通信学会論文誌 Vol.J82-D-I, No.7, pp.916-924 1999年

Testing for the programming circuit of SRAM-based FPGAs

Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamotq, Tomoo Inoue, Hideo Fujiwara

IEICE Transactions on Information and Systems E82-D ( 6 ) 1051 - 1057 1999年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Institute of Electronics, Information and Communication, Engineers, IEICE

The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC-1025.

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テーブル参照型FPGAにおける論理ブロックの検査法査読

道西博行, 横平徳美, 岡本卓爾, 井上智夫, 藤原秀雄

電子情報通信学会論文誌 Vol.J79-D-I, No.12, pp.1141-1150 1996年12月

A Test Methodology for Interconnect Structures of LUT-based FPGAs 査読

Proceedings of the Fifth Asian Test Symposium pp.68-74 1996年11月

Testing for the Programming Circuit of LUT-Based FPGAs 査読

Proc. Sixth Asian Test Symposium (ATS ''97) pp.242-247 1996年11月

Realization of multiwindow system with high-speed operations of nonrectangular windows 査読

Toshiyuki Maeda, Yoichiro Sato, Tokumi Yokohira, Takuji Okamoto

Systems and Computers in Japan 27 ( 10 ) 48 - 58 1996年

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：John Wiley and Sons Inc.

This paper describes the realization of the multi-window system, where the framed nonrectangular windows can be operated with a high speed. The body image (the image to be displayed inside the frame) and the frame image (the image to be displayed as the frame), which are stored on the multiport memory, are read out in parallel, being synchronized to the CRT scanning. By selecting pixelwise one of those images, the window image displayed in the window is generated as a framed image. The selection signal for this purpose is generated based on the window shape information stored in the dedicated memory. The multiwindow image is generated by selecting the image to be displayed for each pixel position on CRT using a hardware. A distributed priority encoder is used as the hardware for this purpose. According to the result of construction and experiment, it is expected that the multiwindow system can realize a sufficiently high-speed operation from the practical viewpoint for the 1200 × 1000 CRT screen using the existing circuit technology.

DOI： 10.1002/scj.4690271005

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Universal Test Complexity of Field-Programmable Gate Arrays 査読

Proceeding of the Fourth Asian Test Symposium pp.259-265 1995年11月

The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuit with Five Outputs 査読

The Transactions of the IEICE Vol.E78-D, No.7, pp.874-881 1995年7月

非長方形ウィンドウの高速操作機能を備えたマルチウィンドウシステムの実現法査読

前田敏行, 佐藤洋一郎, 横平徳美, 岡本卓爾

電子情報通信学会論文誌 Vol.J78-D-I, No.6, pp.509-518 1995年6月

痙縮患者を対象としたペンドラムテストモデルの精度改善査読

軸屋和明, 岡本卓爾, 横平徳美, 明石謙

電子情報通信学会論文誌 Vol.J78-D-II, No.4, pp.650-660 1995年4月

DESIGN ALGORITHM FOR PACKET-SWITCHING NETWORKS WITH DIFFERENT CLASSES OF PACKETS - CAPACITY, PRIORITY, AND FLOW ASSIGNMENT UNDER END-TO-END PACKET DELAY CONSTRAINT 査読

M SUGANO, H TAKASHINA, T YOKOHIRA, T OKAMOTO

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS 78 ( 2 ) 1 - 12 1995年2月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：SCRIPTA TECHNICA-JOHN WILEY & SONS

This paper proposes a design algorithm for packet-switching networks with different classes of packets under end-to-end packet delay constraint and a design algorithm for fault-tolerant networks. The former is a heuristic capacity, priority, and flow assignment algorithm which locally minimizes the network cost while satisfying a constraint that the average transmission delay of each class of packets between two arbitrary nodes never exceed a value predetermined for the class.
This algorithm is composed of three subalgorithms and the cost minimization is pursued by iterating these algorithms as long as the constraint is satisfied. The latter is a design algorithm for a fault-tolerant network which satisfies the foregoing constraint even if an arbitrary single link fails. With this algorithm, an assignment with relatively large cost but satisfying the constraint is obtained first. Then a procedure of reducing the capacity of a link whose effect on cost reduction is great but whose effect on path delay increase is not so great is iterated to reduce the network cost as long as the constraint is satisfied.

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