担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/socc58585.2023.10257130

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担当区分：最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/newcas57931.2023.10198189

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：筆頭著者,　最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/iscas46773.2023.10181472

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担当区分：責任著者  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/icce56470.2023.10043521

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/APCCAS55924.2022.10090314

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担当区分：筆頭著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ICECS202256217.2022.9970905

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：筆頭著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.7567/JJAP.54.09MA06

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/CCWC54503.2022.9720794

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ICFPT52863.2021.9609910

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1016/j.optmat.2021.111932

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.7567/JJAP.54.09MA06

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ipc48725.2021.9592957

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.23919/moc52031.2021.9598095

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/iscas51556.2021.9401291

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1364/osac.415702

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/jphot.2020.3038900

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1364/AO.396525

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ICP46580.2020.9206463

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/APCCAS47518.2019.8953122

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.23919/MOC46630.2019.8982829

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/WMED.2019.8714154

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（その他学術会議資料等）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ICSENG.2018.8638203

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：筆頭著者,　最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ICSJ.2018.8602907

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1364/AO.57.008625

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/SMELEC.2018.8481328

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/AHS.2018.8541375

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ICSIGSYS.2018.8372766

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ISCAS.2018.8351543

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記述言語：英語  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are investigated for the applications requiring high reliability using an optically reconfigurable gate array. The optical properties and internal grating structures are investigated by using a cobalt 60 gamma radiation source to examine the resistance of 100 Mrad total-ionizing-dose.

DOI： 10.23919/MOC.2017.8244556

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Total ionizing dose tolerances of current integrated circuits are limited to 3-10 kGy because semiconductor devices are fundamentally vulnerable to radiation. However, using programmable architecture, the total ionizing dose tolerances of integrated circuits can be increased if the integrated circuits can be repaired each time a permanent failure occurs. Nevertheless, current programmable devices cannot allow such repairable use because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged. To increase the radiation tolerance of integrated circuits, this paper presents a proposal of a new optoelectronic programmable device with a parallel light configuration architecture instead of current field programmable gate arrays which have a serial configuration architecture. This demonstration confirms 1.9 MGy radiation tolerance on an optoelectronic programmable device using a non-radiation-hardened standard complementary metal oxide semiconductor process. (C) 2017 Optical Society of America

DOI： 10.1364/OE.25.028136

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：NATL INST SCIENCE COMMUNICATION-NISCAIR  

Optically reconfigurable gate array (ORGA) is a type of multi-context field programmable gate array (FPGA) that has achieved a nanosecond-order reconfiguration capability as well as attaining numerous reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the function of multi-core processor. ORGA system has high dependability in a radiation rich environment and the development is progressing towards better radiation tolerance. In this paper, size minimization of the ORGA-VLSI is the main concern to maintain its high dependability; hence wire complexity needs special consideration during floor planning. A case of Fast Fourier Transform (FFT) is shown to demonstrate the effectiveness of circuit modification by implementing dynamic reconfiguration for area optimization. Results show that, compared with a normal FFT configuration, the minimum wirelength is reduced 5.5% for a 32-point FFT implementation.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Radiation-hardened optically reconfigurable gate arrays have been developed for use in space embedded systems. An optically reconfigurable gate array consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI, which is one type of radiation-hardened SRAM-based field programmable gate array (FPGA). However, optically reconfigurable gate arrays have the important feature of faster scrubbing operations than that of radiation-hardened SRAM-based FPGAs. Therefore, the soft-error-tol er anees of the configuration memories of optically reconfigurable gate arrays become much higher than those of FPGAs. However, the calculation load of a lot of holographic memory patterns on a personal computer is extremely heavy. This paper therefore presents a hardware accelerator using an FPGA. The Vivado-high-level synthesis tool (Xilinx Inc.) has been used for development. Its operation speed was improved drastically from 1,590 ms to 3.12 ms while its power consumption for calculations has been decreased drastically from 55 W to 4.4 W.

DOI： 10.1109/ICSOS.2017.8357225

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ICSJ.2017.8240123

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V
Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770
Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770
Intel Corp.).

DOI： 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.109

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as the Fukushima Daiichi nuclear power plant. According to recent news, regions with 650 Sv/h radiation have been found at the Fukushima Daiichi nuclear power plant. Under such extremely high radiation environments, high-speed scrubbing operations must be used to maintain correct circuit information on the configuration memory of programmable gate arrays. Up to now, optical high-speed scrubbing based on an optically reconfigurable gate array has been proposed. This paper presents a demonstration of the radiation tolerance of the optical high-speed scrubbing based on an optically reconfigurable gate array VLSI by using lasers that emulate strong radiation environments. It has been confirmed that 70-ns period high-speed scrubbing operations on the optically reconfigurable gate array are never disturbed by the emulated radiation.

DOI： 10.1109/SOCC.2017.8226014

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, optically reconfigurable gate arrays consisting of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI have been under development as high-speed dynamic reconfigurable devices. High-speed dynamic reconfiguration of optically reconfigurable gate arrays can be achieved using a two-dimensional optical bus. If such high-speed reconfiguration were feasible, then its programmable gate array performance could be increased dramatically. This paper presents a demonstration of high-speed asynchronous optical dynamic reconfiguration based on an optically reconfigurable gate array VLSI. The reconfiguration speed of the optically reconfigurable gate array can reach 206.44 Gbit/s.

DOI： 10.1109/INTECH.2017.8102440

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Two salient concerns of current field programmable gate arrays (FPGAs) used for space applications are how to block soft errors that arise on their configuration memories and how to treat permanent failures attributable to total dose effects. To date, those two main concerns have been treated separately, but we present a proposal for multi-context scrubbing to 'kill two birds with one stone' and resolve both issues simultaneously. To decrease the frequency of soft errors arising on the configuration memories of FPGAs, applying scrubbing operations for configuration memories is extremely useful. Since faster scrubbing can increase the radiation tolerances of the configuration memories on FPGAs, optical high-speed scrubbing using optically reconfigurable gate array (ORGA) architecture is introduced. Up to now, major scrubbing operations have invariably used a single configuration context, but since the storage capacities of holographic memories on ORGAs are high, many configuration contexts can be stored on a holographic memory. Thereby, various configuration contexts that avoid permanent failures can be used cyclically for scrubbing operations. Even if a permanent failure occurs on the programmable gate array during scrubbing operations, which exploit numerous configuration contexts, correct operations can be executed.

DOI： 10.1109/MWSCAS.2017.8053231

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Currently, radiation-hardened static random access memory (SRAM) based field programmable gate arrays (FPGAS) are used frequently for space applications. Invariably, such SRAM-based FPGAS are used along with an electrically erasable programmable read-only memory (EEPROM). Although the radiation tolerance of data stored on EEPROMs is much higher than that stored on SRAMs, the radiation tolerance of the data on an EEPROM is not perfectly safe because electrons on the floating gates of transistors are also disturbed by strong radiation. If high-energy charged particles are incident to the EEPROM, then the EEPROM data might be destroyed by the radiation. In stark contrast, the radiation tolerances of holographic memories are perfect Recording and reading of holographic memory can be executed optically. They never depend on electrons or holes. Moreover, data stored on holographic memory are read by summations of numerous light waves. The operation can be regarded as a majority voting operation. Therefore, even if half of a holographic memory is removed, the remaining half of the holographic memory can generate recorded data correctly. This paper describes a holographic memory based FPGA or an optically reconfigurable gate array (ORGA). Furthermore, this paper explains that a holographic memory can function correctly up to a 500 Mrad total-ionizing-dose, exhibiting 1,667 times higher radiation tolerance than current radiation-hardened VLSIs and FPGAS.

DOI： 10.1109/AHS.2017.8046374

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as that of the Fukushima Daiichi nuclear power plant. According to recently reported news, an area with 650 Sv/h radiation intensity has been confirmed outside of a containment vessel at the Fukushima Daiichi nuclear power plant. For uses under such extremely high radiation environments, high-speed scrubbing operations must be applied for FPGAs. A high-speed optical scrubbing method that can be used on optically reconfigurable gate arrays has been proposed in recent reports of the literature. Such optically reconfigurable gate arrays using optical high-speed scrubbing can be used in environments with intense radiation. In addition, to increase the optical scrubbing operation speed, this paper demonstrates a high-speed optical scrubbing method with a simpler sequence for use on an optically reconfigurable gate array. The 50 ns period high-speed scrubbing operation could be confirmed on the fabricated optically reconfigurable gate array VLSI.

DOI： 10.1109/OPTIP.2017.8030702

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.

DOI： 10.1109/NAECON.2017.8268761

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are discussed in the application for an optically reconfigurable gate array. The radiation experiments are conducted using a cobalt 60 gamma radiation source to examine the tolerance of a 100 Mrad total ionizing dose for the HPDLC memory. The optical properties are compared in the conditions before and after gamma-ray irradiation for the fabricated HPDLC gratings. The effects of gamma-ray irradiation on the internal grating structure are also investigated by polarization optical microscopy and scanning electron microscopy observations. The HPDLC memory irradiated by a 100 Mrad total ionizing dose demonstrates the implementation of the optical reconfiguration in a gate-array VLSI. (C) 2017 Optical Society of America

DOI： 10.1364/AO.56.004854

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Currently, radiation-hardened field programmable gate arrays (FPGAs) are sought for embedded systems designed for use in space. However, in terms of soft-error and permanent failure, the radiation tolerances of configuration memories on current FPGAS are not high. Therefore, to remove the soft-error on configuration memories of FPGAS, optically reconfigurable gate arrays with a parallel configuration capability have been proposed. The optically reconfigurable gate array consists of an optically reconfigurable gate array VLSI, a holographic memory, and a laser array. Since the optically reconfigurable gate array allows high-speed scrubbing of its configuration memory, the soft-error factor on configuration memory can be removed from consideration. Moreover, the parallel configuration allows uses of radiation-damaged gate arrays so that the optically reconfig-urable gate array can increase the radiation tolerance. However to support such high-speed scrubbing, its optical part must work correctly even if it receives a large amount of radiation. This paper therefore presents a system in which the holographic memory can function correctly despite exposure up to 300 Mrad total-ionizing-dose, which is 300-times-higher radiation tolerance than those of current VLSIs and FPGAS.

DOI： 10.1109/ISNE.2017.7968743

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, radiation-hardened embedded systems are demanded for robots that must function in high-radiation environments such as those prevailing at the Fukushima Daiichi and Chernobyl nuclear power plants. Recent news reports have described the discovery of a 650 Sv/h radiation region near the containment vessels of the Fukushima Daiichi nuclear power plant. Even under such a dauntingly intense radiation environment, workable robots are required. This paper therefore present a high-soft-error-tolerant 16-bit adder unit based on penta-modular redundancy (SMR) in addition to triple modular redundancy (TMR). The soft-error tolerances of the TMR and SMR were analyzed theoretically. Such TMR and SMR circuits were implemented onto a field programmable gate array (FPGA). Then error-injection experiments for the TMR and SMR were done on the FPGA. Analytical results have revealed that SMR 16-bit adder circuit is useful for heavy radiation environments.

DOI： 10.1109/ISNE.2017.7968746

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, radiation-hardened embedded systems are sought for robots working under high-radiation environments such as the Fukushima Daiichi and Chernobyl nuclear power plants. Recent news reports have described a region with 650 Sv/h radiation outside of containment vessels at the Fukushima Daiichi nuclear power plant. Even in such heavy radiation environments, functioning robots are required. This paper therefore presents radiation-hardened motor controllers used for robots. The radiation tolerances of motor controllers were evaluated using irradiation by a 60Co gamma source.

DOI： 10.1109/ISNE.2017.7968747

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs. (C) 2017 Optical Society of America

DOI： 10.1364/OE.25.007807

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：電子情報通信学会  

近年，FPGAは家電製品，自動車，そして宇宙システムと幅広い用途に使用されている．しかし，2000年代前半まで，FPGAはASICと比較して性能が低く，試作，テスト，研究用途に用いられただけで，量産品に対してはコストあたりの性能に秀でたASICが多用されてきた．これが変わるのが2000年代後半であり，FPGAは最先端のプロセスが利用できる数少ない集積回路の一つとなり，高性能な製品を生み出す主役の座に躍り出た．その代表的なものの一つにFPGAを利用したハードウェア・アクセラレータがあり，その有効性については，MicrosoftがBing検索に用いるデータセンターに対してFPGAを用いたサーバーを開発したり，Intel社がXeonプロセッサにFPGAを実装する等，もはや疑う余地がなくなったと言える．そして今日，FPGAベンダーは開発に多大な工数を要したハードウェア記述言語(HDL)の代わりに，C++からFPGAへの回路実装が可能な汎用的な高位合成ツールの提供を開始している．このような皆高位合成ツール時代のFPGA開発において，各企業が他社との優位性を確保するためには，これら万人向けに作られた汎用高位合成ツールやベンダーから提供されるHDL開発環境等を活用するだけでなく，汎用ツールの弱点を補完でき，より高性能な製品をより少ない工数で開発できる特定用途向けのツール群が必要になる．本論文では既に広く有効性が認知された汎用的な高位合成ツールではなく，まだ認知度が低いが日本で独自に開発が進められる「日の丸」ツール群を紹介する．

DOI： 10.14923/transcomj.2016jbi0002

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a highspeed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.

DOI： 10.1109/CCWC.2017.7868473

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Today, although Blu-ray, DVD, CD, hard disk drive, solid state drive, electrically erasable programmable read-only memory (EEPROM) are available, the lifetime of stored data is short. To store large amounts of data longer than 100 years, long-term data storage media are necessary. Moreover, systems designed for use in space require highly radiation-tolerant memory. As long-term data storage media this study demonstrates that a polymer-dispersed liquid crystal holographic memory has a high radiation tolerance by using a cobalt 60 gamma radiation source. Results show that the holographic memory radiation tolerance is more than 667 times higher than EEPROM radiation tolerance.

DOI： 10.1109/HPCC-SmartCity-DSS.2016.29

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, studies have matured of field programmable gate arrays (FPGAs) that realize hardware acceleration. For such hardware acceleration on FPGAs, hugely parallel computation is frequently used. Consequently, numerous identical circuits are implemented onto an FPGA. However, identical configuration contexts of numerous identical circuits are stored on different regions of the configuration memory when a using currently available FPGA, which is exceedingly wasteful. Therefore, we propose a parallel-operation-oriented ORGA with many gate array layers sharing a common configuration context. In programmable devices, the configuration memory and configuration circuit occupy a large implementation area: 70 % - 80 % of the entire VLSI chip area. For that reason, the gate density of the programmable device could be increased if the amount of configuration memory were decreased. Therefore, a parallel-operation-oriented ORGA presents advantages in terms of gate density. Furthermore, the parallel-operation-oriented ORGA architecture presents the important advantage of shorter compilation time. This study clarifies the benefits of the parallel-operation-oriented ORGA in comparison to those of an FPGA having equivalent gate array structure based on the same process technology.

DOI： 10.1109/ICAMechS.2016.7813465

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

An optically reconfigurable gate array (ORGA), an alternative technology to commercially available field programmable gate arrays (FPGAs), is much faster. Moreover, it can operate in radiation-rich environments. An ORGA uses a laser array, a holographic memory, and an ORGA-VLSI chip including a fine-grained programmable gate array. Many configuration contexts can be stored on the holographic memory and can be addressed by the laser array. The ORGA-VLSI can be programmed optically through numerous photodiodes. To realize faster configuration, measuring the variation of photodiode characteristics is extremely important. Nevertheless, photodiode characteristics have not been estimated to date because measurements must be done using its programmable gate array such that the measurement results include a photodiode response time and propagation delay on the programmable gate array. They cannot be classified clearly. Therefore, this paper proposes a photodiode sensitivity measurement method using low light intensity. Results show that the measurement methodology can remove the propagation delay factor and can extract photodiode sensitivity.

DOI： 10.1109/ICCSE.2016.7581623

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by constructing a laser illumination system to implement successive laser exposures at different small regions in a glass cell filled with LC composites. The context pattern arrangements for circuit information are designed in a 3 x 3 in. 2 photomask by electron beam lithography, and they are recorded as laser interference patterns at nine regions separated in an HPDLC sample by a laser interferometer composed of movable pinhole and photomask plates placed on motorized stages. The multi-context information reconstructed from the different regions in the HPDLC is written to a photodiode array in a gate-array VLSI by switching only the position of laser irradiation using the displacement of the pinhole plate under the control of a personal computer ( PC). The effects of multi-context information recorded at different regions in the HPDLC on optical reconfiguration are discussed in terms of the optical system composed of ORGA VLSI and HPDLC memory. The internal structures in the HPDLC memory formed by multi-context recording are investigated by scanning electron microscopy ( SEM) observation, and the configurations composed of LC and polymer phases are revealed at various regions in the HPDLC memory. (C) 2016 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.55.08RG04

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

As one type of field programmable gate array (FPGA), optically reconfigurable gate arrays (ORGAs) have been undergoing continual development. ORGAs are optoelectronic devices consisting of a holographic memory, a laser array, a programmable gate array. Since the storage capacity of such holographic memory is greater than that of two-dimensional semiconductor memory, an ORGA can accommodate more huge gates and provide higher performance than FPGAs. A programmable gate array of an ORGA has numerous photodiodes that can be reconfigured optically using configuration contexts on a holographic memory. Although the photodiodes are normally used only for a configuration procedure, the photodiodes are useful for direct input of optical communication signals. This paper therefore presents a demonstration of optical communication on ORGA's programmable gate array.

DOI： 10.1109/FGCT.2016.7605065

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) comprise a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. According to holographic memory properties, the reconfiguration speed and radiation tolerance of ORGAs depend on the number of bright bits included in a configuration context. This paper therefore proposes a method of reducing the number of bright bits included in a configuration context using negative logic implementation. Since the method is architecture-independent, the method offers the important benefit that it is never necessary to modify the architecture of optically reconfigurable gate array VLSIs. This paper describes experimental demonstrations of the reconfiguration speed and radiation-tolerance advantages of the method.

DOI： 10.1109/ICMAE.2016.7549570

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Currently, space systems require highly radiation tolerant memory. If memory with high radiation tolerance were available, then shielding of embedded systems for use in space could be reduced or removed, thereby greatly decreasing the weight of such space embedded systems. This study examines the radiation-hardened characteristics of a holographic memory. Using a cobalt 60 gamma radiation source, radiation experiments were conducted for a photopolymer holographic memory. Results show that the holographic memory can function correctly at a 100 Mrad total-ionizing dose. The radiation tolerance of the holographic memory is over 300 times higher than that of an electrically erasable programmable read-only memory (EEPROM). Moreover, this paper shows a demonstration applied for an optically reconfigurable gate array. The configuration procedure could be executed by using the radiation-damaged holographic memory.

DOI： 10.1109/ICMAE.2016.7549569

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper presents experimentally obtained results demonstrating the radiation tolerance of a MEMS mirror device. The radiation tolerance was confirmed as 170 Mrad or higher total-ionizing dose tolerance.

DOI： 10.1109/OMN.2016.7565925

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Currently, microelectromechanical system (MEMS) spatial light modulators (SLMs) with numerous tiny mirrors that are controllable as a binary state are available. Such MEMS spatial light modulators are useful as holographic displays, optical tweezers, optical memories, reconfigurable lenses, etc. Although nonfault devices are always used for such applications, this paper clarifies that even if a part of a MEMS-SLM is faulty, the MEMS-SLM is useful for almost all commercial products related to the applications described above. Moreover, it is useful even as research equipment with a high degree of precision. This paper therefore presents the fault-tolerance analysis results of light intensity, contrast ratio, and spot size of interference pattern generated from a MEMS-SLM to clarify the allowable deteriorations of faulty MEMS-SLMs. Moreover, we propose a recovery method that a faulty MEMS-SLM can be used as a nonfaulty MEMS-SLM by exploiting excess laser power.

DOI： 10.1109/JLT.2015.2483622

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Currently, many consumer game machines are based on the operations of processors. However, in the field programmable gate array (FPGA) research field, various FPGA game solvers have been developed recently. The processing speeds of such FPGA game solvers can reach about 1000 times faster than processor-based operations. This paper explains the development of one such FPGA game solvers, the Blokus Duo FPGA solver, and presents discussion of how processors on game machines can be replaced with FPGAs in future consumer game machines.

DOI： 10.1109/ICCE.2016.7430678

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, radiation-hardened optoelectronic field programmable gate arrays (FPGAs) or optically reconfigurable gate arrays (ORGAs) have been under development. We propose a method of reconfiguration performance recovery for maintaining the gate array performance of ORGAs. We have experimentally demonstrated the recovery of the ORGA configuration speed merely by exploiting excess laser power.

DOI： 10.1109/VLSID.2016.67

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array is discussed for angle-multiplexing recording by controlling the laser interference exposure in LC composites. The successive laser illumination system to record the various configuration contexts at the specified region and angle in HPDLC memory is constructed by using the combination of a half-mirror and a photomask placed on the motorized stages under the control of a personal computer. The effect of laser exposure energy on the formation of holographic memory is investigated by measuring diffraction intensity as a function of exposure energy during the grating formation process and observing the internal grating structure by scanning electron microscopy. The optical reconfiguration in the gate-array VLSI is executed for configuration contexts of OR and NOR operations shown as logical operators that are reconstructed by laser irradiation at different incident angles for a specified region in the HPDLC memory. (C) 2015 Optical Society of America

DOI： 10.1364/AO.54.010623

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, static random access memory (SRAM)based field programmable gate arrays (FPGAs) are used for various systems. Since such SRAM-based FPGAs are programmable, their use over a long period must accommodate the use of a partly damaged programmable gate array. However, since current FPGAs use a serial configuration line for their configuration and the serial configuration circuit is invariably first broken circuit. Therefore, currently available FPGAs cannot accommodate the use of a partly damaged programmable gate array. However, if a partly damaged programmable gate array could be used, then the lifetime of VLSIs would be increased drastically. To extend the lifetime of programmable devices, FPGA should use a parallel configuration architecture instead of the serial configuration architecture of currently available FPGAs. This paper therefore clarifies the benefits of the parallel configuration architecture on an optically reconfigurable gate array (ORGA) VLSI using the designs of an ORGA-VLSI and a currently available serial-configuration FPGA.

DOI： 10.1109/SII.2015.7405083

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, to realize autonomous functions resembling those of humans on space systems, higher-performance embedded systems than those of current space systems are necessary for use in long-distance space missions. Currently, a parallel-operation-oriented optically reconfigurable gate array (ORGA) has been under development. The ORGA can support a nanosecond-order high-speed reconfiguration and high-density implementation of parallel operations. The parallel-operation-oriented ORGA has many programmable gate array layers, which share a common configuration context and increase the number of implementable parallel operations. Therefore, a parallel-operation-oriented ORGA is suitable for hardware acceleration of a software operation on a processor. However, in a space environment, triple modular redundancy (TMR) must be used. Single common configuration memory becomes a weak point for radiation in terms of redundancy. Therefore, we propose a TMR implementation method that is suitable for the parallel-operation-oriented ORGA.

DOI： 10.1109/ICARES.2015.7429829

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/icares.2015.7429832

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

For research related to field programmable gate arrays (FPGAs), various FPGA game solvers have been developed recently. The FPGA game solver can achieve up to 1,000 times faster processing speeds than processor-based operations. This paper presents one development of such FPGA game solvers: an FPGA Trax Solver based on a neural network design. The speed of the FPGA Trax Solver operations implemented on an FPGA (Arria II GX; Altera Corp.) is over 60 times greater than operation of C++ based software on a personal computer (Vostro 460; Dell Inc.).

DOI： 10.1109/FPT.2015.7393119

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, high-speed space optical communication requires real-time hardware operation instead of slow software operation on a processor. For such purposes, field programmable gate arrays (FPGAS) are extremely useful. In such hardware accelerations, a software algorithm is frequently implemented onto an FPGA as a parallel operation. However, in such implementations, many regions of the configuration memory on an FPGA must have common circuit information, but the overlap on the configuration memory can be regarded as wasteful implementation. Therefore, a parallel-operation-oriented FPGA has been proposed to implement parallel operations onto an FPGA efficiently. Such a parallel-operation-oriented FPGA has numerous programmable gate array layers sharing a common configuration context so that the overlap data on the configuration memory of an FPGA can be removed perfectly. However, in space environments, triple modular redundancy must always be used to remove soft errors and the single shared configuration architecture of the parallel-operation-oriented FPGA is the opposite way of such redundancy. To meet those demands, we propose a suitable implementation method of triple modular redundancy (TMR) onto the parallel-operation-oriented FPGA architecture.

DOI： 10.1109/ICSOS.2015.7425070

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, lasers are being used for space optical communications. However, in a space environment, space radiation is constantly incident to lasers. Therefore, the radiation tolerance analysis of lasers is an important characteristic that must be evaluated. As described in this report, we present radiation experiment results of a semiconductor laser array. This experiment measured the radiation tolerance of the laser array using a Cobalt 60 gamma radiation source. Results show that the laser array stands up to at least 100 Mrad total ionizing dose.

DOI： 10.1109/ICSOS.2015.7425076

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, since space satellites use image sensors and photodiode sensors, their radiation tolerance has become an important concern. In addition, some available space communication systems use a photodiode sensor for communications. However, since such sensors have an aperture without shielding, the total ionizing dose tolerance of the sensors becomes so weak that the radiation tolerance becomes lower than that of other embedded components. This paper therefore presents a proposal of a Fresnel lens radiation shield for use with photodiodes. A Fresnel lens can increase the light sensitivity and radiation tolerance of a photodiode.

DOI： 10.1109/ICSOS.2015.7425088

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The effect of laser exposure condition on the formation of holographic polymer-dispersed liquid crystal (HPDLC) memory by the angle-multiplexing recording is discussed. The successive laser illumination system to record the various configuration contexts at the different region and angle in HPDLC memory is constructed by controlling the laser interference exposure in liquid crystal (LC) composites and the optical equipment using the motorized stages.

DOI： 10.1109/MOC.2015.7416433

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) have been developed to realize radiation-hardened field programmable gate arrays (FPGAs). An ORGA consists of a laser array, a holographic memory, and a programmable gate array VLSI. Since the configuration of an ORGA is a parallel configuration, damage to a configuration circuit or a component does not affect configuration procedures on other configuration circuits. Therefore, even if almost all look-up tables (LUTs) malfunction because of radiation, the remaining functional LUTs can be programmed and used, whereas the serial configuration of FPGAs does not allow the use of a partly failed gate array. However, to achieve higher radiation tolerance of a programmable gate array than that of an FPGA in ORGA architecture, the radiation tolerances of a laser array and a holographic memory must be sufficiently higher than that of the part of a programmable gate array VLSI. Since the radiation tolerance of a holographic memory has already been confirmed as sufficiently higher than that of a programmable gate array VLSI, this paper presents a radiation tolerance investigation of a laser array on an optically reconfigurable gate array. Experiments using Co60 gamma radiation have demonstrated that a laser array has a greater than 20 Mrad total ionizing dose tolerance.

DOI： 10.1109/MOC.2015.7416484

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Recently, existing radiation-hardened static random access memory (SRAM)-based field programmable gate arrays (FPGAS) are anticipated for use in space radiation environments. Although such radiation-hardened SRAM-based FPGAS are programmable, the use of a radiation-damaged gate array has never been assessed for use with application-specific integrated circuits (ASICs) because its serial configuration is invariably damaged first by radiation so that the configuration itself becomes impossible. Therefore, currently available FPGA cannot be used in such faulty gate arrays used in space environments. However, if faulty programmable gate arrays are used, then the total ionizing dose tolerance of the programmable gate array would be increased even if its process technology were the same as that of conventional FPGAS. In this paper, in order to explore the possibility, we experimentally assessed the configuration circuit robust capabilities of a normal Cyclone II FPGA. Also, we examined the failure probability when using 1-bit, 2-bit, 4-bit, and 8-bit buses for the FPGA configuration using the designs of serially configured FPGAS.

DOI： 10.1109/ICSOS.2015.7425067

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 x 10(4) times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and highspeed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.09MA06

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array based on the angle-multiplexing recording is discussed by controlling the laser interference exposure in liquid crystal (LC) composites. The successive laser illumination system to record the various configuration contexts at the different region and angle in HPDLC memory is constructed by using the half mirror and photomask placed on the motorized stages under the control of a personal computer (PC). The effect of laser exposure energy on the formation of holographic memory is investigated by the measurement of diffraction intensity during the grating formation process. The reconstruction of configuration contexts for the various logical circuits is demonstrated by the laser illumination at different incident angle in the HPDLC memory.

DOI： 10.1109/CLEOPR.2015.7376567

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, field programmable gate arrays (FPGAs), which have become widely used for embedded systems, have also become anticipated for use in high-radiation environments such as space environments and nuclear power plants. Currently available radiation-hardened FPGAs can support scrubbing techniques, but such techniques entail the difficulty that radiation tolerance is insufficient for high-radiation environments. This paper therefore presents a holographic scrubbing technique for a programmable gate array. The scrubbing period can be less than 10 ns, so the robust ability of programmable gate arrays can be increased drastically. This paper presents theoretical analysis results and a demonstration of high-speed scrubbing on an optically reconfigurable gate array.

DOI： 10.1109/AHS.2015.7231161

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, studies of acceleration of software operations on a processor have been executed aggressively using Field Programmable Gate Arrays (FPGAs). However, currently available FPGA architecture presents waste under a parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous parts of configuration memory. This paper therefore presents a proposal for a parallel-operation-oriented FPGA architecture including a shared common configuration memory. In this research, a parallel-operation-oriented FPGA with four programmable gate arrays sharing a common configuration memory has been designed using a 0.18 mu m CMOS process technology. The advantage of the parallel-operation-oriented FPGA is clarified and a design technique to achieve a high-performance parallel-operation-oriented FPGA is discussed.

DOI： 10.1109/ISNE.2015.7132021

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, optically reconfigurable gate arrays (ORGAs) have been developed to offer numerous reconfiguration contexts with high-speed dynamic reconfiguration. Such ORGAs consist of a holographic memory, a laser array, and optically reconfigurable gate array VLSI. The storage capacity of a three-dimensional holographic memory is much higher than that of current two-dimensional memory technologies. Therefore, even Tera-gate-count circuit information can be stored on such a holographic memory. Moreover, high-speed reconfiguration can be realized by exploiting two-dimensional free optical connections between a holographic memory and a photodiode array on an optically reconfigurable gate array VLSI. Such high-speed dynamic reconfiguration can increase the gate array performance. Currently, we are trying to develop a high-density optically reconfigurable gate array VLSI. An important bottleneck is the limitation of light diffraction. This report presents a method of increasing the resolution of diffraction light for realizing a high-density optically reconfigurable gate array

DOI： 10.1109/ISNE.2015.7131967

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Springer Verlag  

Recently, optically reconfigurable gate arrays (ORGAs) have been developed as radiation-hardened field programmable gate arrays (FPGAs) to realize a 10 Mrad total ionizing dose-tolerance. Specifically, ORGAs offer important benefits of high-speed reconfiguration, numerous reconfiguration contexts, and robust configuration. These three factors are important to remove the soft-error of a configuration circuit on a programmable gate array and to increase the total ionizing dose tolerance. Although the robust configuration capability has been confirmed using radiation emulation, no actual radiation experiment has been reported to date in the relevant literature. This paper therefore presents experiments demonstrating the enhanced radiation tolerance of an optically reconfigurable gate array using a cobalt-60 gamma radiation source.

DOI： 10.1007/978-3-319-16214-0_35

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPRINGER-VERLAG BERLIN  

Recently, studies exploring acceleration of software operations on a processor have been undertaken aggressively using field programmable gate arrays (FPGAs). However, currently available FPGA architectures present waste occurring with parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous configuration memory parts. Therefore, a parallel-operation-oriented FPGA with a single shared configuration memory for some programmable gate arrays has been proposed. Here, the architecture is applied for optically reconfigurable gate arrays (ORGA). To date, the ORGA architecture has demonstrated that a high-speed dynamic reconfiguration capability can increase the performance of its programmable gate array drastically. Software operations can be accelerated using an ORGA. This paper therefore presents a proposal for combinational architecture of the parallel-operation oriented FPGA architecture and a high-speed reconfiguration ORGA. The architecture is called a parallel-operation-oriented ORGA architecture. For this study, a parallel-operation-oriented ORGA with four programmable gate arrays sharing a common configuration photodiode-array has been designed using 0.18 mu m CMOS process technology. This study clarified the benefits of the parallel-operation-oriented ORGA in comparison with an FPGA having the same gate array structure, produced using the same process technology.

DOI： 10.1007/978-3-319-16086-3_1

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, several varieties of image recognition systems using Fourier transform have been proposed. The salient benefit of using a Fourier transform is its position-independent image recognition capability. However, the operation of Fourier transform of high-resolution images is an extremely heavy operation. This paper therefore presents a proposal of image recognition systems using an optical Fourier transform on a dynamically reconfigurable vision architecture. This proposed system can recognize numerous images within an extremely short period using dynamic reconfiguration.

DOI： 10.1109/ISCAS.2014.6865438

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：ASSOC COMPUTING MACHINERY  

Optically reconfigurable gate arrays (ORGAs) have been developed to achieve a high-performance FPGA with numerous configuration contexts. In the architecture, an optical memory technology or a holographic memory technology has been introduced so that the architecture can have numerous configuration contexts and high-speed reconfiguration capability. Results show that the architecture can achieve a large virtual gate count that is much larger than those of currently available VLSIs. To date, ORGAs with a spatially multiplex holographic memory have been reported. However, the spatially multiplexed holographic memory can only have a small number of configuration contexts, which are limited to about 256 configuration contexts. To implement more than a million configuration contexts, an angle-multiplex holographic memory must be used. However, no ORGA with an angle multiplex holographic memory that can sufficiently exploit the huge storage capacity of a holographic memory has ever been reported. Therefore, this paper presents a proposal of a novel ORGA with an angle-multiplexed holographic memory. The architecture can open the possibility of providing a million configuration contexts for a multi-context FPGA.

DOI： 10.1145/2591513.2591597

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Currently, research of optically reconfigurable gate arrays (ORGAs), a type of multi-context field programmable gate arrays (FPGAs), has progressed rapidly. ORGAs offer important benefits of high-speed reconfiguration, numerous reconfiguration contexts, and robust configuration. Such ORGAs always consist of a single-wavelength laser array to address configuration contexts. However, for this architecture, concerns related to its package size often arise. The laser array is large because of the large space between lasers. For that reason, the ORGA also tends to be large. Therefore, we have introduced some wavelength lasers inside a laser array of an ORGA to decrease the laser array size. Results show that the ORGA package can be smaller. However, the dependability of color configuration has never been discussed up to now. This paper therefore presents a demonstration of the radiation tolerance of color configuration on an optically reconfigurable gate array.

DOI： 10.1109/IPDPSW.2014.27

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Springer Verlag  

To date, optically reconfigurable gate arrays (ORGAs) have been developed to realize highly dependable embedded systems. ORGAs present many beneficial capabilities beyond those of field programmable gate arrays (FPGAs): The most important is that an ORGA can be reconfigured using an error-included configuration context that has been damaged by high-energy charged particles. The radiation tolerance of an ORGA is extremely high. Moreover, if an inversion/ non-inversion implementation architecture is introduced to an ORGA, the configuration dependability of the ORGA for radiation can be increased drastically. This paper therefore presents a demonstration of the enhanced radiation tolerance of an optically reconfigurable gate array achieved by exploiting the inversion/ non-inversion implementation. © 2014 Springer International Publishing Switzerland.

DOI： 10.1007/978-3-319-05960-0_14

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPIE  

DOI： 10.1117/12.2038024

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Currently, three-dimensional VLSI technologies are being developed. However, by increasing the number of layers of TSV or stacking layers, the production difficulty of VLSI is increased. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to realize high-speed dynamic reconfiguration. The ORGA consists of a holographic memory, a programmable gate array, and a laser array. An ORGA can store large amounts of circuit information inside a holographic memory. The circuit information can be programmed dynamically onto an ORGA's programmable gate array in nanosecondorder. The ORGA allows high-speed dynamic reconfiguration. If the high-speed dynamic reconfiguration can be used for the implementation of processors, then the processor performance can be increased. The implementation technique is called a mono-instruction set computer (MISC) architecture. This paper presents a demonstration result of a high-performance MISC architecture that fully exploits the high-speed programmability of an ORGA.

DOI： 10.1109/EDAPS.2013.6724417

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demand for programmable devices for space applications is increasing day-by-day to support hardware repair functions, hardware update functions, and hardware acceleration for space systems. An optically reconfigurable gate array (ORGA) has been developed as a robust multi-context field programmable gate array that is quite suitable for such space applications. The ORGA can be reconfigured using corrupt configuration data with nanosecond-order reconfiguration speed. Currently, we also propose a mono-instruction set computer architecture exploiting the high-speed dynamic reconfiguration. Using the mono-instruction set computer architecture, many-module redundancy over triple module redundancy (TMR) can be realized. This paper presents one demonstration result of a mono-instruction set computer and its robust capabilities.

DOI： 10.1109/EDAPS.2013.6724416

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper presents a proposal of a color configuration method for an optically reconfigurable gate array (ORGA). A conventional ORGA consists of a single-wavelength laser array to address configuration contexts. However, the new ORGA has lasers of some other wavelength inside a laser array. Consequently, the addressable number of configuration contexts can be increased.

DOI： 10.1109/FPT.2013.6718400

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

DOI： 10.1109/FPT.2013.6718426

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, optically reconfigurable gate arrays (ORGAs), which can support a high-speed dynamic reconfiguration with numerous reconfiguration contexts, have been developed. Although an ORGA is a three-dimensional VLSI, no through-silicon via (TSV) technology or any micro-bump technology is never necessary to produce an ORGA. A three-dimensional ORGA uses only free-optical connections and a volume-type holographic memory technology. Therefore, the yield ratio of ORGAs is so high that ORGAs can easily be produced with no concern related to production variation. In this study, to increase the gate density, a short wavelength laser of 404 nm is applied to ORGA architecture. This paper presents the reconfiguration capabilities of the reconfiguration period and retention time of the photodiode memory architecture of a newly fabricated ORGA-VLSI. © 2013 IEEE.

DOI： 10.1109/ICP.2013.6687090

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using successive laser exposures in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The configuration contexts corresponding to the various logical circuits are reconstructed by the laser illumination at different incident angle in the HPDLC memory.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Grating devices using photosensitive organic materials play an important role in the development of optical and optoelectronic systems. High diffraction efficiency and polarization dependence achieved in a holographic polymer-dispersed liquid crystal (HPDLC) grating are expected to provide polarization-controllable optical devices, such as a holographic memory for optically reconfigurable gate arrays (ORGAs). However, the optical property is affected by the thermal modulation around the transition temperature (T-ni) where the liquid crystal (LC) changes from nematic to isotropic phases. The temperature dependence of the diffraction efficiency in HPDLC grating is investigated using four types of LC composites comprised of LCs and monomers having different physical properties such as T-ni and anisotropic refractive indices. The holographic memory formed by the LC with low anisotropic refractive index and LC diacrylate monomer implements optical reconfiguration for ORGAs at a high temperature beyond T-ni of LC. (c) 2013 Optical Society of America

DOI： 10.1364/AO.52.006529

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

DOI： 10.1109/FPL.2013.6645603

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

Optically reconfigurable gate arrays (ORGAs) have been developed as high-speed reconfigurable fine grained gate arrays that can accommodate implementation of a multi-soft-core processor. An ORGA's programmable gate array can be reconfigured in nanosecond-order with one of more than 256 reconfiguration contexts. Its high-speed dynamic reconfiguration capability is suitable for dynamically changing the functions of a multi-core processor. In addition to that beneficial feature, ORGAs have high dependability against space radiation since the ORGA can be reconfigured with an error-included configuration context. In this paper, while maintaining its highly dependable capability, a more advanced dependability-increasing technique using a negative logic implementation is proposed. The dependability of data on a holographic memory depends on the number of bright bits or the binary state H included in a configuration context. If the number of bright bits in a configuration context can be decreased, then the configuration dependability can also be increased. The proposed optical configuration dependability-increasing technique of a negative logic implementation can decrease the number of bright bits in a configuration context. This technique can raise the ORGA's configuration dependability level even further. This paper describes an experimental demonstration of the usefulness of the proposed technique. © 2013 IEEE.

DOI： 10.1109/MCSoC.2013.33

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To date, optically reconfigurable gate arrays (OR-GAs) consisting of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI have been developed to realize fast reconfiguration and numerous reconfiguration contexts. Numerous configuration contexts can be stored on a holographic memory and can be programmed dynamically onto a gate array in a nanosecond-order period. Such highspeed dynamic reconfiguration enables a large virtual gate over a physical gate, for example a 1 Tera-gate VLSI. However, in addition to the advantages, the ORGA architecture allows high-speed optical Fourier transformation by addition of a programmable Fresnel lens. This paper presents a proposal of a new ORGA architecture to support Fourier transformation and results of its demonstration.

DOI： 10.1109/MWSCAS.2013.6674618

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We have been developing Optically Reconfigurable Gate Arrays (ORGAs) with higher radiation tolerance than that of a Field Programmable Gate Array (FPGA). The ORGA configuration is extremely robust against radiation. Moreover, that radiation tolerance of ORGA's programmable gate array can be increased by exploiting the advantageous high-speed dynamic reconfiguration of an ORGA. Although an ORGA has such a radiation-tolerance benefit, a lot of lasers that are necessary for addressing a holographic memory present concerns related to cost. Therefore, MEMS technology was introduced to reduce the number of lasers. Using a novel interleaving method, the reconfiguration speed is maintained as 10 ns: 1000 lasers and 1,000,000 MEMS mirrors can address one million configuration contexts. This paper presents a proposal of more advanced technique by which one mirror can address four configuration contexts by controlling the mirror angle. Although MEMS mirrors are not expensive, the proposed method contributes to the miniaturization of an ORGA package and to weight reduction. © 2013 IEEE.

DOI： 10.1109/AHS.2013.6604242

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/cleopr.2013.6600439

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array with more than 100 reconfiguration contexts can be reconfigured in nanosecondorder. In addition to that beneficial feature, ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment. Even if 35 % or 5,915 pixels of holographic memory data are damaged by high-energy charged particles, the ORGA can execute configuration operations correctly. Therefore, ORGAs are sufficiently robust devices for use in spaceradiation environments. This paper presents a proposal of a more advanced dependability-increasing technique on a multicontext ORGA. This technique can raise the ORGA's level of configuration dependability even further by exploiting multicontext implementation.

DOI： 10.1109/ISCAS.2013.6572159

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ISCAS.2013.6572133

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

Grating devices using photosensitive organic materials play an important role in the development of optical and optoelectronic systems. High diffraction efficiency and polarization dependence achieved in a holographic polymerdispersed liquid crystal (HPDLC) grating are expected to provide polarization controllable optical devices, such as the holographic memory for optically reconfigurable gate arrays (ORGAs). However, the optical property is affected by the thermal modulation around the transition temperature (T ni) that the liquid crystal (LC) changes from nematic to isotropic phases. The temperature dependence of the diffraction efficiency in HPDLC grating is discussed with two types of LC composites comprised of isotropic and LC diacrylate monomers. The holographic memory formed by the LC and LC diacrylate monomer performs precise reconstruction of the context information for ORGAs at high temperatures more than 150°C. © 2013 Optical Society of America.

DOI： 10.1364/OL.38.001158

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OSA - The Optical Society  

This paper presents a proposal of an optical configuration acceleration method applied to optically reconfigurable gate arrays (ORGAs) using a negative logic implementation. The gate array of an ORGA is reconfigured using a holographic memory. The reading time of a holographic memory depends on the number of bright bits included in a configuration context. The proposed optical configuration acceleration method can decrease the number of bright bits. As a result, the proposed optical configuration acceleration method can increase the reconfiguration frequency. In this paper, a fabricated ORGA very large scale integration that can support the optical configuration acceleration method is estimated. Consequently, this paper shows that the reconfiguration frequency of the proposed method is 1.97 times higher than those of conventional ORGA architectures with no increase of laser power. © 2013 Optical Society of America.

DOI： 10.1364/AO.52.001939

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Optically reconfigurable gate arrays (ORGAs) can be reconfigured using error-inclusive configuration contexts under a radiation-rich space environment. Therefore, the ORGA presents an important benefit: the allowable amount of configuration data damage is greater than that by field programmable gate arrays (FPGAs) with error-checking and correction. However, the ORGA's programmable gate array itself is never as robust against space radiation as that of an application-specific integrated circuit (ASIC) because the programmable architecture of its gate array is the same as that of FPGAs. Therefore, to achieve a drastic increase in the robust capability of a fine-grained programmable gate array on an ORGA-VLSI, this paper presents a proposal of a novel dynamic module multiple redundancy scheme based on a mono-instruction set computer architecture exploiting high-speed dynamic reconfiguration. © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-36812-7_21

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：一般社団法人電子情報通信学会  

我々は現在,レーザアレイ,ホログラムメモリ,ゲートアレイVLSIから構成され,光による高速動的再構成が可能な光再構成型ゲートアレイを研究開発している.光再構成型ゲートアレイの特徴として,高速動的再構成と大規模なコンテキスト情報数の記憶が挙げられる.しかし,これまで光再構成型ゲートアレイは構造上,コンテキスト情報数に応じてレーザが必要なので,既存のプログラマブルデバイスと比較して価格が高くなるという問題点があった.そこで我々は,偏光依存性ホログラムメモリを用いることにより,レーザ数を削減できる光再構成型ゲートアレイのアーキテクチャを考案した.本稿では,偏光依存性ホログラムメモリを用いた9コンテキスト光再構成型ゲートアレイの試作結果について報告する.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

As gates in field programmable gate arrays (FPGAs) become usable in ever-increasing numbers, FPGAs are becoming more widely applied in various embedded systems. FPGAs have been demonstrated as useful renewable devices. Recently however, a hard-core processor inside an FPGA is frequently used for high-performance systems so that the implementation of the hard-core processor decreases the possibility of a specification change and reuse of its FPGA. Therefore, demand for implementing a soft-core processor onto an FPGA is gaining. In response to that demand, FPGA vendors have provided soft-core processors for FPGAs, but those processors invariably provide lower performance than hard-core processors do. Therefore, this paper presents high-performance mono-instruction set computer (MISC) architecture that fully exploits the programmability of a dynamically reconfigurable fine-grained gate array. In addition, this paper presents a proposal of a uniform partitioning method for the MISC architecture. © 2012 IEEE.

DOI： 10.1109/NBiS.2012.107

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To date, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present advantageous capabilities compared with other ORGAs: they have increased the reconfiguration frequency per unit of laser power and have reduced optical configuration power consumption. On the other hand, dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density, but an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical configuration power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array has been developed, adopting only the best attributes from both architectures. This paper presents an inversion/non-inversion implementation for a newly fabricated 0.18 mu m CMOS process optically reconfigurable gate array VLSI.

DOI： 10.1109/MWSCAS.2012.6291971

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Currently, demand is increasing for high-speed dynamic reconfiguration on programmable devices to improve their performance. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been undergoing rapid development. Moreover, to more increase the reconfiguration speed, optically differential reconfigurable gate arrays (ODRGAs) incorporating a differential reconfiguration method between configuration contexts have been developed. An ODRGA comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Its large-bandwidth optical connection enables high-speed reconfiguration. However, photodiode sensitivities of conventional ODRGAs are not good. This paper therefore presents a newly fabricated 0.18 mu m CMOS process optically differential reconfigurable gate array VLSI chip with highly sensitive photo-circuits.

DOI： 10.1109/ISVLSI.2012.71

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand is increasing daily for a robust VLSI chip that is useful in a radiation-rich environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a radiation-tolerant Field Programmable Gate Array (FPGA). The ORGA architecture is extremely robust against multi-event upsets. Moreover, it can recover from permanent errors resulting from a heavy total radiation dose. This paper presents demonstration results of a 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed-adjustment function. © 2012 IEEE.

DOI： 10.1109/FPL.2012.6339205

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Holographic polymer dispersed liquid crystal (HPDLC) memory is fabricated by a photoinduced phase separation comprised of polymer and liquid crystal (LC) phases using laser light interference exposures. The anisotropic diffraction induced by the alignment of LC in the periodic structure of the HPDLC memory is applied to reconstruct the configuration contexts for the optically reconfigurable gate arrays. Optical reconfiguration for various circuits under parallel programmability is implemented by switching the polarization state of incident light on the HPDLC memory using a spatial light modulator. (C) 2012 Optical Society of America

DOI： 10.1364/AO.51.005168

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSls. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, in contrast to current field-programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: alignment errors arise when a programmable ORGA is recorded with a writer system. When programming a programmable ORGA along with alignment errors between the programmable ORGA and its writer system, the reconfiguration speed of the programmable ORGA is decreased. This paper therefore presents a detection and compensation method of alignment errors between a programmable ORGA and a writer system to alleviate that shortcoming.

DOI： 10.1109/NAECON.2012.6531052

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, fiber networks and undersea fiber optic cables have become widely used throughout the world. Because of its much lower attenuation and interference, optical fiber is superior to copper wire for long-distance applications. Optical fiber data transfer rates and distances reach GHz-order and over 100 km. Previously, a remote configurable field programmable gate array (FPGA) system using current fiber networks was reported. However, since its configuration speed was very low, dynamic high-speed reconfiguration was impossible. Therefore, this paper presents a 4-configuration context fiber-linked optically reconfigurable gate array using a bundle of fiber networks and an optically reconfigurable gate array. © 2012 IEEE.

DOI： 10.1109/OECC.2012.6276587

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand is increasing daily for a large-gate-count robust VLSI chip that is useful in a radiation-rich space environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. © 2012 IEEE.

DOI： 10.1109/AHS.2012.6268635

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) with an amplitude-modulation type holographic memory have been developed as a type of multi-context field programmable gate array. The ORGA's programmable gate array can be reconfigured in nanosecond-order, with more than 100 reconfiguration contexts. However, the diffraction efficiency of the amplitude-modulation type holographic memory is not good because the holographic memory decreases its transmission light intensity depending on the modulation level. About half of the power of the laser is consumed by the holographic memory. Therefore, this paper presents a high-speed - low-power optical configuration capability of an ORGA with a phase-modulation type holographic memory.

DOI： 10.1109/IPDPSW.2012.28

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand is increasing daily for a robust field programmable gate array that is useful for operations performed in a radiation-rich space environment, such as those of spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) are under development as robust field programmable gate arrays. Their holographic memories can generate correct configuration contexts at any time, even if up to 20 % of the holographic memory data are damaged. However, up to now, a soft error effect for a laser array on ORGA devices has never been discussed. Therefore, this paper first presents a proposal of a method to find an unexpected configuration procedure caused by a laser array driver circuit facing a soft error on conventional ORGA architectures and to recover from such a procedure. Then this paper presents a proposal of a new robust laser array driver circuit that is applicable for any ORGA architecture, which can perfectly remove the unexpected configuration procedure itself. © 2012 Springer-Verlag.

DOI： 10.1007/978-3-642-28365-9_14

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：ALIFE ROBOTICS CO, LTD  

Optically reconfigurable gate arrays (ORGAs) consisting of a holographic memory, a laser diode array, and a programmable gate array were developed to realize an artificial brain system for robots. In the ORGA, much information or many reconfiguration contexts can be stored in a volume-type holographic memory and can be programmed dynamically onto a programmable gate array at nanosecond-order perfectly in parallel. Therefore, by exploiting the huge storage capacity of the holographic memory and large parallel operations on a programmable gate array, huge parallel brain operations can be executed quickly on an ORGA. This paper presents a proposal of a binary MEMS-interleaving reconfiguration operation on an optically reconfigurable gate array for an artificial brain system.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, for fse in aftonomofs vehicles and robots, demand has been increasing for high-speed image recognition that is sfperior to that of the hfman eye. However, to recognize nfmerofs images qfickly, sfch system reqfires many template images to be read oft dynamically from memory. They mfst then be sent to a processor qfickly. Realizing sfch high-speed real-time image recognition operation is difficflt becafse of the bottleneck of transfer speed between the memory and the processor. Therefore, to improve the bottleneck, a dynamically reconfigfrable vision architectfre that can recognize binarized images has been presented. However, to date, no dynamically reconfigfrable vision architectfre that can recognize gray-level images has ever been presented. Therefore, this paper presents experimentation related to a more advanced dynamically reconfigfrable vision architectfre that can recognize gray-level images. © 2012 IEEE.

DOI： 10.1109/SOCC.2012.6398381

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Holographic polymer-dispersed liquid crystal (HPDLC) memory formed by a subwavelength grating (SWG) mask is presented for new optical information processing. The SWG structure in a photomask is formed on the SiO2 plate using the anisotropic reactive ion etching technique. The configuration contexts for optically reconfigurable gate arrays (ORGAs) are stored in the HPDLC memory by polarization modulation property based on the form birefringence of the SWGplate. The configuration context pattern in the HPDLC memory is reconstructed to write it for the ORGAs under parallel programmability. (C) 2011 Optical Society of America

DOI： 10.1364/AO.50.006369

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, immediately following invention of a Connect6 game, many game programs were developed aggressively. However, because the solution space of the Connect6 game is extremely large, the computation powers of current computers are quite insufficient to search all possible solutions. This paper therefore presents a proposal of a field programmable gate array (FPGA) Connect6 Solver with a two-stage pipelined evaluation exploiting numerous zero-evaluation functions to evaluate only a zero value and a small number of detailed evaluation functions which can evaluate all range. The FPGA Connect6 Solver implemented onto a Cyclone IV FPGA is able to defeat target software provided by the 2011 International Conference on Field-Programmable Technology (ICFPT) within the time limit of 1 s for each turn. In addition, the FPGA Connect6 Solver can defeat another JAVA-based software program with a similar algorithm. At that time, the operation speed of the FPGA Connect6 Solver is 764.2 times higher than that of the software operating on a personal computer (Vostro 220S
Dell Inc.) with a 3.16 GHz, Core 2 Duo processor (Intel Corp.). © 2011 IEEE.

DOI： 10.1109/FPT.2011.6133249

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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DOI： 10.1364/AO.50.006369

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Demand is increasing daily for large data storage systems that are useful for applications in spacecraft, space satellites, and space robots, which are all exposed to radiation-rich space environment. As candidates for use in space embedded systems, holographic storage systems are promising because they can easily provided the demanded large-storage capability. Particularly, holographic storage systems, which have no rotation mechanism, are demanded because they are virtually maintenance-free. Although a holographic memory itself is an extremely robust device even in a space radiation environment, its associated lasers and drive circuit devices are vulnerable. Such vulnerabilities sometimes engendered severe problems that prevent reading of all contents of the holographic memory, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal for a recovery method for the turn-off failure mode of a laser array on a holographic storage system, and describes results of an experimental demonstration. (C) 2011 Optical Society of America

DOI： 10.1364/OE.19.024147

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ISOCC.2011.6138757

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array can be reconfigured at nanosecond-order, with more than 100 reconfiguration contexts. In addition to that beneficial feature, since ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment, ORGAs are suitable for space applications. The robust capability of ORGAs with an amplitude modulation type holographic memory has already been demonstrated, but an ORGA with a phase-modulation type holographic memory that can achieve more robust capability has never been reported. Therefore, this paper presents a proposal of a new dependable ORGA architecture based on a phase-modulation type of holographic memory. In addition, this paper describes experimental clarification through a demonstration that the dependable ORGA is more robust than conventional ORGAs with an amplitude modulation type holographic memory. © 2011 IEEE .

DOI： 10.1109/FPL.2011.17

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper presents a proposal for a four-context programmable optically reconfigurable gate array (PORGA) with a high-resolution reflective silver-halide holographic memory and a corresponding writer system. The PORGA demonstrates the capability of 4.6-11.5-mu s high-speed configuration context switching among four configuration contexts, which is 1000 times faster than that of conventional field programmable gate arrays (FPGAs).

DOI： 10.1109/JPHOT.2011.2160335

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記述言語：英語  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of high-fault-tolerance multi-context field programmable gate array for space applications under radiation-rich environments. However, although many configuration contexts can be stored on an ORGA device and can be implemented on its gate array dynamically in an extremely short time, several laser sources are necessary to address the configuration contexts. Since such lasers are always expensive and because such devices are easily damaged by surge current, reducing the number of lasers is an important factor. Therefore, this paper presents a proposal of a new optically reconfigurable gate array with a polymer-dispersed liquid crystal holographic memory. Under the ORGA, all configuration contexts can be addressed by half the number of lasers as there are reconfiguration contexts. This paper presents demonstration results of the optically re-configurable gate array obtained using a polymer-dispersed liquid crystal holographic memory. © 2011 IEEE.

DOI： 10.1109/AHS.2011.5963965

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, high-speed image recognition functionality that is superior to the image recognition speed of the human eye is demanded for autonomous vehicles and robots. Currently, such embedded systems comprise a processor and memory. To recognize many images, many template images must be stored in memory and must be sent quickly from memory to the processor. For example, assuming that the system receives an external image with 1 million pixels at every 1 ms and assuming that the system must execute template-matching operations of 1 million template images with the same million pixels within 1 ms, then the transfer speed from the memory to the processor and the processor operation reaches 1 Petapixel/s. Therefore, to realize high-speed template-matching operation, a dynamically reconfigurable vision-chip architecture with a holographic memory and large-bandwidth optical connections has been proposed. Among such researches, this paper presents a proposal of novel parallel template-matching operations performed on the dynamically reconfigurable vision-chip architecture. Furthermore, the advantages of the new method are discussed based on some demonstration results. © 2011 IEEE.

DOI： 10.1109/NEWCAS.2011.5981291

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand is increasing daily for a robust VLSI chip that is useful for operating under a radiation-rich space environment, such as spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. This paper presents a robust 16-laser array for an optically reconfigurable gate array and its demonstration results. © 2011 IEEE.

DOI： 10.1109/ICSOS.2011.5783679

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

An optically reconfigurable gate array (ORGA) was developed recently as one multi-context device to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers, but such lasers increase the ORGA power consumption and package size. In some cases, they might even require a cooling system. For that reason, this paper presents a configuration speed acceleration method for a sequential circuit using a negative logic implementation without ORGA architecture modification and without any increase of laser power. Based on experimentally obtained results, this paper clarifies the acceleration method's effectiveness. © 2011 IEEE.

DOI： 10.1109/ICSOS.2011.5783670

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：ASSOC COMPUTING MACHINERY  

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

DOI： 10.1145/1968502.1968506

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPRINGER-VERLAG BERLIN  

Optically reconfigurable gate array (ORGAs) were developed to realize next-generation large-virtual gate count programmable VLSIs. An ORGA consists of an ORGA-VLSI, a holographic memory, and a laser array, which is used for addressing the holographic memory. Since many configuration contexts can be stored on a volume-type holographic memory, the corresponding number of lasers must he implemented on an ORGA. However, a laser array with numerous lasers is always expensive. Therefore, to accommodate numerous configuration contexts with fewer lasers, this paper presents a novel method using an interleaving read operation of a holographic memory for ORGAs. This method can provide an addressing capability of a billion configuration contexts along with a nanosecond-order high-speed configuration capability.

DOI： 10.1007/978-3-642-19475-7_25

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demand for space uses of FPGAs is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. However, under a space radiation environment, the incidence of high-energy charged particles causes single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 144-configuration context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment.

DOI： 10.1109/SOCC.2011.6085083

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demand for use of FPGAs in space is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. Under a space radiation environment, embedded devices must allow for incidence of high-energy charged particles. Such incidence can cause single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 64-context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment. © 2010 IEEE.

DOI： 10.1109/FPT.2010.5681467

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：ELSEVIER SCIENCE BV  

A function enabling remote programming is necessary for systems used with nuclear power plants, high-energy physics experiments, and other plants with no personnel Recently, optically reconfigurable gate array (ORGA) architecture has been developed to achieve a huge virtual gate count that is much greater than those of currently available VLSIs However, ORGA architectures have never supported a remote programming capability since a complicated holographic writer system is required along with an ORGA for that purpose. This paper therefore presents a proposal of a new remotely reconfigurable gate array architecture with four configuration contexts that enable remote reconfiguration using optical fiber networks Furthermore, this paper presents discussion of the availability of this architecture and plans based on the experimental results (C) 2010 Elsevier B V All rights reserved

DOI： 10.1016/j.optcom.2010.06.090

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DOI： 10.1364/AO.49.006986

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 mu m three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 mu s partial reconfiguration. (C) 2010 Optical Society of America

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, as one dynamic reconfigurable device, optically reconfigurable gate arrays (ORGAs) that consist of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve greater than 1 Teragate virtual integration, which is much greater than the integration that is possible using currently available VLSIs. If the ORGA can be used, a large software system can be implemented directly as hardware so that a large real-time system can be realized. Currently, a programmable ORGA architecture has been proposed to support user programmability. This paper presents the demonstration result of a multi-context programmable ORGA using a silver-halide non-volatile holographic memory and a corresponding writer system. ©2010 IEEE.

DOI： 10.1109/SII.2010.5708364

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchronous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results. © 2010 IEEE.

DOI： 10.1109/FPT.2010.5681470

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, demands for implementation of a high-speed image recognition function onto autonomous vehicles and robots, that is superior to that of the human eye, have been increasing. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, realizing such high-speed real-time image recognition operation is extremely difficult because the template information transfer rate and template matching operation cycle reach the order of Petapixel/s. Therefore, to accommodate template matching operations that can be executed at rates greater than Petapixel/s, a dynamically reconfigurable vision-chip architecture has been developed in which a holographic memory technique is introduced to current VLSI technology. However, the dynamically reconfigurable vision-chip architecture must receive image information in addition to configuration context information. At such a time, a salient concern is that image information light might reduce the retention time of photodiode memories on a dynamically reconfigurable vision-chip. This paper therefore clarifies that the background light does not affect the photodiode memories on a dynamically reconfigurable vision-chip architecture. ©2010 IEEE.

DOI： 10.1109/SII.2010.5708363

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To date, optically reconfigurable gate arrays (ORGAs) have been developed to address high-speed operations. During that development, a MEMS dynamic optically reconfigurable gate array architecture was proposed: it perfectly removes the static configuration memory to store a context and uses junction capacitances of photodiodes as dynamic configuration memory to realize high-gate count ORGA-VLSI. However, this architecture presents the issue that retention time of programmed circuits on a gate array is, just like DRAMs, not infinite. Since the circuit reconfiguration frequency is always superior to the refresh cycle frequency, the refresh cycle problem need not be considered. However, circuits with a long lifetime exist among the many implementation circuits. For these circuits, many refresh cycles must be required continuously. Therefore, This paper presents a proposal of a retention time improvement method by adjusting the threshold level in the holographic memory calculation. ©2010 IEEE.

DOI： 10.1109/MHS.2010.5669547

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, fiber networks and undersea fiber optic cables have become widely used throughout the world. Because of its much lower attenuation and interference, optical fiber is superior to copper wires for long-distance applications. Such fibers' transfer rates and distances reach GHz-order and over 100 km. Up to now, a remote configurable FPGA system using current fiber networks was reported. However, since its configuration speed was very low, dynamic highspeed reconfiguration was impossible. This paper therefore presents a high-speed remote reconfiguration experiment using a bundle of fiber networks and an optically reconfigurable gate array. Such architecture presents the possibility of a remote high-speed dynamic reconfigurable hardware system.

DOI： 10.1109/TENCON.2010.5686374

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper experimentally presents a template matching operations on a dynamically reconfigurable vision-chip architecture. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665152

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demand is increasing daily for large storage systems that are useful for devices operating under a radiation-rich space environment, such as spacecraft, space satellites, and space robots. A holographic storage system, which can easily provide large storage capacity, is a candidate for space embedded systems. The holographic storage system, which requires no rotation mechanism, usually consists of a holographic memory material, a laser array, and a photodiode array. Although a holographic memory itself is an extremely robust device for use in a space radiation environment, its associated components are vulnerable to radiation. Such vulnerable devices can cause severe problems by preventing the reading of all holographic memory contents. This is a turn-off failure mode of a laser array. This paper therefore presents a recovery method for a turn-off failure mode of a laser array on a holographic storage system and presents results of its demonstration. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665158

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Demand is increasing daily for a large-gate-count robust VLSI chip that can be used in a radiation-rich space environment. Since they exploit the large storage capacity of a holographic memory, optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a recovery method for a turn-off failure mode of a laser array on a DORGA and its demonstration results.

DOI： 10.1109/DFT.2010.55

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Optically reconfigurable gate arrays (ORGAs) have been developed to realize large virtual gates and to increase gate array performance. Since the performance of gate arrays in dynamically reconfigurable gate arrays can be increased as increasing its reconfiguration clock frequency, a high-speed reconfiguration capability is extremely important. However, the efficiency of a conventional optical configuration is not good because the optical configuration speed suffers from the photodiode characteristic variation, optical component variation, alignment errors, and holographic memory properties. This paper therefore presents a proposal of a compensation method using an analog configuration context that can improve the optical configuration efficiency. Based on the experimental results, this paper presents a discussion of its performance. © 2010 IEEE.

DOI： 10.1109/SOCC.2010.5784753

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper presents a proposal of a novel optically reconfigurable gate array architecture with a microelectromechanical system (MEMS) mirror array that allows high-speed reconfiguration by exploiting large-bandwidth optical connections between the MEMS mirror array and a programmable gate array. The MEMS mirror array is used as a holographic memory. Four configuration contexts can be programmed electrically and dynamically onto the MEMS mirror array as holographic memory information. The configuration procedure is executed by switching both a laser array and an MEMS mirror array. This experiment demonstrated a four-context 146 ns microelectromechanical configuration for a programmable gate array. Submicrosecond configuration is attainable.

DOI： 10.1109/JQE.2010.2047378

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Field Programmable Gate Arrays (FPGAs) have been used widely in recent years because of their flexible reconfiguration capabilities. Moreover, demand of high-speed reconfiguration for FPGAs has been increasing. However, since reconfiguration of FPGAs cannot be increased because of the serial transfer of configuration data, new optically reconfigurable gate arrays (ORGAs) have been proposed as an alternative device to achieve high-speed reconfiguration and numerous reconfiguration contexts. However, in the ORGAs, alignment errors affect the configuration power consumption. This paper presents the relation between alignment errors of optical components and power consumption in optoelectronic devices. ©2010 IEEE.

DOI： 10.1109/CPMTSYMPJ.2010.5680217

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

This paper proposes a method of superimposing acceleration and optimizing the optical reconfiguration speed while requiring no increase of laser power. Using this technique, the optical reconfiguration speed is increased by superimposing multiple configuration contexts. Simultaneously, optimization of the number of configuration contexts and reconfiguration speed is possible. A full four-context optically reconfigurable gate array system consisting of an optically reconfigurable gate array VLSI, an easily rewritable liquid crystal holographic memory, and four vertical-cavity surface-emitting lasers was constructed to demonstrate this method. This paper clarifies the method's benefits using experimental results obtained from the demonstration system. (C) 2010 Optical Society of America

DOI： 10.1364/AO.49.004120

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記述言語：英語  

DOI： 10.1364/AO.49.004255

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DOI： 10.1364/AO.49.004120

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Holographic polymer-dispersed liquid-crystal (HPDLC) memory using liquid-crystal composites is proposed for new optical information processing. Formation of HPDLC memory using a photomask is discussed for parallel programmability to realize fast reconfiguration of optically reconfigurable gate arrays (ORGAs). The defect tolerance of HPDLC memory is investigated to clarify the defect limitation of holographic configurations using ORGAs. Experimental results show that the noise ratio less than 15% applied to HPDLC memory rarely affects its diffraction pattern or a reconfiguration context. (C) 2010 Optical Society of America

DOI： 10.1364/AO.49.004255

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. However, comparison of conventional ORGAs with current field programmable gate arrays (FPGAs) reveals one important shortcoming: they are not reprogrammable after fabrication. To remove that shortcoming, a programmable ORGA (PORGA) has been proposed. However, a PORGA must implement a window to detect holographic memory patterns. A PORGA window might have scratches, fingerprints, or other defects that could occur while a PORGA is used. Even under such situations, a PORGA must be programmable. This paper therefore presents influence analysis of a holographic memory window of a PORGA. It has been demonstrated that even if a window of PORGA has scratches, fingerprint, or defects, a programming procedure can be executed correctly.

DOI： 10.1109/MWSCAS.2010.5548776

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

(Figure Presented) This paper presents a four-context MEMS optically differential reconfigurable gate array that is useful in a space radiation environment. The technique enables rapid recovery of a programmable device that has been damaged by high-energy charged particles. It can use incorrect configuration data including some error bits resulting from damage by particles. This paper also clarifies the fault tolerance of the MEMS optically differential reconfigurable gate array. ©2010 IEEE.

DOI： 10.1109/OMEMS.2010.5672149

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported. © 2010 IEEE.

DOI： 10.1109/FPL.2010.101

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand for high-speed dynamic reconfiguration for programmable devices has increased since such fast dynamic reconfiguration can increase the programmable gate array performance. To meet that demand, optically reconfigurable gate arrays (ORGAs) have been developed to achieve the fast dynamic reconfiguration. Among such studies, a MEMS ORGA has been developed. The reconfiguration can be executed not only by switching a laser array but also by switching a holographic memory. The first proposed MEMS ORGA took an analog fringe pattern for generating a configuration context, although the MEMS device is a binary spatial light modulator. The switching capability can therefore not be fully exploited from a MEMS device since a MEMS device requires PWM control for generating an analog fringe pattern. This paper presents a novel binary MEMS ORGA. The binary MEMS ORGA has achieved a 312 ns laser-reconfiguration and 22 μs holographic memory switching. © 2010 IEEE.

DOI： 10.1109/ICIS.2010.89

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper presents a new programmable optically reconfigurable gate array using a silver-halide non-volatile holographic memory and its writer system. This device achieves high-speed reconfiguration, numerous reconfiguration contexts and user programmability.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand for a large-gate-count robust VLSI chip that is usable in a radiation-rich space environment is increasing daily. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. However, the ORGA has only an unallowable failure mode, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal of a recovery method for a turn-off failure mode of a laser array on an ORGA and presents its demonstration results. © 2010 IEEE.

DOI： 10.1109/AHS.2010.5546252

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Optically reconfigurable gate arrays (ORGAs) consisting of a holographic memory, a laser array, and a programmable gate array have been developed to realize large virtual gates and to increase a gate array's performance. To date, all ORGAs used binary values for optically applied configuration contexts. However, the energy efficiency is not good. Therefore, this paper presents a novel acceleration method of optical reconfigurations using analog configuration contexts. © 2010 IEEE.

DOI： 10.1109/AHS.2010.5546242

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To date, optically reconfigurable gate arrays (ORGAs) have been developed to realize large virtual gates and to increase gate array performance by combining a holographic memory with a programmable gate array. Among such studies, a 16-context ORGA architecture with nanosecond-order reconfiguration capability has already been demonstrated. However, its reconfiguration contexts are too few to execute large real-time operations. This paper therefore presents a proposal of a more advanced 100-context ORGA architecture in addition to related experimental results.

DOI： 10.1109/ISCAS.2010.5536965

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPRINGER-VERLAG BERLIN  

Embedded devices used for spacecraft, satellites, and space stations are vulnerable to the effects of high-energy charged particles. To resolve single-event latch-up (SEL)-associated troubles more flexibly using limited hardware resources in a space environment, reconfigurable devices such as field programmable gate arrays (FPGAs) are suitable. However, such reconfigurable systems present the shortcoming that the circuit itself on the gate array is not robust. The configuration context on a configuration SRAM also suffers from single-event upsets (SEUs) and SELs. This paper therefore proposes an MEMS dynamic optically reconfigurable gate array that is usable under a space radiation environment. The technique enables rapid recovery of a programmable device that has been damaged by high-energy charged particles. It uses incorrect configuration data including some error bits that had been damaged by particles. The configuration data are transferred using wireless communications and are retained on an EEP-ROM/SRAM.

DOI： 10.1007/978-3-642-12133-3_14

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION & COMMUNICATION ENGINEERS  

This paper presents a new remotely reconfigurable gate array, based on a dynamic optically reconfigurable gate array architecture, which is intended for use in systems at nuclear power plants, plants with no personnel, and other systems.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

We propose an optical buffering technique for a programmable gate array under a space radiation environment. The technique allows rapid recovery of a programmable device that is damaged by high-energy charged particles. The technique uses invalid configuration data, including error bits that have already been damaged by the particles, while the configuration data are transferred using wireless communications and are retained on electronically erasable, programmable read-only, or static random-access-memory devices. (C) 2009 Optical Society of America

DOI： 10.1364/OL.34.003719

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Reconfiguration applications based on reconfigurable devices present new computational paradigms since, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, Optically Reconfigurable Gate Arrays (ORGAs) with a holographic memory were developed. They realize rapid reconfigurations and numerous reconfiguration contexts. Furthermore, Optically Differential Reconfigurable Gate Arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However, fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results demonstrating its fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

DOI： 10.1109/JLT.2009.2024173

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：SPRINGER  

Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 mu m and 0.35 mu m CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.

DOI： 10.1007/s10470-008-9210-9

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPRINGER-VERLAG BERLIN  

To date, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present the advantageous capabilities compared with ORGAs: they have increased reconfiguration frequency per unit of laser power and reduced optical power consumption. Dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density, but an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array that adopts only the good factors from both architectures has been developed. This paper presents an inversion/non-inversion implementation for a fabricated 11,424 gate-count dynamic optically reconfigurable gate array VLSI. Based on that implementation, three factors are discussed: gate density, reconfiguration frequency per unit of laser power, and optical power consumption.

DOI： 10.1007/978-3-642-03138-0_15

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記述言語：英語  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the ORGAs capability of perfectly parallel programmability enables avoidance of those defective areas through alternative use of other non-defective areas. Moreover, a holographic memory to store contexts is known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Consequently, damage of a holographic memory rarely affects its diffraction pattern or a reconfiguration context. For that reason, ORGAs are extremely robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability. This paper presents experimentation related to the defect tolerance of new optically reconfigurable gate array with a one-time easily writable volume holographic memory.

DOI： 10.1109/AHS.2009.62

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on a programmable device. Such dynamic reconfiguration necessitates two important features: fast reconfiguration and numerous contexts. However, because fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DOR-GAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a 16-context DORGA architecture. Furthermore, we present experimental results: 530-833 ns reconfiguration times and 5-9.375 mu s retention times.

DOI： 10.1109/AHS.2009.64

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.

DOI： 10.1109/ASAP.2009.41

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/newcas.2009.5290410

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically differential reconfigurable gate arrays (ODRGAs) have been developed to achieve rapid reconfiguration and numerous reconfiguration contexts. Although fast reconfiguration experiments of a four-context ODRGA have been presented in earlier reports, the number of configuration contexts was insufficient for dynamic reconfiguration applications. Therefore, we have developed a more advanced nine-context ODRGA system. This paper presents fast 86.2 ns reconfiguration experiments using a nine-context ODRGA architecture and discusses plans for future work.

DOI： 10.1109/ISCAS.2009.5118187

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：ASSOC COMPUTING MACHINERY  

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, compared with current field programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and then implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that daunting problem, this paper presents a nine-context programmable ORGA and its writer. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1145/1531542.1531606

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPRINGER-VERLAG BERLIN  

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs) that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a nine-context DORGA architecture. Furthermore, this paper presents experimental results: 1.2-8.97 mu s reconfiguration times and 66-221 mu s retention times.

DOI： 10.1007/978-3-642-00641-8_14

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on the use of junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm(2) and a 0.35 mu m-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper shows an experimental result of a long retention time of its photodiode memory architecture.

DOI： 10.1109/ASPDAC.2009.4796460

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DOI： 10.1364/AO.48.000302

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve huge virtual gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teragate counts will be producible. However, compared with current field programmable gate arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world's first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results. (C) 2009 Optical Society of America

DOI： 10.1364/AO.48.000302

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have particularly high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the perfectly parallel programmable capability of ORGAs enables perfect avoidance of those defective areas through alternative use of other non-defective areas. Moreover, holographic memories to store contexts are known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. For those reasons, the damage of some part of the device rarely affects its diffraction pattern or a reconfiguration context. Consequently, ORGAs are very robust against component defects in devices such as a laser array, a gate array, and a holographic memory, and are particularly useful for space applications, which require high reliability. This paper presents experimental results of defect tolerance of a new dynamic optically reconfigurable gate array with a one-time easily writable holographic memory.

DOI： 10.1109/MWSCAS.2009.5235916

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, exploitation of the storage capacity of a holographic memory produces ORGAs with more than tera-gate capacity. However, comparison of conventional ORGAs with current field programmable gate arrays (FPGAs) reveals one important shortcoming: they are not reprogrammable after fabrication: to reprogram an ORGA, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and again implemented onto the ORGA package with high precision beyond the capability of manual assembly. Therefore, to remove that shortcoming, a programmable ORGA has been proposed. However, since previously proposed programmable ORGA configurations used a beam splitter, its alignment was complicated. Furthermore, the alignments of lasers were also limited. This paper presents a multi-context programmable optically reconfigurable gate array that uses no beam splitter. Furthermore, this paper presents discussions of the availability of this architecture and future plans based on experimental results.

DOI： 10.1109/MWSCAS.2009.5235928

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on its programmable gate array. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous contexts. However, fast reconfigurations and numerous contexts share a trade-off relation on current VLSIs. Therefore, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma. ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Also, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the world's first demonstration of an ORGA with micro electro mechanical system's (MEMS) holographic memory.

DOI： 10.1109/FPL.2009.5272445

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Optically reconfigurable gate arrays (ORGAs) have been developed for the purposes of realizing large virtual gates and increasing a gate array's performance by combining a holographic memory with a programmable gate array. In addition, dynamic optically reconfigurable gate arrays (DORGAs) using a photodiode memory architecture have been developed to realize a high-density VLSI. We have already demonstrated a 16-context DORGA architecture with a nanosecond-order reconfiguration capability. This paper presents a more advanced 36-context DORGA with performance that exceeds that of current dynamic reconfigurable devices. ©2009 IEEE.

DOI： 10.1109/SI.2009.5384563

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers. However, such high-power lasers increase power consumption and package size. In the worst case, they might require a cooling system. For that reason, this paper proposes a negative logic implementation method by which optical configurations can be accelerated without ORGA architecture modification and any increase of laser power. This time, the method was demonstrated on a dynamic optically reconfigurable gate array architecture. Based on the experimental results, this paper clarifies the acceleration method's effectiveness.

DOI： 10.1109/ELECTRO.2009.5441043

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

A function enabling remote programming is necessary for systems at nuclear power plants, plants with no personnel, and other systems. Recently, an optically reconfigurable gate array (ORGA) architecture has been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. However, ORGA architectures have never realized a remote programming capability. Therefore, this paper proposes a new remotely reconfigurable gate array architecture that enables remote reconfiguration using optical fiber networks. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1109/SOCDC.2009.5423925

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

To date, for large system integrations, various optically reconfigurable gate arrays (ORGAs) have been developed to realize both fast reconfiguration and numerous reconfiguration contexts. Optically differential reconfigurable gate arrays (ODRGAs) present advantageous capabilities compared with ORGAs: they have increased reconfiguration frequency per unit of laser power and reduced optical power consumption. Dynamic optically reconfigurable gate arrays (DORGA) can realize the highest gate density. Nevertheless, an important disadvantage of DORGAs is that their reconfiguration frequency is lower than that of ODRGAs and their optical power consumption is greater than that of ODRGAs. Therefore, a novel inversion/non-inversion dynamic optically reconfigurable gate array incorporating only the good attributes from both architectures has been developed. This paper presents a novel inversion/non-inversion ORGA using a rewritable MEMS holographic memory. ©2009 IEEE.

DOI： 10.1109/SI.2009.5384560

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Demands for fast dynamic reconfiguration for programmable devices have increased because the fast dynamic reconfiguration can increase the number of functions on a gate array. This paper presents a proposal of a novel optically differential reconfigurable gate array architecture with a microelectromechanical system (MEMS) mirror array that enables high-speed reconfiguration by exploiting large-bandwidth optical connections between the MEMS mirror array and a programmable gate array. The MEMS mirror array is used as a holographic memory. Four configuration contexts can be programmed electrically and dynamically onto the MEMS mirror array as holographic memory information. A configuration procedure is executed by switching of both a laser array and a MEMS mirror array. This experiment has demonstrated a four-context 9 ns microelectromechanical reconfiguration for a programmable gate array.

DOI： 10.1109/EDSSC.2009.5394174

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Fast reconfiguration and numerous reconfiguration contexts are two important features of dynamically reconfigurable devices. However, realizing both is difficult in current dynamically reconfigurable devices. Therefore, optically reconfigurable gate arrays (ORGAs) have been under development to solve this problem. Actually, ORGAs can realize a large virtual gate count over current VLSIs by combining a holographic memory storing numerous reconfiguration contexts with an optically reconfigurable gate array VLSI. To date, a 16-configuration-context ORGA has been developed. This paper presents a more advanced demonstration of a 36-configuration-context ORGA architecture, which is larger than the number of reconfiguration contexts of current dynamically reconfigurable devices. The 36-configuration-context ORGA architecture achieved 52 ns - 1.65 mu s fast reconfiguration. In addition, this paper presents a discussion of some technical issues for increasing the number of configuration contexts of a multi-context ORGA and future vision, based on results of several experiments.

DOI： 10.1109/SOCDC.2009.5423866

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Reconfiguration applications based on reconfigurable devices present new computational paradigms because increasing the reconfiguration frequency of such devices can enhance their activity and performance dramatically. Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory were developed, achieving important new advances in the areas of rapid reconfiguration and numerous reconfiguration contexts. Furthermore, optically differential reconfigurable gate arrays have been developed to accelerate optical reconfigurations of conventional ORGAs. This paper presents experimental results of the fastest 13.75 ns holographic reconfiguration of an optically differential reconfigurable gate array, along with discussion of the advantages of optically differential reconfigurable gate array architecture. © 2009 IEEE.

DOI： 10.1109/IIH-MSP.2009.250

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on its programmable gate array. Such dynamic reconfiguration is dependent upon two important features: fast reconfiguration and numerous contexts. However, fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically recon-figurable gate arrays (ORGAs) have been developed to resolve this dilemma. Among studies of such devices, this paper presents a demonstration of a dynamic ORGA (DORGA) with a MEMS holographic memory and its fault tolerance analysis results. ©2009 IEEE.

DOI： 10.1109/MHS.2009.5352102

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, optically reconfigurable gate arrays (OR-GAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, in contrast to current field-programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package and reprogrammed outside of the ORGA package using a holographic memory writer. Then it must be implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that problem, this paper presents a new programmable optically reconfigurable gate array and its lens-less imaging holographic memory writer system. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

DOI： 10.1109/ELECTRO.2009.5441161

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語  

DOI： 10.1364/AO.47.004692

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC AMER  

An optically reconfigurable gate array (ORGA) system, which consists of an ORGA very large scale integration (VLSI), an easily rewritable liquid crystal holographic memory recording four configuration contexts, and a laser array, is proposed. Circuits on a gate array of the ORGA-VLSI can be programmed rapidly by exploiting large parallel connections between a holographic memory and a gate array VLSI; that programming can be executed even as it is being programmed. Consequently, the gate array can be switched from a certain circuit to another circuit instantaneously. We present a demonstration of the ORGA system and experimental results. (C) 2008 Optical Society of America

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.

DOI： 10.1109/JQE.2008.916705

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. However in ORGAs, although a large virtual gate count can be realized by exploiting the large capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is still important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, to increase the gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However to date, although only a 1.83-1.89 ms single-context holographic configuration and a retention time of 3.495.61 s of DORGA architecture have been confirmed, the performance at nanosecond-scale reconfiguration with a multi-context DORGA architecture has never been analyzed. Therefore, this paper presents the experimental result of a 937.5 ns multi-context holographic configuration and a 30.75 mu s retention time of DORGA architecture. The advantages of this architecture are discussed in relation to the results of this study.

DOI： 10.1109/IPDPS.2008.4536539

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Reconfiguration applications based on reconfigurable devices present new computational paradigms because, by increasing the reconfiguration frequency of reconfigurable devices, their activity and performance can be improved dramatically. Recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory have been developed to realize rapid reconfigurations and numerous reconfiguration contexts. In addition, optically differential reconfigurable gate arrays (ODRGAs) have been developed to accelerate optical reconfigurations of conventional ORGAs. However fast configuration experiments under multiple contexts exploiting the ODRGA architecture have never been reported. Therefore, this paper presents a four-context ODRGA system and experimental results that elucidate aspects of fast reconfiguration. The advantage of the ODRGA architecture is discussed based on those results.

DOI： 10.1109/ASAP.2008.4580174

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：WORLD SCIENTIFIC AND ENGINEERING ACAD AND SOC  

Up to now, an optically differential reconfigurable gate array taking a differential reconfiguration strategy and a dynamic optically reconfigurable gate array taking a photodiode memory architecture have been proposed. The differential reconfiguration strategy can increase the reconfiguration frequency, with no increase in laser power, compared to other optically reconfigurable gate arrays, but the differential reconfiguration strategy can not achieve a high gate count VLSI because of the area occupied by static configuration memory. On the other hand, the dynamic optically reconfigurable gate array can achieve a high-gate count VLSI, but its configuration speed is slower than that of the optically differential reconfigurable gate array using equivalent laser power. Therefore, to realize both advantages of rapid configuration and a high gate count, this paper presents a novel inversion/non-inversion dynamic optically reconfigurable gate array that combines both architectures. In this study, the effectiveness of the inversion/non-inversion optical configuration method is clarified through some experiments.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper presents a novel inversion / non-inversion zero-overhead dynamic optically reconfigurable gate array that can extract good factors from architectures of both optically differential reconfigurable gate arrays and dynamic optically reconfigurable gate arrays. A full VLSI design using a 0.35 mu m CMOS process technology is presented. Based on that presentation, three factors are discussed: gate density; reconfiguration frequency per unit of laser power, optical power consumption.

DOI： 10.1109/FPT.2008.4762422

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

A DORGA architecture has been proposed to increase gate density It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the world's largest 11,424 gate-count dynamic optically reconfigurable gale array (DORGA) VLSI fabricated on a 96.04 mm(2) chip using a 0.35 mu m three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture arc, discussed in relation to the results described herein.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In previously proposed ORGAs, the optical reconfiguration period was designed to be constant by assuming a worst-case reconfiguration speed. However, the diffraction efficiency of a holographic memory differs depending on the number of bright bits included in a configuration context. Therefore, previous ORGAs can not fully exploit reconfiguration performance. For that reason, this paper presents a proposal for an analog reconfiguration-period adjustment technique for ORGAs to reduce each reconfiguration period. The advantages are then discussed herein based on experimental results obtained using an ORGA system on which the technique is adopted.

DOI： 10.1109/FPT.2008.4762400

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.

DOI： 10.1109/VLSI.2008.26

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

To increase gate density, a dynamic optically reconfig-urable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted, thereby demonstrating its availability. However, because the resolution of the liquid crystal holographic memory is very low and because the storable configuration contexts are numerically limited to four, that estimation cannot be considered a practical experiment. Therefore, this paper presents a practical demonstration of the DORGA architecture using a silver-halide holographic memory that can store over 3,000 configuration contexts. The DORGA architecture performance, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study. ©2008 IEEE.

DOI： 10.1109/ISVLSI.2008.94

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array to realize fast reconfiguration and numerous reconfiguration contexts. Along with such advantages, ORGAs have high defect tolerance. They consist simply of a holographic memory, a laser diode array, and a gate array VLSI. Even if a gate array VLSI includes defective areas, the perfectly parallel programmable capability of ORGAs enables perfect avoidance of those defective areas through alternative use of other non-defective areas. Moreover holographic memories to store contexts are known to have high defect tolerance because each bit of a reconfiguration context can be generated from the entire holographic memory. Moreover the damage of some fraction rarely affects its diffraction pattern or a reconfiguration context. Therefore, ORGAs are very robust against component defects in devices such as laser arrays, gate arrays, and holographic memory, and are particularly useful for space applications, which require high reliability. However, to date, the degree to which defects in a holographic memory affects holographic configurations has never been analyzed. Therefore, this paper describes analysis results of defect limitations of holographic configurations.

DOI： 10.1109/IPDPS.2008.4536537

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. It is noteworthy that ORGA-VLSIs which can be reconfigured in nanoseconds without any overhead have already been fabricated. However to date, no multiholographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has ever been developed. As the first step toward realizing such a device, a four-context optical system is demonstrated experimentally using a liquid crystal spatial light modulator and a He-Ne laser This paper describes those experimental results and plans for future work.

DOI： 10.1109/VLSI.2008.27

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve huge virtual gate counts that is much larger than those of currently available VLSIs. Using ORGA architecture, greater than 1 tera gate count VLSIs are possible by exploiting the storage capacity of a holographic memory. Conventional ORGAs have only one shortcoming compared with current field programmable gate arrays (FPGAs) : they are not reprogrammable after their fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and implemented into the ORGA package with high precision beyond that available by manual assembly. To improve that shortcoming, this paper presents the world's first programmable ORGA architecture and experimental results. Furthermore, in light of those experimental results, this paper presents discussion of the availability of this architecture and future plans.

DOI： 10.1109/SI.2008.4770434

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Recently, to realize large real-time systems, demands for fast computation on large VLSI have continued to increase. An optically reconfigurable gate array has been developed to realize large virtual gates. As part of that research effort, the world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on a concept using junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm(2) and a 0.35 mu m-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper presents an experimental result of along retention time of its photodiode memory architecture.

DOI： 10.1109/SI.2008.4770433

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, dynamic optically reconfigurable architecture has been proposed to increase the gate count of the ORGA-VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memories. Consequently, extremely high gate count ORGAs have been realized. However, in this architecture, since background diffraction light of configuration contexts reduces the retention time of circuit information stored in junction capacitances of photodiodes, it has remained a concern that under multi-configuration, an optical configuration can reduce the retention time of other circuits that have already been programmed before the configuration and are functioning on a gate array. This paper clarifies that the dynamic optically reconfigurable architecture is effective even under multi-configuration.

DOI： 10.1109/SOCC.2008.4641495

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. Up to now, four-context ORGAs have been demonstrated. This paper presents the first 9-context ORGA architecture that uses spreading beams of Vertical Cavity Surface Emitting Lasers (VCSELs) with no lenses. This paper describes experimental results and plans for future work.

DOI： 10.1109/SOCDC.2008.4815560

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