記述言語：日本語   掲載種別：研究論文（学術雑誌）  

担当区分：筆頭著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： 10.14923/transcomj.2017PEP0001

記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.14923/transcomj.2017PEP0001

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

DOI： 10.1587/transinf.2015ICP0018

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A connector model expressed as an inductance is proposed for use in a previously reported common-mode antenna model. The common-mode antenna model is an equivalent model for estimating only common-mode radiation from a printed circuit board (PCB) more quickly and with less computational resources than a calculation method that fully divides the entire structure of the PCB into elemental cells, such as narrow signal traces and thin dielectric layers. Although the common-mode antenna model can estimate the amount of radiation on the basis of the pin configuration of the connector between two PCBs, the calculation results do not show the peak frequency shift in the radiation spectrum when there is a change in the pin configuration. A previous study suggested that the frequency shift depends on the total inductance of the connector, which led to the development of the connector model reported here, which takes into account the effective inductance of the connector. The common-mode antenna model with the developed connector model accurately simulates the peak frequency shift caused by a change in the connector pin configuration. The results agree well with measured spectra (error of 3 dB).

DOI： 10.1587/transcom.2015EBP3269

担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1541/ieejfms.136.365

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

DOI： 10.1587/transcom.E98.B.1188

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IOP PUBLISHING LTD  

The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.011502

担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

DOI： 10.1109/TEMC.2013.2250505

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

担当区分：筆頭著者   記述言語：英語   掲載種別：研究論文（学術雑誌）  

記述言語：英語   掲載種別：研究論文（学術雑誌）  

掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.1109/temc.2023.3345883

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TEMC.2023.3236674

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope57790.2023.10274220

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241637

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241643

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：電子情報通信学会  

損失を有する共振器型フィルタは，回路基板の平行平板共振抑制時におけるオープンスタブ構造からの不要放射が懸念される．本論文では，放射要因ごとに分解したモデルを用いて共振抑制時の放射を評価した結果，当該構造からの放射増は無視できる程度と判明した．

DOI： 10.14923/transcomj.2022bll0005

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LEMCPA.2022.3228199

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：The Institute of Electronics, Information and Communication Engineers  

This paper examines the possibility of an electromagnetic interference (EMI) caused by unintentional radiated emissions from an unshielded twisted pair (UTP) cable in the sub-6GHz band of 5G. First, it is experimentally and numerically confirmed that a UTP cable with a twist pitch of 20mm and a sheath with relative permittivity of 2.9 radiates above 5.7GHz. It is also clarified that the radiated emissions are attributable to the twist structure. In addition, the usefulness of two equations, derived in developing radiating pair cables, to easily calculate the radiation band and the radiation angle to solve the EMI problem is validated.

DOI： https://doi.org/10.1587/comex.2022XBL0101

掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/comex.2022xbl0101

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We investigated the prediction of side-channel leak-age on the power delivery network (PDN) outside a cryptographic IC. To predict the leakage, it is necessary to estimate the switching current caused by the switching activity. So far, high temporal resolution estimation based on gate-level logic simulation has been proposed, but due to the decoupling property of the PDN, the switching current leaking out of the IC chip attenuates signif-icantly. Therefore, this paper calculates the mean of the switching currents over the clock period based on register transfer level (RTL) logic simulation, and then approximates it into a triangle waveform. This approach enables us to simulate the switching current faster than with gate-level simulation. In addition, the simulation time is further shortened by calculating the switching current only to the targeted round of a cryptographic algorithm (AES). Switching currents of the previous rounds were given as statistical models with the same sample mean and variance as the targeted round. As a result of simulating the switching current of an FPGA with the proposed method, we were able to obtain the low-order harmonic components of the current in almost the same magnitude as the gate-level simulation. We also simulated correlation power analysis (CPA) results for the printed circuit board on which the FPGA with the AES circuit was mounted, and found that the proposed method could predict the dynamic power supply voltage observed on the board and CPA results with sufficient accuracy.

DOI： 10.1109/EMCEurope51680.2022.9900948

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We previously proposed a lossy resonator filter to suppress the parallel-plate resonance of printed circuit boards (PCBs). The filter consists of an open stub (a quarter-wavelength resonator) covered with a ferrite thin film (inducing a small loss). This paper evaluates the effect of the small loss by investigating the suppression of parallel-plate resonance and the unintentional radiation from a PCB with or without the ferrite thin film. An open stub can work as a narrow-band filter but may also work as an antenna and radiate unintentionally, which causes a secondary noise problem at frequencies other than the target frequency of 2.4 GHz. The electric field distribution between the parallel plates and the total radiated power were thus investigated to validate the effect of the small loss of the lossy resonator filter. The results showed that the total radiated power from parallel plates resonating at 2.4 GHz was suppressed by about 12 dB by using open stubs with a resonant frequency of 2.4 GHz, regardless of the presence or absence of the ferrite thin film. At 2.54 GHz, however, the open stubs without ferrite increased the radiated power by about 10 dB, whereas those with ferrite did not increase it at all. It was thus found that the lossy resonator filter could suppress not only the parallel-plate resonance but also unintentional radiation around the target frequency without causing any other problems.

DOI： 10.1109/EMCEurope51680.2022.9901324

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Once the signal-tu-noise ratio (SNR) of the side- channel (SC) leakage trace is known, the intensity of the SC information leakage source inside the integrated circuit (IC) can be identified from measurements carried out outside the IC, SNR observation of SC leakage can also make it possible to set quantitative design targets to achieve the demanded leakage intensity. We discuss an improved method for identifying the SNR of SC leakage traces composed of multiple transient responses of IC switching current. The IC switching current repeatedly occurs as the IC runs the cryptographic operation since the cryptographic algorithm repeats a set of sub-operations. The method was applied to simulated and measured leakage traces to eliminate the effect of transient IC switching current caused before the target sub-operation was processed. As a result, a transient component more extensive than the signal component of side-channel analysis was identified in the decoupling capacitor configuration, where the convergence of the transient response is slow. In addition, the correlation coefficients obtained by the correlation power analysis, a major side-channel analysis method, were plotted as a function of SNR, and the plot of the simulated traces agreed with the theoretical curve. On the other hand, some errors remained in the plot of the measured traces.

DOI： 10.1109/EMCSI39492.2022.9889660

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掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.1109/lemcpa.2022.3228199

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ic4me253898.2021.9768521

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc49932.2021.9596844

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc49932.2021.9597127

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

To estimate the amount of noise suppressed by lossy resonator filters (LRFs) in a power bus with a decoupling capacitor, we used an equivalent circuit model considering the effect of the capacitor to know the suppression mechanism using the LRF. The discrepancy between the model and a full-wave simulation was approximately 2 dB.

DOI： 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559213

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper proposes noise-source parameter identification of the noise-source equivalent-circuit model for predicting conducted noise while considering the switching fluctuation of a DC/DC converter. We decomposed measured conducted noise into ripple noise, turn-on spike noise, and turn- off spike noise to prevent the accuracy degradation in the parameter identification. The predicted conducted noise spectra show the error with the measurement was within 3 dB up to 200 MHz, which is more accurate than that in our previous study.

DOI： 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559182

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.</p>

DOI： 10.1587/transcom.2020EBP3056

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

In recent years, some lightweight cipher algorithms for IoT devices have been proposed. These algorithms can be applied to a variety of IoT devices without occupying too much memory and power consumption, and compared to traditional ciphers, such as AES, these algorithms have higher efficiency. The Speck algorithm is a lightweight block cipher, proposed by the NSA in June 2013, and it is specifically optimized for IoT microcontrollers. A few previous studies have shown that the Speck algorithm can be attacked through power analysis. Based on Arduino Uno as the implementation platform of the Speck 128/128 algorithm, in this paper, we propose a method to attack the Speck 128/128 algorithm. Our experiment results have shown that when the attack point in the last round of Speck 128/128 XOR operation, the round key can be successfully recovered by the Correlation Power Analysis attack.

DOI： 10.1109/CANDARW51189.2020.00076

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Symmetry is important for differential-transmission lines, but the dense parallel traces easily break the symmetry due to coupling with the adjacent conductor, leading to mode conversion. We propose an asymmetric geometry of differential-transmission lines placed on the side of a nonadjacent conductor to suppress mode conversion and maintain signal integrity in the cases of loosely coupled and tightly coupled parallel traces. By designing the asymmetric geometry of dense differential-transmission lines by taking into account coupling with the adjacent conductor, mode conversion was successfully suppressed by decreasing the line width on the side of the non-adjacent conductor. It was also found that the asymmetric geometry can suppress mode conversion and maintain signal integrity in tightly coupled parallel traces. In loosely coupled parallel traces, on the other hand, the tightly coupled asymmetrically tapered bend we previously proposed suppresses mode conversion.

DOI： 10.1109/EMCEUROPE48519.2020.9245880

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We investigated impedance discontinuity detection on a wire network by applying sequence time domain reflectometry (STDR) using maximal-length sequence (M-sequence). We focused on impedance discontinuity detection under multiple reflection generated at nodes on a wire network. We first conducted a preliminary investigation of impedance discontinuity detection on a wire network with one node and confirmed that STDR resulting in cross-correlation of the observed signal with transmitted pulse train exhibits higher noise immunity than conventional TDR. We then demonstrated that STDR can distinguish the impedance discontinuity of various (resistive, inductive, and capacitive) impedance variations on a wire from the shape of the correlation response. Finally, we demonstrated that STDR can detect the location of impedance discontinuity due to small inductance and capacitance on a simple wire network with four nodes.

DOI： 10.1109/EMCEUROPE48519.2020.9245855

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

As the conducted disturbance of a power converter changes with its load value, the relationship between the electromagnetic interference of the power converter and its load needs to be investigated. This work examines a 2-port equivalent circuit model for a DC/DC buck converter with consideration of the load effect. Factors that influence the model accuracy are also discussed. We used a synchronous buck converter operating under a continuous conduction mode condition to determine the load effect and evaluate the model. Results showed that the input port of the fixed-load model and load-variable model had good accuracy up to 70 MHz. We also predicted the load effect on input port noise and found that the input port noise of an 8.2-? load could be predicted from the other two load values (6.6 ? and 11.6 ?).

DOI： 10.1109/EMCEUROPE48519.2020.9245680

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Controller Area Network (CAN) is widely employed as an in-vehicle network, and is required for extremely high reliability. CAN uses five mechanisms to detect errors caused by channel noises in CAN frames. However, an adversary can reportedly falsify a CAN frame by tampering with sample points in the frame. In this paper, the effectiveness of a new falsification method that does not require sample point tampering is proposed. In the method, transient electromagnetic pulses are injected into a CAN bus by magnetic coupling that enables falsification at the target CAN node without error detection. The proposed method was examined on a CAN bus which consists of two CAN nodes. As a result, the new falsification method was effective for CAN.

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsi38923.2020.9191655

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2019.8871971

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2019.8871562

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

A method for optimally designing RL and RC snubber circuits is presented to reduce the electromagnetic interference caused by parasitic LC resonance. The Q factor of the resonance is used as the design criteria. Optimum snubber parameters are determined analytically and uniquely by using a simplified equivalent circuit of the resonant loop and deriving an analytical formula for the Q factor as a function of the snubber parameters. The optimally designed snubbers can adequately adjust the Q factor to any design target. They can also minimize the increases in the negative effects of the snubbers, i.e., overshoot and power loss. The method was applied to RL and RC snubbers to be added to a synchronous buck converter. The effects of the snubbers were reproduced by simulation program with integrated circuit emphasis ( SPICE) simulation to validate the method from the perspective of resonance damping, overshoot, and power loss. The results showed that the damping effects obtained with the optimized snubbers met the Q factor design targets. They also demonstrate that the parameters are optimum in terms of suppressing overshoot and power loss. These results indicate that the method is suitable for optimizing RL and RC snubbers to damp parasitic LC resonance.

DOI： 10.1109/TEMC.2018.2841424

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担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

<p>EMI対策および評価コストの削減を目的として，ノイズ源IC毎の放射強度推定法を提案する。この手法はEMI発生要因の1つであるスイッチング電流を振幅変調し，その時の電磁妨害波の時間変化を観測することで得られるノイズ源強度比から各ICの放射強度を推定する。本論文では，プリント回路板に提案手法を適用し，遠方界放射から複数ICによる放射の強度を算出，さらにIC個別に駆動した測定結果と比較し推定精度を評価した。その結果，各ICに起因する放射が同相と見なせる場合に放射強度を高い精度で推定可能であることを示した。</p>

DOI： 10.5104/jiep.22.218

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：日本ソフトウェア科学会  

<p>IoT機器の情報セキュリティを保証するために不可欠な技術の1つである暗号技術に関する実践的な演習科目を開発した．開発した演習は，現代暗号の基礎となっている代数学や離散数学の座学，暗号アルゴリズムのハードウェア実装，そして実装した暗号ハードウェアへのサイドチャネル攻撃実験で構成される．本演習では，暗号アルゴリズムの教科書的な知識を学ぶだけでなく，受講生自身が暗号アルゴリズムを市販ハードウェアへ実装し，その実装ハードウェアへの攻撃を実行することで，実用上の脅威を体験し，そのような脅威を考慮して暗号アルゴリズムを実装する重要性を理解することを目標としている．本演習を学部3, 4年生50名に対して実施し，ほぼ全員がこの目標を達成した．さらに受講生へのアンケートによると，ほぼ全ての受講生が暗号技術に関する実践力向上を実感する結果を得た．</p>

DOI： 10.11309/jssst.36.30

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

DOI： 10.1109/EMCEurope.2018.8485011

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記述言語：日本語  

DOI： 10.14923/transcomj.2017PEP0001

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担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1541/ieejfms.136.365

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.2015ICP0018

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記述言語：日本語  

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transcom.2015EBP3269

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記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1541/ieejfms.136.25

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

DOI： 10.1587/transcom.E98.B.1188

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掲載種別：研究論文（国際会議プロシーディングス）  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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記述言語：日本語  

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

バルク電流やバーストといった外乱注入により発生した暗号FPGAの誤動作に関して考察した。特に発生した誤動作の直接原因がクロックグリッチの場合について、まず、外乱によりFPGAのクロック配線にグリッチが重畳することを実験により検証した。次に、発生した誤動作をグリッチ付クロックをFPGAに直接与える構成において再現し、回路動作とグリッチの関係を検証した。以上の実験結果に基づき、外乱によりクロックグリッチが発生した場合の誤動作発生機構、および評価環境における誤動作発生確率を示した。

DOI： 10.11486/ejisso.28.0_63

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

DOI： 10.1109/TEMC.2013.2250505

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記述言語：日本語  

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担当区分：筆頭著者,　責任著者   記述言語：日本語  

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担当区分：責任著者   記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

IC/LSIの高周波電流による電磁妨害波(EMI, Electromagnetic Interference)のシミュレーションヘの適用を目的として,ドライバ回路のマクロモデルを構築する.従来は,ドライバ回路の動作モデルとしてIBIS (Input/output Buffer Information Specification)モデルが幅広く使われてきた.しかし,IBISモデルは信号系解析用モデルであり,EMIシミュレーションに用いると誤差が大きいという問題がある.そこで,EMIシミュレーションにも適用可能な新しいマクロモデルを提案する.トランジスタの静特性に着目し,IBISモデルより静特性のモデリング精度を向上させた.実際にドライバ回路について提案するマクロモデルを構築し,IBISモデルとの比較シミュレーションを実施した.その結果,IBISモデルに比べて高精度な結果が得られた.

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記述言語：日本語  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：INST PURE APPLIED PHYSICS  

A new algorithm to estimate lidar ratios of aerosol layers with a monochromatic Mic-scattering lidar profile is proposed. The algorithm employs both the forward,and the backward solutions of the monochromatic single-scattering lidar equation. The lidar ratios are estimated through an iterative procedure to match the two solutions by correcting a lidar ratio assigned at the beginning of the procedure. The algorithm has been applied to simulated lidar profiles and a measured one from the literature. In testing of the simulated profiles, the estimation errors of the lidar ratios were investigated for four boundary conditions-clear to turbid conditions-by scanning boundary values and extinction coefficients of an aerosol layer. This investigation indicated that the algorithm estimates the lidar ratio with sufficient accuracy under clear boundary conditions even with inaccurate boundary values, but requires correct boundary values under turbid boundary conditions. The algorithm was successfully applied to the measured lidar profile of a thin aerosol layer. The obtained lidar ratio was reasonably plausible. This suggests that an enhanced form of this algorithm using the forward and the backward solutions would be able to determine the lidar ratios and boundary values from only a lidar profile measured under arbitrary atmospheric conditions.

DOI： 10.1143/JJAP.43.6513

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Blackwell Publishing Ltd  

We coordinated a ground-based network that has been in use since 1997 to observe Asian dust during springtime. Huge Asian dust events that occurred in the middle of April 1998 were captured by this network. In this paper we present the organization of the network
a description of the instruments, including the lidar, sky radiometer, and optical particle counter
and the results of the observation, and offer discussions regarding the transport mechanism of Asian dust in east Asia using an on-line tracer model. We discussed the time series of the surface concentration and the height distribution of the dust. A cutoff cyclone generated during the dust episode was responsible for trapping and sedimentation during the transportation of the Asian dust, particularly in the southern parts of China and Japan. Horizontal dust images derived from NOAA/AVHRR clearly revealed the structure of the vortex. The lidar network observation confirmed the general pattern of dust height distribution in this event
the height of the major dust layer was about 3 km over Japan but was higher (4 to 5 km) in Seoul and Hefei. A thin dust layer in the upper troposphere was also commonly observed in Hefei and Japan. Evidence of the coexistence of dust and cirrus was shown by the polarization lidar. The lidar network observation of Asian dust and satellite remote sensing provide key information for the study of the transport mechanism of Asian dust. Further extension of the lidar network toward the interior of the continent and the Pacific Rim would reveal the greater global mechanism of the transportation. Copyright 2001 by the American Geophysical Union.

DOI： 10.1029/2000JD900554

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

A new inversion inhomogeneous atmosphere (IA) method that is more stable than Fernald’s method for two-component (molecule and aerosol) scattering analysis of polarized Mie lidar signals is proposed and examined. The backscattering coefficient and the extinction-to-backscattering ratio (EBR) can be calculated for specified regions at which the depolarization ratio is less than that of molecule without further assumptions. The inversion procedure can be extended to both inward stepwise and outward stepwise integration algorithms. Simulation results indicate that a higher precision was achieved with the IA method than with Fernald’s method in terms of error and random noise in estimating boundary value and EBR. Experimental results were also better with the IA method than with Fernald’s method. © 2001 Optical Society of America.

DOI： 10.1364/JOSAA.18.000392

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical Engineers of Japan  

In the modal-equivalent circuit derived from the view of the mode-decomposition technique, mode-conversion sources are placed at the interface where the imbalance factor of the transmission lines changes. In addition, the amount of the mode-conversion sources is proportional to not only the difference in the imbalance factor but also the magnitudes of the normal-mode voltage and the common-mode current at the same position. In this paper, therefore, the suppression of mode conversion from normal mode to common mode is experimentally examined by installing a bypass capacitor to power distribution network. The bypass capacitor helps reduce the normal-mode voltage in the vicinity of a connector on a test board where mode conversion occurs so that the common-mode current flowing a power-line cable and the electric field far from the test board are decreased. In fact, the mode conversion was most suppressed when the bypass capacitor is placed closest to the connector on the test board. Also, it was found that the mode conversion was suppressed by the capacitor installed to the power-line cable in the vicinity of the connector.

DOI： 10.1541/ieejfms.136.25

担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

担当区分：筆頭著者,　責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical Engineers of Japan  

Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors
(1) leakage is reduced by making Hamming distance (HD) at registers constant, (2)leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

DOI： 10.1541/ieejfms.136.365

記述言語：日本語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1541/ieejfms.136.25

担当区分：責任著者   記述言語：英語   掲載種別：研究発表ペーパー・要旨（国際会議）  

担当区分：責任著者   記述言語：英語   掲載種別：研究発表ペーパー・要旨（国際会議）  

担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究発表ペーパー・要旨（国際会議）  

担当区分：責任著者   記述言語：英語   掲載種別：記事・総説・解説・論説等（国際会議プロシーディングズ）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Pseudo-random binary sequence (PRBS) was applied to identify dominant noise sources of electromagnetic interference (EMI) radiated from a printed circuit board (PCB) including line driver ICs. The ICs were controlled in activation of output according to a set of PRBSs that varied amplitude of switching current generated in the ICs and also changes the strength of EMI. Correlation coefficients between the temporal variation of conducted EMI strength and PRBS were examined. Results showed that PRBS has a potential to identify dominant noise sources of EMI.

DOI： 10.1109/ICCE-China.2017.7991087

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記述言語：英語   掲載種別：記事・総説・解説・論説等（国際会議プロシーディングズ）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The miniaturization of unit cells in planar electromagnetic bandgap (EBG) structures has been difficult because the stopband frequency depends on the unit-cell size. To solve this problem, we developed an EBG structure that uses two power planes (dual power plane: DPP) with the addition of a capacitive coupling element. This enables us to easily enlarge the capacitance formed in the unit cell and achieve miniaturization with a stopband frequency of interest. Using full-wave simulation, we tested a 2-mm-square (4-mm2) unit cell of the DPP-EBG structure and measured a stopband frequency around 2.4 GHz.

DOI： 10.1109/APEMC.2017.7975472

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記述言語：英語   掲載種別：記事・総説・解説・論説等（国際会議プロシーディングズ）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Improving the countermeasures against side-channel attacks (SCAs) increases the cost of both designing the countermeasures and evaluating SCA resistance. This may force cryptographic ICs to remain vulnerable. The increased cost is due to an indispensable procedure where a large number of side-channel traces need to be analyzed in order to evaluate the SCA resistance. In this work, a low-cost method to design and evaluate countermeasures using the signal-to-noise ratio (SNR) of side-channel traces as design and evaluation criteria is proposed. The method combines two existing methods: A prediction method of correlation coefficients between side-channel traces and a power model based on the SNR of the side-channel traces, and an estimation method of the number of traces needed to disclose the secret key based on the correlation coefficients. We construct a method to measure the SNR of side-channel traces and validate it for the design and evaluation criteria. In our method, the SNR is first calculated from signal and noise variances extracted from side-channel traces by increasing the number of averaging in side-channel trace measurements, and then the correlation coefficients and the number of traces for key-disclose are estimated on the basis of the calculated SNR. We confirmed that the estimated correlation coefficient and the number of traces for key-disclose were in good agreement with the corresponding measured ones. This result demonstrates that the proposed method can accurately measure the SNR of side-channel traces.

DOI： 10.1109/APEMC.2017.7975433

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担当区分：責任著者   記述言語：英語   掲載種別：研究発表ペーパー・要旨（国際会議）  

記述言語：英語   掲載種別：記事・総説・解説・論説等（国際会議プロシーディングズ）  

J-GLOBAL

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記述言語：英語   掲載種別：記事・総説・解説・論説等（国際会議プロシーディングズ）  

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記述言語：英語   出版者・発行元：IEEE  

In this paper, the authors apply two modular exponentiation algorithms such as left-to-right binary method and Montgomery powering ladder algorithm on Raspberry Pi and evaluate their security against Side-channel attack.

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記述言語：英語   出版者・発行元：IEEE  

To overcome the intra EMC problems in wireless communications, electromagnetic bandgap (EBG) structures can be used to effectively reduce power-bus noise. We previously proposed a vialess open-stub EBG structure. However, it still has the intrinsic disadvantage of a narrow stopband because it uses the open-stub's resonance. Thus, this paper aims to optimize the structural parameters of the vialess open-stub EBG structure to sufficiently suppress power-bus noise in a wider stopband. The structural parameters to determine the noise-reduction performance of the vialess open-stub EBG structure are the branch width rob, the stub width w(s), and the unit-cell length alpha. Rectangular power buses were designed as test vehicles through the analytical approach and used to evaluate the stopband expansion and the noise suppression in the stopband in a full wave simulation. The transmission characteristics showed that, after w(b), W-s, and a are optimized, the stopband is expanded from 0.61 GHz (2.23-2.84 GHz) to 1.56 GHz (2.20-3.76 GHz). In addition, an optimized structure was made that reduced the amount of noise by approximately 10 dB.

DOI： 10.1109/ICSJ.2016.7801273

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記述言語：英語   出版者・発行元：IEEE  

The bend in a pair of differential transmission lines on printed circuit boards causes a path difference, which leads to mode conversion due to the phase difference. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion. In this paper, we propose a design methodology of our tightly coupled asymmetrically tapered bend that limits the bend structure within the area of the original classic bend for high-density mounting. We also evaluated the 45-degree-angle bend formed based on our design methodology and found that the methodology helps improve or maintain its transmission characteristics compared to those of the classic bend.

DOI： 10.1109/APEMC.2016.7522769

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記述言語：英語   出版者・発行元：IOP PUBLISHING LTD  

The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.011502

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記述言語：英語   出版者・発行元：IEEE  

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

DOI： 10.1109/ISEMC.2015.7256163

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記述言語：英語   出版者・発行元：IEEE  

This paper describes a proposed planar electromagnetic bandgap (EBG) structure whose unit cell size is miniaturized through the use of interdigital electrodes (IDEs). For planar EBG structures in general, it is difficult to miniaturize the cell size independently of stopband frequency because the stopband frequency depends on the cell size. For the proposed structure, however, the cell size can be miniaturized because the IDEs help enlarge the capacitance between adjacent unit cells and utilize a resonator formed in the unit cells. Because the resonator's resonant frequency determines the stopband frequency of an EBG structure with IDEs, the cell size can be miniaturized independently of the stopband frequency. In the work described in this paper, the proposed EBG structure's efficacy in reducing power bus noise was examined and evaluated through full-wave simulation and measurement in the wireless communication band. It was found that an IDE-EBG structure with a small (25 mm(2)) unit cell is a valid means for achieving power bus noise reduction.

DOI： 10.1109/EDAPS.2015.7383703

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記述言語：英語   出版者・発行元：IEEE  

This paper formulates mode conversions of transmission and reflection from differential mode to common mode in differential transmission lines with bend discontinuity using a very simple model. The formulae tell us that the mode conversion is caused by not only the path difference in the bend but also the difference between the characteristic impedance and port impedance. The formulae were validated by full-wave simulation under the assumption that effect of the bend region is small and results showed that path difference reduction and impedance matching at the input and output ports are significant in suppressing mode conversion. This suggests that the tightly coupled asymmetrically tapered bend proposed by the authors should be effective for suppressing mode conversion.

DOI： 10.1109/EDAPS.2015.7383689

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記述言語：日本語  

DOI： 10.5104/jiep.18.344

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記述言語：英語   出版者・発行元：IEEE  

Electromagnetic immunity analysis as well as electromagnetic emission analysis is significant for EMC design. In this paper, we apply a modal equivalent-circuit model with mode-conversion sources to electromagnetic immunity analysis in a simple cable interconnection system. The analysis can treat mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis and has been validated in electromagnetic emission analysis. The approach takes an advantage in less calculation sources and helps get design considerations compared with full-wave simulation. In this paper, common-mode excitation by a current probe in a simple cable interconnection system is investigated for model validation. As a result, it is demonstrated that the circuit analysis with the modal-equivalent circuit model agrees well with the measurement results.

DOI： 10.1109/APEMC.2015.7175388

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記述言語：英語   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

DOI： 10.1109/ISEMC.2014.6899067

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記述言語：英語   出版者・発行元：IEEE  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace too close to the return edge on a printed circuit board. In our previous study, a guard trace with a periodic structure was proposed not only to reduce common-mode radiation but also to maintain signal integrity and was found to be effective. In the current work, the shape of the periodic structure and the termination at both edges to improve the features was investigated through full-wave simulation and measurement from the viewpoint of transmission coefficient as well as far-field radiation. Results show that the smaller the widths of the narrow portion, the further the periodic structure helps reduce common-mode radiation and maintain signal integrity. Also shown is that the periodic guard trace with both ends connected to the return plane is an appropriate structure.

DOI： 10.1109/EDAPS.2014.7030811

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記述言語：英語   出版者・発行元：IEEE  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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記述言語：英語   出版者・発行元：IEEE  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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記述言語：英語   出版者・発行元：IEEE  

A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

DOI： 10.1109/EMCEurope.2014.6931007

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記述言語：英語   出版者・発行元：IEEE  

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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記述言語：英語   出版者・発行元：IEEE  

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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記述言語：英語   出版者・発行元：IEEE  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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記述言語：英語   出版者・発行元：IEEE  

For investigating mode conversion in four-conductor transmission systems we have developed a modal-equivalent-circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in three-conductor transmission systems. The modal equivalent circuit consists of three modal equivalent circuits of normal mode, primary-common mode, and secondary-common mode. In this paper, the influence of mode conversion by the pigtail termination of a shielded-twisted-pair (STP) cable was analyzed using the modal equivalent circuit and mixed-mode S parameters with respect to normal mode and primary- common mode. As a result, it was found that mode conversion depends on the imbalance factor and that the modal equivalent circuit helps to explain mode conversion that occurs in terminating STP cables with pigtail.

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記述言語：英語   出版者・発行元：IEEE  

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

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記述言語：英語   出版者・発行元：IEEE  

For treating mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis, we have proposed a modal equivalent-circuit model with mode-conversion sources. The approach takes an advantage in less calculation sources and countermeasure consideration compared with full-wave simulation. A mode-decomposition technique was applied with an imbalance factor, that is, the current division factor in our study, of the transmission line. In the modal circuit analysis we proposed, mode conversion is expressed by the controlled sources of which magnitude is proportional to the difference between the current division factors of the adjacent transmission lines. In this paper, we focused on the modal transfer power and derived the mathematical expressions of the mode conversion using the modal characteristic impedance as well as the current division factor. For validating the derived equations, in addition, the comparison with full-wave simulation was carried out and a good agreement was confirmed.

DOI： 10.1109/EDAPS.2013.6724455

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記述言語：英語   出版者・発行元：IEEE  

An equivalent circuit model was evaluated in simulating data-dependent power voltage variations of a field-programmable gate array (FPGA). The equivalent circuit model was Linear Equivalent Circuit and Current Source (LECCS) model representing dynamic switching current inside the FPGA with an equivalent current source. The current source was supposed to depend on input data for the FPGA on which a cryptographic circuit was implemented. Model identification was based on the procedure of LECCS model identification from on-board measurements and the current source was identified for all values of input data used in this work. The identified current source was investigated in accordance with the operation process of the cryptographic circuit and found an excellent correlation to the operation process. The identified LECCS model was combined with an equivalent circuit of the power distribution network for the FPGA core circuit to simulate power voltage variations for the 1,000 input texts. The simulated variation waveforms were compared to the corresponding measured ones to evaluate the LECCS model. Results indicated that the simulated and measured power variations matched excellently for all input data with high cross-correlation coefficients from 0.7 to 0.9. LECCS model is, therefore, able to predict the data-dependent power voltage variation by combining a PDN equivalent circuit.

DOI： 10.1109/EMCCompo.2013.6735196

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記述言語：英語   出版者・発行元：IEEE  

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

DOI： 10.1109/ISEMC.2013.6670526

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記述言語：英語  

Noise suppression and power integrity are two requirements for power/ground layers of printed circuit boards. To accomplish the requirements, we proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. To evaluate the proposed EBG structure, we have so far measured the electric characteristics of both driving-point impedance and transmission coefficient. Although these evaluation indices are helpful, the evaluation using an actual device is also indispensable. In this paper, we evaluated the suppression of noise propagation through power bus by the proposed EBG structure in wireless communication module. The proposed structure provided sufficient result of the effective maintenance of communication quality by suppressing the propagation of electromagnetic noise. © 2013 IEEE.

DOI： 10.1109/EDAPS.2013.6724428

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記述言語：英語   出版者・発行元：IEEE  

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

DOI： 10.1109/APEMC.2012.6237943

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記述言語：英語   出版者・発行元：IEEE  

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Delta h). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Delta h becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity.

DOI： 10.1109/ISEMC.2012.6351682

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記述言語：英語   出版者・発行元：IEEE  

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication.

DOI： 10.1109/ISEMC.2012.6351661

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記述言語：英語   出版者・発行元：SOC INSTRUMENT CONTROL ENGINEERS JAPAN  

Side-channel attacks are a kind of cryptanalytic attacks by means of the electric current in the range of radio frequency (RF) leaking out from a cryptographic integrated circuit (IC) and/or the electromagnetic radiation generated by the RF power current. The RF power current is caused by simultaneous switching activities of logic gates during an encryption process operated in the cryptographic IC. The RF power current is a major cause of the electromagnetic interference (EMI). To decrease the RF power current at PCB level can lead to decrease designing costs. As a preparation of applying LECCS models to a cryptographic IC for estimating the RF power current occurred during an encryption process, the model parameters were identified from measurements in this paper. The LECCS models were composed of a current source that expressed the RF power current occurred in the cryptographic circuit and a passive network. The current source identified grown in amplitude 200 ns after the beginning of the encryption process. This agreed to the beginning of the target round. In frequency domain, current spectra were seen at 24 MHz and its harmonics. The authors obtained waveforms of the RF power current from analog circuit simulations with the LECCS model identified, and validated the cryptographic device in security against the side-channel attacks by means of the correlation power analysis (CPA) method. Results of CPA with the simulated waveforms were consistent to CPA results with measured waveforms. These results means that model parameters were identified correctly, and suggests that the LECCS model is effective for validation of cryptographic devices with respect to side-channel attacks.

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記述言語：英語  

A lot of improvements and optimizations for the hardware implementation of AES algorithm have been reported. These reports often use, instead of arithmetic operations in the AES original, those in its isomorphic tower field and. This paper focuses on which provides higher-speed arithmetic operations than. In the case of adopting, not only high-speed arithmetic operations in but also high-speed basis conversion matrices from the to should be used. Thus, this paper improves arithmetic operations in with Redundantly Represented Basis (RRB), and provides basis conversion matrices with More Miscellaneously Mixed Bases (MMMB). © Springer-Verlag Berlin Heidelberg 2012.

DOI： 10.1007/978-3-642-34117-5-4

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記述言語：英語   出版者・発行元：IEEE  

In grounding an STP cable, mode conversion occurs depending on how to ground it. For investigating the mode conversion in a four-conductor transmission-line system that consists of three conductors and the system ground such as the STP cable above the system ground, as shown in Fig. I. we have developed modal equivalent circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in a three-conductor transmission-line system. The modal equivalent circuit consists of three modal equivalent circuits of normal mode (Fig. 2), primary common mode (Fig. 3), and secondary common mode(Fig. 4). In this paper, mode conversion between normal mode and primary common mode was evaluated using mixed-mode S parameters and the measured data validated the modal equivalent circuit. As a result, it was found that mode conversion depends on the imbalance factor and it was examined how to ground for suppressing mode conversion.

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記述言語：英語   出版者・発行元：IEEE  

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

ICパッケージ電気特性のモデリングにおいて,電磁界シミュレーションに基づき構築したモデルを実測結果と比較することは,一つの重要なモデル精度検証方法である.しかし,過去の報告では,パッケージを開封した状態での測定例が報告されているのみであり,パッケージを封止した状態での測定例は見られない.筆者らは,封止かつボード実装された状態におけるパッケージ特性の測定法を検討しており,本報告では、自己インダクタンスの測定法を検討した.提案法では,特性が既知のTHRUラインを用いて,そのTHRUラインをチップ部にマウントしたパッケージをPCB上に実装し,PCB上の測定結果からパッケージ部の自己インダクタンスを抽出する.そして,実測および3次元電磁界解析により抽出精度を検証した.その結果,500 MHz以下で実測では-0.8〜-0.2 nH,電磁界解析では-0.9〜-0.6nHの絶対誤差で自己インダクタンスを測定できた.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板の電源/グラウンド層間における高周波ノイズ伝搬阻止のため,電磁的バンドギャップ(Electromagnetic Bandgap : EBG)構造の層間への適用が検討されている.2本のスタブを用いたオープンスタブ型EBG構造では,セルサイズの小型化,阻止域の拡大およびマルチバンド化が期待できる.本稿では,等価回路モデルを用いたマッシュルーム型EBG構造やスタブ1本のオープンスタブ型EBG構造との比較を行い,その特性を明らかにする.さらに,オープンスタブ型EBG構造において,無線LAN使用周波数である2.4GHz, 5.2GHzの周波数帯域に阻止域を得るための設計手法を検討した.最終的に,2本の異なる長さのスタブをもつオープンスタブ型EBG構造により,2.4GHz, 5.2GHz帯のそれぞれに2つの阻止域が形成できることを確認した.最後に,特性量を利用した等価回路解析と物理的なサイズまでを考慮した電磁界シミュレータによる解析を比較し,等価回路モデルにおけるスパイラル状スタブの等価長について考察を行った.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板(Printed Circuit Board : PCB)の電源層が具備すべき条件は,高周波ノイズの伝搬阻止と電源バウンスの生じない電源供給である.我々は,PCBの電源-グラウンド層に対して,電磁バンドギャップ(Electromagnetic Bandgap : EBG)構造の導入に加え,磁気損失効果のあるフェライト膜を電源-グラウンド層間へ挿入した電源層が有効であると考えている.本論文では,この提案構造のテスト基板と,これと比較するための3種類のテスト基板を作製し,ネットワークアナライザを用いたSパラメータの2ポート測定により,不要電磁波(Electromagnetic Interference : EMI)抑制と電源品質(Power Integrity : PI)の両特性を評価した.さらに,PI特性については実際の回路への導入を想定し,模擬電源回路と組み合わせた場合の評価を回路シミュレータを用いて検討した.提案構造はEMI抑制,PI特性とも良好な結果を得た.同様にEBG構造ではないベタ層とフェライト膜を組み合わせたテスト基板も提案構造と同等の結果が得られることが分かった.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電流配分率の異なる線路が接続された3導体で構成される伝送系では,線路の接続点においてモード変換が生じる.モード変換を回路上で表現するモ-ド変換励振源を用いて,送受信機器が平行2本線路で接続された系を対象としてモード等価回路を構築した.このモード等価回路の実測における有効性を,コモンモード電流とノーマルモード電圧を用いて評価した.実測と回路シミュレーションのスペクトルは概ね良く一致し,モード変換の影響によって,コモンモードの共振時にコモンモードからノーマルモードヘの変換によりノーマルモード電圧が影響を受けることを確認した.そこでモード変換励振源のパラメータである2つの線路の電流配分率の差とコモンモード電流に着目して,モード変換の抑制を試みた.対策を行ったその結果,回路シミュレーションで予測されたように,モード変換の影響を低減することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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担当区分：責任著者   記述言語：英語   出版者・発行元：IEEE  

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules.

DOI： 10.1109/ISEMC.2011.6038441

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記述言語：英語   出版者・発行元：IEEE  

Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs). We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for noise-suppression and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit. Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results.

DOI： 10.1109/EDAPS.2011.6213804

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

送受信器が平行ケーブルで接続された3導体系の伝送線路が,システムグラウンドからある一定の距離を隔てて設置されている場合を対象として,モード等価回路を構築した.実電圧・電流の直交モード分解に基づき導出された直交モードの変換行列は,モード電圧間,モード電流間のみのモード変換を表現する.電流配分率の異なる線路を接続した場合では,線路の接続位置にモード変換電圧源やモード変換電流源を挿入することに相当する.モデル評価では,誘電体を含まない導体のみからなる簡単な系を対象とした.提案法では,ノーマルモード等価回路,コモンモード等価回路を別々に構築し,モード変換電圧源やモード変換電流源に両者を結び付けることで回路シミュレータを用いて解くことができる.解析対象を結合伝送線路と考えて回路シミュレーションで解いた場合とは非常によく一致した.さらに,フルウェーブ計算で得られたモード電流のスペクトルとも概ねよく一致した.フルウェーブ計算ではTEMモードが前提ではないため,TEMモードからのずれが計算結果に影響することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

ICの過渡動作時における,電源安定性(PI,Power Integrity)及び信号完全性(SI,Signal Integrity)解析の高精度化を目的として,ICマクロモデルを提案する.ICマクロモデルは,信号系解析用のIBIS(Input/output Buffer Information Specification)モデルと電源系解析用のLECCS-core(Linear Equivalent Circuit and Current Source for core circuits)モデルを組み合わせた構造をとる.PI及びSI特性は相互に影響し,組合せ構造をとることで両特性を高精度に表現できることを示す.従来にも,同様の組合せ構造をもつモデルが存在したが,本モデルとはインダクタンスの位置及びモデル抽出法が異なる.トランジスタレベルモデルに対して,本モデルと従来モデルを抽出し,比較シミュレーションを実施した.その結果,本モデルの方がトランジスタレベルモデルのシミュレーション結果とよく一致した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

デカップリングキャパシタを実装することで,デカップリングキャパシタが持つESLと電源系パターンの寄生容量が共振を起こし,IC/LSIのスイッチングに起因する高周波電流が増加する場合がある.本報告では,この問題について述べ,対策法としてデカップリングインダクタの配置について検討し,電源端子電流の低減効果をシミュレーションにより確認した.DUTとして,汎用ロジックICを実装した25mm角のプリント基板を用い,シミュレーションにはLECCSモデルを使用した.その結果,寄生のキャパシタよりIC側にデカップリングインダクタを挿入した場合には,低周波において鋭いピークがみられるものの,高周波電流を大きく低減できることを示した.さらに,寄生のキャパシタより外部にデカップリングインダクタを挿入した場合には,電源端子電流を全周波数において低減できることを示した.また,チップ部の電源端子間の電位差をシミュレーションし,PIへの影響は十分小さいことを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

インバータやコンバータのようにスイッチング電源を内蔵した家電製品の電源ポート伝導妨害波を低減する電源フィルタ設計への適用を目的として、インバータの線形等価回路モデルを構築した。まず、市販電子レンジを被試験体として疑似電源回路網(LISN)を用いて伝導妨害波電圧を測定した。その結果にディファレンシャルモードおよびコモンモードどちらのノイズも確認されたため、両モードを表現する等価回路構造を決定し、モデル定数を決定する手法を述べた。さらに実際に伝導妨害波電流測定よりモデル定数を決定した。最後に構築したモデルを使い回路シミュレーションにより電磁妨害波電圧を予測し測定結果と比較した。その結果、決定したモデル定数が有意であった周波数においてはEMIフィルタによるノイズ低減効果を実用的な精度で予測した。これにより測定による構築可能なマクロモデルのEMIフィルタ設計への適用可能性を示した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

システムグラウンドからある一定の距離を隔ててケーブルで接続された送受信器が設定されている伝送系において、提案するコモンモード等価回路モデルにより、この系を流れるコモンモード電流を見積もった。このモデルは、伝送線路の平衡度が変わるケーブルと送受信器の接続点にコモンモード励振源が生じ、これによりコモンモード電流が流れると考える平衡度不整合理論に基づいている。今回、送受信器がケーブルで接続された単純な伝送系を対象としてコモンモード等価回路モデルを適用し、その系を流れるコモンモード電流を推定できるか調べた。さらに、モデルの評価では、コモンモード電流をノーマルモード電圧で規格化した伝達アドミタンスを指標に用いた。送受信器のシステムグラウンドとの接続状態や、伝送系の全長、システムグラウンドからの距離、ケーブルの平衡度を変え、回路シミュレータにより提案モデルを用いてコモンモード電流を計算したところ、実際の測定結果と概ね一致する結果を得、このモデルの有効性を確かめた。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板上の伝送系の帰路面にスリットパターンを導入することにより,それ自体が何らかの受動素子のような振る舞いをする.DGS(Defected Ground Structure)もその1つである.DGSは,導入するスリットパターンによりその伝搬特性が大きく変化するため,フィルタなど様々な用途への応用が期待される.しかし,導入するスリットパターンの設計手法が確立されていないため,明確な設計手法モデルが必要である.3次元電磁界シミュレータによる解析ではコストが大きいうえ,最終的な特性と構造の相関関係が不明確である.これまでにいくつかの等価回路モデルが利用されているが,それらは集中定数モデルで,さらに3次元解析を必要とする.また,集中定数素子の値は物理構造とは対応しておらず設計に用いるのは困難である.本報告では,フィルタとして機能するDGSに着目し,伝送線路モデルを用いた等価回路モデルの構築を行った.3次元解析の結果と等価回路モデルを回路解析した結果の透過特性を比較すると,フィルタとして一般的に利用される第一伝搬阻止域は概ね一致した.

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記述言語：英語   出版者・発行元：IEEE  

The noise suppression effect after interposing a ferrite film of several microns in thickness between the power and ground planes is discussed in this paper. In particular, we focused on the combination of a planar electromagnetic bandgap structure with a ferrite film deposited by using spin spray ferrite plating at a low temperature. In this paper, the stopband characteristics are discussed through the use of both simulation and measurement results. First, a full-wave electromagnetic simulation revealed that a test board with a dielectric as thin as a few hundreds of microns has the stopband characteristics of the frequency shift towards the lower frequencies (miniaturization effect) and stopband expansion with the removal of the passband, which was not observed in the case of a thick-dielectric test board. The simulation results also demonstrated that these improvements mainly resulted from the complex permeability of the ferrite film. Next, we found that the measurements are very similar to the simulation results.

DOI： 10.1109/APEMC.2010.5475608

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記述言語：英語   出版者・発行元：IEEE  

The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator.

DOI： 10.1109/ISEMC.2010.5711287

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電源系解析用ICマクロモデルLECCS(Linear Equivalent Circuit and Current Source)を,バイパス回路設計に適用する.EMI(Electromagnetic Interference:不要電磁輻射)低減とPI(Power Integrity:電源安定性)確保を設計要件とし,LECCSモデルを用いて各性能を向上するための方策について検討した.LECCSモデルは線形等価回路と等価内部電流源より構成されるが,EMI性能と線形等価回路,PI性能と等価内部電流源が密接に関連し,各方策が異なることを述べる.方策に基づいたバイパス回路の設計例を示し,SPICEモデルを用いてその効果を検証した結果,機能することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電源系解析用ICマクロモデルLECCS(Linear Equivalent Circuit and Current Source)を,バイパス回路設計に適用する.EMI(Electromagnetic Interference:不要電磁輻射)低減とPI(Power Integrity:電源安定性)確保を設計要件とし,LECCSモデルを用いて各性能を向上するための方策について検討した.LECCSモデルは線形等価回路と等価内部電流源より構成されるが,EMI性能と線形等価回路,PI性能と等価内部電流源が密接に関連し,各方策が異なることを述べる.方策に基づいたバイパス回路の設計例を示し,SPICEモデルを用いてその効果を検証した結果,機能することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板のEMC設計において,IC/LSIのEMCマクロモデルの優位性はますます高まっている.EMI放射は電源だけでなく出力系の高周波電流も原因となるため,出力端子電流モデル化も重要である.本報告では,従来電源系解析だけでなく出力系解析を考慮したLECCS-I/Oモデルを構築する.測定より二つ電流源をもつLECCS-I/Oモデル構築し,電源および出力端子電流のシミュレーション精度を検証した.また電流源が一つのLECCS-I/Oモデルとの比較も行った.その結果,電源電流シミュレーションでは,両モデルとも500MHz以下の周波数で精度よく一致していた.一方,出力電流シミュレーションでは,電流源が一つの場合に大きな誤差が生じているのに対して,電流源が二つの場合では500MHz以下の周波数で精度よく一致した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板の電源/グランドプレーンに形成した電磁バンドギャップ(Electromagnetic Bandgap:EBG)構造は,帯域阻止フィルタとして動作し,不要電磁波伝搬の抑制に有効である.我々はこれまでに,ノイズ抑制シートを電源/グランド層間へ挿入することがEBG構造の小型化及び高周波側への阻止域の拡大を実現することに有効であることを実験的に示している.しかし,実験で使用したノイズ抑制シートの透磁率が小さくなる高周波数域で小型化の効果が見られた.本報告ではノイズ抑制シートの誘電率に着目し,飽和磁界を印加した状態でSパラメータ測定を行うことで誘電率と透磁率の効果を切り分けて評価した.EBG構造にノイズ抑制シートを適用した場合の阻止域の低周波側へのシフトは,ノイズ抑制シートの異方性誘電率の効果によることが判明した.これは特にスリットにおける面内方向の電界成分に作用したためである.これは,市販の電磁界シミュレータMicrowave Studioを用いた計算でも再現できた.この結果を踏まえて,EBGパターンへの効果的なノイズ抑制シートの適用法を実験的に示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

1GHzを超えるEMIは自由空間で測定するように規定されている。この測定に使用するサイトの評価を行なう方法として、CISPR 16-1-4にサイトVSRW法が規定されている。このサイトVSWR法では、400mmの範囲に6点の測定ポイントを設けて、その点からの伝達特性の最大・最小によって自由空間条件の評価を行なう。この測定法では、測定ポイント数が少ないために測定結果に大きな不確かさを生じている。この測定は周波数間隔が50MHz以下で測定を行なうことが規定されている。一般的には、上限の50MHz間隔で測定を行なうが、我々は、測定周波数ステップを小さくすることによって不確かさを低減させる手法を提案し、実際の測定によってその効果を確認した。また、この手法では測定点の設定誤差に対する不確かさも低減できることを示した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：社団法人電子情報通信学会  

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記述言語：英語   出版者・発行元：IEEE  

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記述言語：英語   出版者・発行元：IEEE  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

我々の研究グループではIC/LSIの電源系を流れる高周波電流をシミュレーションするため,EMCマクロモデルである多電源ピンLECCS-coreモデルを提案している.このECCS-coreモデルはIC/LSIの電源系を流れるCMOSトランジスタのスイッチングに伴い発生する高周波電流を線形等価回路と内部電流源で表現する.本報告では,DUTを複数の電源端子を有するマイクロコントローラとし,モデル構築基板とは配線パターンの異なる別の基板を用い,LECCS-coreモデルによる電源端子電流シミュレーションと実測を比較した.その結果,平均誤差4dB以内で実測と一致した.さらにバイパスキャパシタを外した場合において,電源配線が合流する箇所でも精度良く電源端子電流がシミュレーションできることを示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

本報告では,コネクタを介して接続されているプリント回路基板(PCB)に対して,コネクタ部の持つインダクタンスを考慮したコモンモードアンテナモデルを提案する.コモンモードアンテナモデルは,PCBからのコモンモード放射を高速かつ少ない計算コストで計算できる.前報では,コネクタ接続PCBにおいてもコネクタのピン配置による放射量の変化を計算することができることを示した.しかし実測で見られた放射スペクトルの周波数シフトは再現できなかったので,ピーク付近の精度は十分とは言えなかった.この原因をコネクタ部の実効インダクタンス変化と考え,本報告ではこれを考慮することでモデル改良を行った.その結果,このインダクタンスを考慮した改良モデルでは放射の周波数シフトが表現でき,実測結果と比較したところピーク付近での精度は誤差2dB程度まで改善した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：英語   出版者・発行元：IEEE  

This paper describes an electromagnetic interference (EMI) simulation of radiated emissions caused by simultaneous switching noise in an irregular power/ground plane structure. For quick simulation of the radiated emissions from the power-bus edges, we used a series of analytical approaches: power-bus resonance characterization by a fast algorithm based on a cavity-mode model and a segmentation method and radiation calculation using equivalent magnetic current based on the field equivalent principle. The analytically based radiation calculation is achieved within a few minutes on a single personal computer and agrees with the actual measurements. Furthermore, this paper demonstrates an EMI simulation with and without decoupling capacitors by using a linear macro model of an integrated circuit as a noise source. We found a fair agreement between the simulation and measured results.

DOI： 10.1109/APEMC.2008.4559902

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記述言語：英語   出版者・発行元：IEEE  

We investigated the effects of noise suppression by interposing magnetic materials between the power and ground planes of a printed circuit board and focused on RF transmission through and radiation from the power bus. To reduce power bus resonance and radiation, we used a commercial noise suppression sheet, which is commonly used to suppress RF noise generated from electronic devices. We also examined a thin Ni-Zn ferrite film for practical use in the future. We found that power bus resonance and radiation could be mitigated owing to the imaginary part of complex permeability of magnetic materials. The thin ferrite film with a planar electromagnetic bandgap (EBG) structure helped suppress transmission and radiation in the EBG passband.

DOI： 10.1109/APEMC.2008.4559938

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記述言語：英語   出版者・発行元：IEEE  

We have proposed a common-mode antenna model that is designed specifically for estimating common-mode radiation from printed circuit boards (PCBs) very quickly. The model is composed of an antenna that has the same geometry as the adjacent ground plane of the PCB and an excitation source based on an imbalance difference model. The excitation source is provided by the product of Delta h and V-N, where Delta h is the difference in current division factors related to the cross-sectional structure of the transmission line, and VN is the voltage between the signal line and return plane of the transmission line. Here, we describe an experimental validation of the common-mode excitation carried out by measuring the reduction in radiation due to a guard trace placed close to a signal line with a narrow return plane. As a result, it was found that the total common-mode excitation can be given by a superposition of two excitation sources. The results also suggest that when designing the PCB, the guard trace should be grounded at the interface between different ground-plane widths to suppress noise.

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記述言語：英語   出版者・発行元：IEEE  

In this paper, the common-mode antenna model, which can estimate the amount of common-mode radiation quickly and accurately, was applied to a board-to-board interconnection structure with a connector. The inductor model is introduced as the connector model for improving accuracy of the common-mode antenna model. By using the inductance, which was calculated with the commercial electromagnetic field simulator, the radiated emissions estimated by the model agreed with the measurement results within an error of 3 dB around the peak emission levels.

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記述言語：英語   出版者・発行元：IEEE  

The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.

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記述言語：英語   出版者・発行元：IEEE  

An EMC macro-model of a 16-bit microcontroller with multiple-power-supply pins has been proposed for estimating the conducted EMI from a power-supply network. The macro-model, called the linear equivalent circuit and current sources (LECCS) model, is composed of multiple circuit blocks and multiple current sources corresponding to the composition of the chip circuits in the microcontroller, i.e., a current source for a circuit block. A current source statistically expresses the total RF current occurring in the corresponding circuit block. We confirmed that the proposed model could correctly estimate the RF power-supply currents under different decoupling conditions up to 300 MHz. We also found that a linear circuit of the regulator between the I/O and core circuit blocks could express the RF coupling between the two blocks.

DOI： 10.1109/EDAPS.2008.4736018

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：日本磁気学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

これまで筆者らは,IC/LSIの電源系に流れる高周波電流予測のためのEMCマクロモデルLECCSを提案している.このLECCSモデルは,非線形回路素子であるCMOSトランジスタで構成されるIC/LSIのスイッチングノイズを線形等価回路と等価内部電流源で表現する.線形等価回路構築にあたってIC/LSIの電源系インピーダンス測定をした結果,高周波で反共振が生じていた.本報告では,その反共振の一因がパッケージ及びその外部の寄生インピーダンスであることを,3種類の基板を用いた電源系インピーダンス測定と,その比較により明らかにした.次に,それぞれの基板の寄生容量を市販の電磁界シミュレータSonnetで見積もり,LECCSへ付加したうえで,PSpiceを用いて電源系インピーダンスシミュレーションをし,実測と比較した.そして,LECCSに寄生容量を付加することでモデル精度が向上しうることを示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

これまでに筆者らは,プリント回路基板(Printed Circuit Board:PCB)から発生するコモンモード放射を高速に予測するためのコモンモードアンテナモデルを提案している.このコモンモードアンテナモデルはコモンモード励振源とアンテナエレメントから構成される.コモンモード励根源はPCB上に広く分布するため,複数のマイクロストリップ線路(Microstrip Line:MSL)がPCB上に配線された場合,同一の位置に異なるMSLに起因するコモンモード励振源が存在することになる.複数のMSLがPCB上に配線された場合のコモンモード放射計算を目標に,本報告では,直角に曲がったMSLがPCB上に配置された試験基板を用いて,コモンモード励根源の重ね合わせを検討した.遠方電界放射の測定とFDTD法による数値解析による比較の結果,コモンモード励振源の重ね合わせができることを示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

マザーボードとドーターボードがコネクタを介して接続されている場合,コネクタ部のグラウンドピン数を変えたときにプリント回路基板(Printed Circuit Board:PCB)のコモンモード放射量が変化することが報告されている.この放射量の変化について,これまでに我々のグループでPCBからの放射予測を高速に行うために提案してきたコモンモードアンテナモデルを用いることで説明できるのかどうかを実際にコネクタ接続基板を作製し,その遠方電界放射の測定と比較することで検証した.コモンモードアンテナモデル構築の際,コモンモード電位変換係数よりプリント回路基板上のコモンモード電位分布を求め,その電位差をコモンモード励振源とする.これを基板上に配置しアンテナ解析することで遠方電界放射を求めた.実測と計算を比較する際,コネクタ接続基板ではグラウンドピン数によってコネクタ部の特性インピーダンスが変化することも考慮した.ボード部とコネクタ部の平衡度を調べ,その差が少なくなるようなコネクタを設計することでコモンモード放射を低減することができることが分かった.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：英語   出版者・発行元：AMER METEOROLOGICAL SOC  

A Coulter Multisizer, which is based on the electrical sensing zone (ESZ) or the Coulter principle, was used to measure the size distribution of Asian dust. Coulter Multisizer analysis provides high-resolution size measurements of water-insoluble aerosol particles (WIPs) and the number concentration at each size bin. Aerosol filter sampling was conducted at four sites in Japan during spring 2003. The measured volume size distributions fit fairly well with a lognormal distribution. The results show that the WIP size distributions of the same Asian dust air mass varied at each sampling site and the volume mode diameter at the sites reduced from west to east. The derived volume mode diameter ranged from 1.4 to 2.2 mu m and was comparatively smaller than those in previous studies on Asian dust. This can be explained by the possible internal mixing of Asian dust with other components and by the breaking of particles and dispersion of aggregations by ultrasonification during extraction. The analysis method was improved by washing the aerosol particles collected on a filter using a magnetic stirrer, instead of an ultrasonic cleaner. As a result, the WIP size distribution can be measured in the range of 1-10 mu m. The measured mode diameters were 2.6-3.1 and 4.3-5.6 mu m in 2 Asian dust phenomena at Kofu, Japan, in 2004. It is demonstrated that the Coulter Multisizer method can furnish detailed information regarding the spatial and temporal variations in the mineral dust size distribution.

DOI： 10.1175/JTECH1965.1

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記述言語：英語   出版者・発行元：IEEE  

In order to estimate. the amount of common-mode radiation from a printed circuit board with low calculation cost, a common-mode antenna model has been developed. This paper demonstrates the application of the model to a board interconnection via a connector that is known to be a possible source of common-mode radiation. The radiated emissions estimated by the model agreed with the measurements for practical use.

DOI： 10.1109/ELMAGC.2007.4413451

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記述言語：英語   出版者・発行元：IEEE  

This paper describes fast calculation of radiated emissions from an arbitrarily shaped printed circuit board (PCB). The radiated emissions from the PCB edge are calculated by taking into account magnetic surface current based on the field equivalent principle. The electric field at the PCB edge is provided by a fast algorithm the authors have proposed for power-bus resonance in the PCB. The calculation of radiated emission was completed within a few minutes and in, good agreement with Finite Difference Time Domain (FDTD) calculation. In addition, an EMI simulation was demonstrated by using a linear macro model of IC/LSI. The calculation results were found to be in good agreement with the measurements.

DOI： 10.1109/ELMAGC.2007.4413479

Web of Science

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記述言語：英語   出版者・発行元：IEEE  

Electromagnetic bandgap (EBG) structures in a pair of parallel planes are quite effective for suppressing simultaneous switching noise, but they are too large to be applied to compact electronic devices. To miniaturize the EBG structures, we investigated an approach to interpose a high-permeability magnetic metal sheet between the parallel planes. The experimental results show that high permeability of the sheet shifts the stopband towards lower frequencies. This suggests that such sheets contribute to the miniaturization of the EBG structures. In addition, it is demonstrated that the imaginary part of the permeability can expand the stopband.

DOI： 10.1109/ISEMC.2007.19

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記述言語：英語   出版者・発行元：ETH FOUNDATION ZURICH  

A motherboard-daughterboard structure with a connector is known to have another source of common-mode radiated emissions, and the emissions depend on the connector's signal/ground pin configuration. In order to estimate the amount of radiated emissions from the structure, a common-mode antenna model is described. The model consists of an excitation source and an antenna element, and it calculates radiated emissions from PCBs not only quickly but accurately for practical use. In modeling the board interconnection via a connector, we added two common-mode excitation sources at each end of the connector. The electromagnetic emissions estimated by the model agreed with the measurements within an error of 6 dB around peak emission levels between 300 and 600 MHz.

DOI： 10.1109/EMCZUR.2007.4388207

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

筆者らが提案しているディジタルICのEMCマクロモデル(LECCS-I/O)の広帯域化のため,Sパラメータ測定に基づくインピーダンスパラメータ抽出法について検討した.まず,従来モデルにおいて電源-グランド間インピーダンスのシミュレーション精度が高周波で低下する原因を調べたところ,2ポートSパラメータ測定ではIC入力端子に接続された外部回路の影響がモデルのインピーダンスパラメータに現れることが判明した.そこで,IC内部の等価回路と外部回路を分離するためICの入力部を考慮した線形等価回路(LEC)のモデルを構築し,3ポートSパラメータ測定によるパラメータ抽出を検討した.ICの外部負荷や入力端子に接続する回路を変化させた時のインピーダンスシミュレーションを行ったところ,従来モデルと比較してより高い周波数までモデルのシミュレーション精度が向上した.

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記述言語：英語   出版者・発行元：IEEE  

Is proposed an approach to know magnitudes of parasitic electromagnetic modes excited by the micro-strip line passing over a slit in the return plane. A part of the power having been carried along, the microstrip-line is transferred to the coplanar-line modes along the slot, and the cylindrical. mode in between the pair of re. turn and ground planes. Magnitudes of those modes are expressed by the ratio of powers of the excited electromagnetic mode to the original microstrip line mode, discarding information of phase. Calculation was done with FDTD in the limited domain., around the cross-point in a moderate time of calculation. This approach contributes to the efficient designing of PCB of commercial electronic devices.

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記述言語：英語  

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記述言語：英語   出版者・発行元：Faculty of Engineering, Okayama University  

The optical properties of clouds were measured with a polarization Mie lidar during April, 2004 and investigated to categorize the particles detected by the lidar. The cloudlayers were categorized into five types according to the depolarization ratios, as follows: (I) constant and small (less than 5%); increasing with height (II) nearly from 0% and (III) from about 50%; (IV) large and varying with the backscattering coefficient; and (V) sharply decreasing. This categorization of clouds enabled us to separate aerosols from clouds in a lidar signal. Comparison of the backscattering coefficients between clouds of types (I) and(II) suggested that the depolarization ratio induced by multiple scattering in dense clouds does not depend on the particle density. Estimation of the particle phase for the five cloud categories was also examined.

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担当区分：筆頭著者   記述言語：英語   掲載種別：記事・総説・解説・論説等（大学・研究所紀要）   出版者・発行元：Faculty of Engineering, Okayama University  

Aerosol extinction coefficients of clouds and dust were continuously measured in the year of 2002 with a polarized Mie-scattering lidar controlled by an automatic and remotely operating system utilizing internet services. Measured cloud extinctions were greater than 1.0 km(-1) below the altitude 6 km, 0.17 - 1.0 km(-1) between 6 and 10 km, and 0.091 - 0.3 km(-1) beyond 10km. Extinction of dust were 0.10 and 0.20 km(-1) for Asian dust and 0.057 km(-1) for urban dust.

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DOI： 10.1117/12.417092

Scopus

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記述言語：英語   出版者・発行元：Faculty of Engineering, Okayama University  

In spring of 1998, Asian dust was observed with a Mie LIDAR in Okayama University, which can measure depolarization ratio. Three events of intense Asian dust were occurred in the period and medially detailed structure of atmosphere was found after examining records. Asian dust was distinguished from water droplets and the possibility to study three dimensional dynamic structure of atmosphere were demonstrated.

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開催年月日： 2022年7月14日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2022年4月15日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2022年3月15日 - 2022年3月18日

記述言語：日本語   会議種別：口頭発表（一般）  

国名：日本国  

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開催年月日： 2022年1月18日 - 2022年1月21日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2022年1月18日 - 2022年1月21日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年12月17日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年12月13日 - 2021年12月14日

記述言語：日本語   会議種別：ポスター発表  

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開催年月日： 2021年11月24日 - 2021年11月30日

記述言語：日本語   会議種別：公開講演，セミナー，チュートリアル，講習，講義等  

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開催年月日： 2021年10月23日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年10月23日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年10月23日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年10月23日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年9月14日 - 2021年9月17日

記述言語：日本語   会議種別：口頭発表（一般）  

国名：日本国  

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開催年月日： 2021年9月14日 - 2021年9月17日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年6月15日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年4月16日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2021年3月9日 - 2021年3月12日

記述言語：日本語   会議種別：口頭発表（一般）  

国名：日本国  

開催年月日： 2020年12月11日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2020年10月26日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2020年5月15日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2020年5月15日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2020年1月28日 - 2020年1月31日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2020年1月17日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2020年

記述言語：日本語  

<p>ケーブル-コネクタ間の平衡度不整合によるコモンモード発生、さらに、放射シミュレーションを行うには、コネクタの電流配分率を容易に算出できることが不可欠である。今回、コネクタのSパラメータから電流配分率を算出する簡易モデルを構築したのでこれを報告する。</p>

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開催年月日： 2019年12月6日

記述言語：日本語   会議種別：ポスター発表  

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開催年月日： 2019年7月19日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年7月18日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年7月18日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年5月10日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年3月19日 - 2019年3月22日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年3月19日 - 2019年3月22日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年1月22日 - 2019年1月25日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2019年

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2018年11月22日 - 2018年11月23日

記述言語：英語   会議種別：口頭発表（一般）  

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開催年月日： 2018年11月22日

記述言語：英語  

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開催年月日： 2018年11月22日

記述言語：英語   会議種別：口頭発表（一般）  

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開催年月日： 2018年3月6日 - 2018年3月8日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2018年1月23日 - 2018年1月26日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2018年1月23日 - 2018年1月26日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2018年1月18日 - 2018年1月19日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2018年1月18日 - 2018年1月19日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2018年1月18日 - 2018年1月19日

記述言語：日本語   会議種別：口頭発表（一般）  

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開催年月日： 2015年5月15日

記述言語：日本語  

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開催年月日： 2015年1月22日

記述言語：日本語  

周期構造による電磁バンドギャップ(Electromagnetic Bandgap: EBG)形成(EBG構造)により,プリント回路基板の電源-グラウンド層間の高周波ノイズを低減する検討が行われている.EBG構造はその抑制量が非常に大きいため,デジアナ混載基板において微弱な信号を扱う高周波回路部に対してディジタル回路部で発生する同時スイッチングノイズの伝搬抑制に有効である.EBG構造には様々な形状があるが,大まかにはビアの有無で分類できる.我々は,ビアの無いプレーナ型EBG構造に着目して高周波ノイズの抑制を検討してきた.これは2層で構成でき,ビアが不要であることからコスト面からも有利と考えられるためである.一方,ビア有りのEBGで提案されているオープンスタブEBGは抑制周波数に依存せず小型化が可能である.オープンスタブEBG構造はビア有りに特有の構造と考えていたが,本報告では,構造を工夫することでビア無しのプレーナ型オープンスタブEBG構造を提案する.そして,電磁界シミュレーションによりその抑制効果を調べ,2.4GHz帯においてそれを確認した.

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開催年月日： 2014年

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開催年月日： 2012年12月14日

記述言語：日本語  

IC/LSIの同時スイッチングノイズに起因するEMI予測を目的として開発されたEMCマクロモデルを使用し、暗号モジュールのサイドチャネル攻撃に対する安全性を予測した。暗号モジュールとして市販のサイドチャネル攻撃標準評価プリント基板SASEBO-Gを使用し、AES暗号に対して相関電力解析によるサイドチャネル攻撃を仕掛けた時の安全性を、EMCマクロモデルと電源供給回路の線形等価回路を用いた回路シミュレーションによって予測した。EMCマクロモデルのインピーダンスおよび等価電流源はLECSSモデルの同定法を参考に実測により同定した。同定したEMCマクロモデルとPDNの線形等価回路を使い、ボード上の電源供給回路にローパスフィルタを挿入した場合について、相関電力解析で得られる相関係数を予測した。予測された相関係数は、同じフィルタ条件において実測したサイドチャネル信号を相関電力解析した時の相関係数とよく一致した。この結果は、暗号モジュールのサイドチャネル攻撃に対する安全性予測において、EMCマクロモデルを用いた等価回路解析が有効であることを示している。

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開催年月日： 2012年8月28日

記述言語：日本語  

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開催年月日： 2012年6月15日

記述言語：日本語  

電子機器の省エネ化か進むなかで電力変換回路から発生する伝導妨害波の低減設計が重要となっている。伝導妨害波は規制値内に収めらければならない。本報告では、IC/LSIのEMCマクロモデルであるLECCSモデルをベースに構築した伝導妨害波を予測するための線形等価回路モデルについて述べる。またモデル構築のために作製したDual Port LISN(DP-LISN)についても報告する。今回はEUTに卓上IHを使用した。線形等価回路モデルの定数はDP-LISNの負荷抵抗を切り替えることで10組の負荷条件で伝導妨害波電圧を測定し、それらの最小二乗近似により決定した。構築した線形等価回路モデルを用いて伝導妨害波電圧シミュレーションを行い、その結果、シミュレーションによる伝導妨害波強度の周波数変化は実測結果と一致した。

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開催年月日： 2012年3月6日

記述言語：日本語  

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開催年月日： 2012年3月6日

記述言語：日本語  

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開催年月日： 2012年3月6日

記述言語：日本語  

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開催年月日： 2012年3月6日

記述言語：日本語  

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開催年月日： 2012年1月26日

記述言語：日本語  

IC/LSIの電源品質(PI)および電磁環境適合(EMC)設計においてパッケージ部のインダクタンスを把握しておくことは重要である。本稿では、既に提案したボード実装状態におけるパッケージインダクタンス測定法について、測定精度を3次元電磁界シミュレーションに基づき検証した。提案法では半導体チップの代わりに伝送線路(LINE)をパッケージ内に埋め込み、測定したいパッケージ構造をLINEの両側に縦続接続した特性を2ポートSパラメータ測定する。取得したSパラメータと先に測定しておいたLINEの特性よりパッケージ部のインダクタンスを算出する。市販の電磁界シミュレータHFSSにおいて提案法を4種類の評価パッケージに適用し、パッケージインダクタンスを測定した。またパッケージ部のみを電磁界解析し別途パッケージインダクタンスを求め、提案法による結果と比較した。その結果、最大0.9nHの誤差で一致した。さらに誤差の原因として電磁界解析用のポートを設置する時に使用するダミーオブジェクトの影響を評価した。その結果、ダミーオブジェクトの使用に起因する誤差は最大0.06nHと十分小さいことを確認した。

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開催年月日： 2011年11月25日

記述言語：日本語  

我々は,モード等価回路による表現に着目し,モード変換に伴い生じる問題の発生メカニズムを明確にし,さらに,効果的な対策を施しやすくすることを目標として検討を行っている.提案法では,別々に構築したノーマルモード,コモンモード等価回路を,モード変換励振源により結び付けることで回路シミュレータにより解くことができる.本稿では,モード等価回路を用いた解析の有効性を調べるため,送受信器間に中継器が存在する場合と電流プローブによりコモンモード励振を行う場合を対象として検討した.ノーマルモード電圧スペクトル,コモンモード電流スペクトルを用いて評価したところ,モード等価回路による解析結果は現象を精度よく再現できることが分かった.

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開催年月日： 2010年

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開催年月日： 2009年3月4日

記述言語：日本語  

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開催年月日： 2009年

記述言語：日本語  

多層プリント回路基板の電源系共振は,グリーン関数のモード展開を適用したポート間インピーダンス解析に高速化手法を適用することで,短時間でその特性を計算することができる.この手法では,電源層にスリットを含む場合も,スリット間の電磁結合を表現するモデルを用いて共振特性が求められる.しかし,このスリットモデルの表現ではスリットが幅を持たないため,複数のスリットがある場合など,スリットの幅が電源層の大きさに影響を与える場合には計算結果が正しくなくなる可能性がある.そこで本論文では,スリット間の電磁結合を表現するため,結合マイクロストリップ線路から求めた等価回路モデルを用いて単一のスリットのみを含むスリットセグメントを構成し,これを電源系共振解析に適用することを検討した.結果として,従来モデルと同等かそれ以上の精度で電源系共振解析が可能であることが分かった.

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開催年月日： 2003年

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開催年月日： 2002年

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開催年月日： 2002年

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記述言語：日本語   会議種別：口頭発表（一般）  

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記述言語：日本語   会議種別：口頭発表（一般）  

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