掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10584970

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10584961

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.23919/emcjapan/apemcokinaw58965.2024.10585053

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記述言語：英語   出版者・発行元：The Institute of Electronics, Information and Communication Engineers  

The direct connection of a micro strip line (MSL)to coupled lines causes a mode transformation that is
proportional to the difference in the equilibria of the lines,
which can be represented by the equilibrium mismatch model.
In this paper, we show that the mode conversion can be
accurately represented by using the staircase approximation to
represent the continuously varying unbalance coefficient as the
distance between the coupled lines and the system ground is
varied. When the coupled lines are placed perpendicular to the
system ground, full-wave calculations show that mode
conversion occurs as the distance between the coupled lines and
the system ground changes. This mode transformation is
represented using an unbalance mismatch model utilizing field
and circuit co-analysis in the commercial simulator HFSS. The
continuous variation of the unbalance factor is represented by
a staircase approximation, and by increasing the number of
steps in the staircase approximation, the peak value of the
spectrum of the DM voltage generated by the common-mode
resonance approaches the value obtained in the full-wave
calculation.

DOI： 10.34385/proc.82.monpm2c.3

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/LEMCPA.2024.3366881

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掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.1109/temc.2023.3345883

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/TEMC.2023.3236674

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope57790.2023.10274220

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241637

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsipi50001.2023.10241643

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記述言語：日本語   出版者・発行元：電子情報通信学会  

損失を有する共振器型フィルタは，回路基板の平行平板共振抑制時におけるオープンスタブ構造からの不要放射が懸念される．本論文では，放射要因ごとに分解したモデルを用いて共振抑制時の放射を評価した結果，当該構造からの放射増は無視できる程度と判明した．

DOI： 10.14923/transcomj.2022bll0005

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/isie51358.2023.10228017

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc57782.2023.10217366

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/comex.2022xbl0101

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

We previously proposed a lossy resonator filter to suppress the parallel-plate resonance of printed circuit boards (PCBs). The filter consists of an open stub (a quarter-wavelength resonator) covered with a ferrite thin film (inducing a small loss). This paper evaluates the effect of the small loss by investigating the suppression of parallel-plate resonance and the unintentional radiation from a PCB with or without the ferrite thin film. An open stub can work as a narrow-band filter but may also work as an antenna and radiate unintentionally, which causes a secondary noise problem at frequencies other than the target frequency of 2.4 GHz. The electric field distribution between the parallel plates and the total radiated power were thus investigated to validate the effect of the small loss of the lossy resonator filter. The results showed that the total radiated power from parallel plates resonating at 2.4 GHz was suppressed by about 12 dB by using open stubs with a resonant frequency of 2.4 GHz, regardless of the presence or absence of the ferrite thin film. At 2.54 GHz, however, the open stubs without ferrite increased the radiated power by about 10 dB, whereas those with ferrite did not increase it at all. It was thus found that the lossy resonator filter could suppress not only the parallel-plate resonance but also unintentional radiation around the target frequency without causing any other problems.

DOI： 10.1109/EMCEurope51680.2022.9901324

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We investigated the prediction of side-channel leak-age on the power delivery network (PDN) outside a cryptographic IC. To predict the leakage, it is necessary to estimate the switching current caused by the switching activity. So far, high temporal resolution estimation based on gate-level logic simulation has been proposed, but due to the decoupling property of the PDN, the switching current leaking out of the IC chip attenuates signif-icantly. Therefore, this paper calculates the mean of the switching currents over the clock period based on register transfer level (RTL) logic simulation, and then approximates it into a triangle waveform. This approach enables us to simulate the switching current faster than with gate-level simulation. In addition, the simulation time is further shortened by calculating the switching current only to the targeted round of a cryptographic algorithm (AES). Switching currents of the previous rounds were given as statistical models with the same sample mean and variance as the targeted round. As a result of simulating the switching current of an FPGA with the proposed method, we were able to obtain the low-order harmonic components of the current in almost the same magnitude as the gate-level simulation. We also simulated correlation power analysis (CPA) results for the printed circuit board on which the FPGA with the AES circuit was mounted, and found that the proposed method could predict the dynamic power supply voltage observed on the board and CPA results with sufficient accuracy.

DOI： 10.1109/EMCEurope51680.2022.9900948

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Once the signal-tu-noise ratio (SNR) of the side- channel (SC) leakage trace is known, the intensity of the SC information leakage source inside the integrated circuit (IC) can be identified from measurements carried out outside the IC, SNR observation of SC leakage can also make it possible to set quantitative design targets to achieve the demanded leakage intensity. We discuss an improved method for identifying the SNR of SC leakage traces composed of multiple transient responses of IC switching current. The IC switching current repeatedly occurs as the IC runs the cryptographic operation since the cryptographic algorithm repeats a set of sub-operations. The method was applied to simulated and measured leakage traces to eliminate the effect of transient IC switching current caused before the target sub-operation was processed. As a result, a transient component more extensive than the signal component of side-channel analysis was identified in the decoupling capacitor configuration, where the convergence of the transient response is slow. In addition, the correlation coefficients obtained by the correlation power analysis, a major side-channel analysis method, were plotted as a function of SNR, and the plot of the simulated traces agreed with the theoretical curve. On the other hand, some errors remained in the plot of the measured traces.

DOI： 10.1109/EMCSI39492.2022.9889660

Scopus

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SPIE  

DOI： 10.1117/12.2660186

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

DOI： 10.1109/lemcpa.2022.3228199

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ic4me253898.2021.9768521

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担当区分：最終著者   記述言語：英語  

担当区分：最終著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc49932.2021.9597127

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/apemc49932.2021.9596844

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper proposes noise-source parameter identification of the noise-source equivalent-circuit model for predicting conducted noise while considering the switching fluctuation of a DC/DC converter. We decomposed measured conducted noise into ripple noise, turn-on spike noise, and turn- off spike noise to prevent the accuracy degradation in the parameter identification. The predicted conducted noise spectra show the error with the measurement was within 3 dB up to 200 MHz, which is more accurate than that in our previous study.

DOI： 10.1109/emc/si/pi/emceurope52599.2021.9559182

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To estimate the amount of noise suppressed by lossy resonator filters (LRFs) in a power bus with a decoupling capacitor, we used an equivalent circuit model considering the effect of the capacitor to know the suppression mechanism using the LRF. The discrepancy between the model and a full-wave simulation was approximately 2 dB.

DOI： 10.1109/emc/si/pi/emceurope52599.2021.9559213

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>The plain bend in a pair of differential transmission lines causes a path difference, which leads to differential-to-common mode conversion due to the phase difference. This conversion can cause serious common-mode noise issues. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion and derived the constraint conditions for high-density wiring. To provide sufficient suppression of mode conversion, however, the additional correction was required to make the effective path difference vanish. This paper proposes a practical and straightforward design methodology by using a very tightly coupled bend (decreasing the line width and the line separation of the tightly coupled bend). Full-wave simulations below 20GHz demonstrated that sufficient suppression of the forward differential-to-common mode conversion is successfully achieved as designed. Measurements showed that our design methodology is effective.</p>

DOI： 10.1587/transcom.2020ebp3056

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>Side-channel (SC) leakage from a cryptographic device chip is simulated as the dynamic current flowing out of the chip. When evaluating the simulated current, an evaluation by comparison with an actual measurement is essential; however, it is difficult to compare them directly. This is because a measured waveform is typically the output voltage of probe placed at the observation position outside the chip, and the actual dynamic current is modified by several transfer impedances. Therefore, in this paper, the probe voltage is converted into the dynamic current by using an EMC macro-model of a cryptographic device being evaluated. This paper shows that both the amplitude and the SC analysis (correlation power analysis and measurements to disclosure) results of the simulated dynamic current were evaluated appropriately by using the EMC macro-model. An evaluation confirms that the shape of the simulated current matches the measured one; moreover, the SC analysis results agreed with the measured ones well. On the basis of the results, it is confirmed that a register-transfer level (RTL) simulation of the dynamic current gives a reasonable estimation of SC traces.</p>

DOI： 10.1587/transcom.2020ebp3015

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電気学会  

<p>When a shielded-twisted-pair (STP) cable is connected with a printed circuit board (PCB) via an Ethernet (RJ45) connector, mode conversion between primary- and secondary-common modes occurs at the connector section due to their structural difference that causes the difference in the imbalance factor of the transmission line. In this paper, we investigate the suppression of the mode conversion at the connector section by using a modal-equivalent circuit model based on imbalance matching. We focus on improving the PCB pattern below the shielded Ethernet connector by placing a copper layer on the PCB surface, and the inadequate shielding at the connector section by soldering and wrapping with copper tape. The application of this improvement based on imbalance matching at the connector section makes the imbalance factor of the connector section closer to that of the cable section and results in the suppression of the mode conversion. Based on the concept of imbalance matching, we confirmed the effect of the shield-improved connector with an improved PCB pattern on the suppression of the mode conversion at the connector section through circuit simulation and measurement, and it was validated that the circuit simulation results obtained from the modal-equivalent circuit model agree well with the measurement results.</p>

DOI： 10.1541/ieejfms.140.586

CiNii Article

CiNii Books

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/emceurope48519.2020.9245855

J-GLOBAL

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

As the conducted disturbance of a power converter changes with its load value, the relationship between the electromagnetic interference of the power converter and its load needs to be investigated. This work examines a 2-port equivalent circuit model for a DC/DC buck converter with consideration of the load effect. Factors that influence the model accuracy are also discussed. We used a synchronous buck converter operating under a continuous conduction mode condition to determine the load effect and evaluate the model. Results showed that the input port of the fixed-load model and load-variable model had good accuracy up to 70 MHz. We also predicted the load effect on input port noise and found that the input port noise of an 8.2-? load could be predicted from the other two load values (6.6 ? and 11.6 ?).

DOI： 10.1109/emceurope48519.2020.9245680

Scopus

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Symmetry is important for differential-transmission lines, but the dense parallel traces easily break the symmetry due to coupling with the adjacent conductor, leading to mode conversion. We propose an asymmetric geometry of differential-transmission lines placed on the side of a nonadjacent conductor to suppress mode conversion and maintain signal integrity in the cases of loosely coupled and tightly coupled parallel traces. By designing the asymmetric geometry of dense differential-transmission lines by taking into account coupling with the adjacent conductor, mode conversion was successfully suppressed by decreasing the line width on the side of the non-adjacent conductor. It was also found that the asymmetric geometry can suppress mode conversion and maintain signal integrity in tightly coupled parallel traces. In loosely coupled parallel traces, on the other hand, the tightly coupled asymmetrically tapered bend we previously proposed suppresses mode conversion.

DOI： 10.1109/emceurope48519.2020.9245880

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emcsi38923.2020.9191655

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人 電子情報通信学会  

<p>Asymmetry of differential transmission lines over a meshed ground plane causes differential skew, which leads to signal integrity issues. We measured to evaluate how the angle between the differential transmission lines and meshed ground (the rotation angle) affected differential skew. We also investigated the effect of the lines' position on characteristic impedance and the feasibility of high-density layout of the differential transmission lines, including the bend structure. We found that the differential skew and characteristic impedance are not significantly affected by the position of the differential transmission lines and meshed ground when the rotation angle is set to 30°, a relatively small value. Measurements showed that our design is effective.</p>

DOI： 10.1587/elex.17.20200101

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：OPTICAL SOC JAPAN  

Visualization of an electromagnetic field distribution is helpful for spatial evaluation of field leakage and can aid in solving inverse problems of signal-source estimation. Optical detection is more accurate and less invasive than other methods owing to a low metal content in the sensing probes and signal wires. We have previously reported optical detection of alternating magnetic fields using an alkali-metal atomic magnetometer. In this study, we have proposed a method for imaging the field in a 10 mm diameter area in the sensor head and achieved a resolution below 0.3 mm using a digital micro-mirror device. In this paper, we demonstrate the visualization of an alternating magnetic field at 70 kHz, generated using a Helmholtz coil and a 0.5-mm diameter metal wire attached to the sensor head. Both the uniform field image from the coil and the gradient field image from the wire were clearly observed. The output linearity of the magnetometer was investigated by varying the electric current applied to the coil. In addition, we performed signal-source estimation from the gradient field image. The obtained and calculated distributions were compared to estimate the position of the wire. The estimated wire depth of 1.41 mm was within the range of actual wire depths. This measurement technique has the potential for application in precise position estimation of signal sources with high sensitivity.

DOI： 10.1007/s10043-020-00591-y

Web of Science

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

<p>ケーブル-コネクタ間の平衡度不整合によるコモンモード発生、さらに、放射シミュレーションを行うには、コネクタの電流配分率を容易に算出できることが不可欠である。今回、コネクタのSパラメータから電流配分率を算出する簡易モデルを構築したのでこれを報告する。</p>

DOI： 10.11486/ejisso.34.0_3B4-03

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2019.8871971

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Visualizing an AC magnetic field distribution is valuable to evaluate spatially as signal or noise components and to estimate locations of signal sources. We propose an optical imaging technique to visualize AC magnetic field distributions. An atomic magnetometer with phase sensitive detections realize optical detections of the AC field with dividing into two axes. A digital micro-mirror device enables us to obtain the field image in 10 mm square area with sub-mm spatial resolution. As a result, bi-directional AC-field images from a fine metal-wire were obtained. The obtained images allow us to evaluate field distributions clearly. This imaging technique has a potential for spatial evaluations of AC field from electrical and electronic devices.

DOI： 10.1109/emceurope.2019.8871985

Scopus

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2019.8871562

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers (IEEE)  

A method for optimally designing RL and RC snubber circuits is presented to reduce the electromagnetic interference caused by parasitic LC resonance. The Q factor of the resonance is used as the design criteria. Optimum snubber parameters are determined analytically and uniquely by using a simplified equivalent circuit of the resonant loop and deriving an analytical formula for the Q factor as a function of the snubber parameters. The optimally designed snubbers can adequately adjust the Q factor to any design target. They can also minimize the increases in the negative effects of the snubbers, i.e., overshoot and power loss. The method was applied to RL and RC snubbers to be added to a synchronous buck converter. The effects of the snubbers were reproduced by simulation program with integrated circuit emphasis ( SPICE) simulation to validate the method from the perspective of resonance damping, overshoot, and power loss. The results showed that the damping effects obtained with the optimized snubbers met the Q factor design targets. They also demonstrate that the parameters are optimum in terms of suppressing overshoot and power loss. These results indicate that the method is suitable for optimizing RL and RC snubbers to damp parasitic LC resonance.

DOI： 10.1109/temc.2018.2841424

Web of Science

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担当区分：筆頭著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：筆頭著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

<p>EMI対策および評価コストの削減を目的として，ノイズ源IC毎の放射強度推定法を提案する。この手法はEMI発生要因の1つであるスイッチング電流を振幅変調し，その時の電磁妨害波の時間変化を観測することで得られるノイズ源強度比から各ICの放射強度を推定する。本論文では，プリント回路板に提案手法を適用し，遠方界放射から複数ICによる放射の強度を算出，さらにIC個別に駆動した測定結果と比較し推定精度を評価した。その結果，各ICに起因する放射が同相と見なせる場合に放射強度を高い精度で推定可能であることを示した。</p>

DOI： 10.5104/jiep.22.218

CiNii Article

CiNii Books

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担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）  

J-GLOBAL

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掲載種別：研究論文（国際会議プロシーディングス）  

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

DOI： 10.1109/EMCEurope.2018.8485011

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/emceurope.2018.8485052

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The asymmetry, or imbalance, of a differential-transmission-line pair over a meshed ground plane depending on their position leads to the differential skew. This study is focused on the angle between the differential-transmission-line pair and the meshed ground to investigate the angle dependence of differential skew. In a full-wave simulation after preliminary evaluation by a simple model, it is found that the differential skew does not depend on the position of the differential transmission lines to the pattern of the meshed ground and keeps a comparatively small value at the rotation angle around 30°.

DOI： 10.1109/ISEMC.2018.8394024

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Signal-to-noise ratio (SNR) of side-channel traces leaked from cryptographic ICs can be a candidate of system-designer-friendly design index in security evaluation against the side-channel attack (SCA). A method to calculate SNR of side-channel traces from measured side-channel traces was proposed for the scenario of the byte-by-byte attack on AES cryptographic circuits. The proposed method was a simple extension of an SNR calculation method for the brute force attack scenario proposed in a previous study. Measured SNRs according to the methods were validated by comparison with analytical formulas. Results suggested that the proposed method could provide SNRs of side-channel traces accurately.

DOI： 10.1109/ISEMC.2018.8393880

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

In high speed signal transmissions, glass cloth of the dielectric in printed circuit boards can cause a differential skew. It has been reported that the differential skew is mitigated when the angle between the differential transmission lines and the thread of the glass cloth is around 10°. However, the angle dependence between 10° and 45° and the optimum angle have not yet been investigated. This study focuses on the angle between the trace of the differential transmission lines and the thread of the glass cloth to investigate the angle dependence of the differential skew. We conducted a preliminary evaluation by analytical estimation of the phase delay difference in the differential transmission lines using our simple glass-cloth model. In a full-wave simulation, it was confirmed that the optimum angle between the threads of the glass cloth and the traces of the differential transmission lines is around 40°.

DOI： 10.23919/ICEP.2018.8374316

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

プリント配線板の近接グラウンド幅が変化する差動伝送線路では，線路がグラウンド端に寄るなどの非対称構造によりコモンモード放射が発生する。本論文では，線路が近接グラウンド端近傍に配線されている差動伝送線路を対象に，コモンモード放射の発生量を予測するための平衡度不整合モデルの精度を検証した。放射に最も寄与する全ての導体を同相に流れる2次コモンモード電流に着目し，近接グラウンド端からの距離が異なる試験基板を用いて，平衡度不整合モデル，実験，3次元電磁界解析により2次コモンモード電流変化量を比較した。その結果，提案する平衡度不整合モデルは最大3 dBの誤差で実験および3次元電磁界解析の結果と一致した。

DOI： 10.5104/jiep.21.178

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To identify semiconductor devices that are dominant noise sources at low cost in order to reduce electromagnetic interference (EMI), we propose a method based on a noise source amplitude modulation technique and correlation analysis (NSM-CA). In this study, we applied the NSM-CA method to a printed circuit board (PCB) with multiple integrated circuits (ICs) and identified ICs dominantly contributing to EM emission. The switching currents produced in three of the ICs were modulated in amplitude with three different modulation signals. The noise source amplitude modulation was implemented in an FPGA, mounted on a PCB, by using three pseudorandom binary sequences (PRBSs) as modulation signals. During the modulations, EM emission was measured at frequencies where the emission exceeded the limit of EMI regulation. The temporal variation in the measured emission was correlated with each of the PRBSs. The ranking of the contributions of the ICs to the emission was determined by means of the resultant correlation coefficients. According to the ranking, the dominant ICs to which a combination of EMI reduction techniques should be primarily applied were identified. Moreover, we applied an EMI reduction technique to the dominant ICs and found a larger reduction in emission than when the technique was applied to low priority ICs.

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.11486/ejisso.32.0_316

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Pseudo-random binary sequence (PRBS) was applied to identify dominant noise sources of electromagnetic interference (EMI) radiated from a printed circuit board (PCB) including line driver ICs. The ICs were controlled in activation of output according to a set of PRBSs that varied amplitude of switching current generated in the ICs and also changes the strength of EMI. Correlation coefficients between the temporal variation of conducted EMI strength and PRBS were examined. Results showed that PRBS has a potential to identify dominant noise sources of EMI.

DOI： 10.1109/ICCE-China.2017.7991087

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Improving the countermeasures against side-channel attacks (SCAs) increases the cost of both designing the countermeasures and evaluating SCA resistance. This may force cryptographic ICs to remain vulnerable. The increased cost is due to an indispensable procedure where a large number of side-channel traces need to be analyzed in order to evaluate the SCA resistance. In this work, a low-cost method to design and evaluate countermeasures using the signal-to-noise ratio (SNR) of side-channel traces as design and evaluation criteria is proposed. The method combines two existing methods: A prediction method of correlation coefficients between side-channel traces and a power model based on the SNR of the side-channel traces, and an estimation method of the number of traces needed to disclose the secret key based on the correlation coefficients. We construct a method to measure the SNR of side-channel traces and validate it for the design and evaluation criteria. In our method, the SNR is first calculated from signal and noise variances extracted from side-channel traces by increasing the number of averaging in side-channel trace measurements, and then the correlation coefficients and the number of traces for key-disclose are estimated on the basis of the calculated SNR. We confirmed that the estimated correlation coefficient and the number of traces for key-disclose were in good agreement with the corresponding measured ones. This result demonstrates that the proposed method can accurately measure the SNR of side-channel traces.

DOI： 10.1109/APEMC.2017.7975433

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The miniaturization of unit cells in planar electromagnetic bandgap (EBG) structures has been difficult because the stopband frequency depends on the unit-cell size. To solve this problem, we developed an EBG structure that uses two power planes (dual power plane: DPP) with the addition of a capacitive coupling element. This enables us to easily enlarge the capacitance formed in the unit cell and achieve miniaturization with a stopband frequency of interest. Using full-wave simulation, we tested a 2-mm-square (4-mm2) unit cell of the DPP-EBG structure and measured a stopband frequency around 2.4 GHz.

DOI： 10.1109/APEMC.2017.7975472

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.11486/ejisso.31.0_311

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

The bend in a pair of differential transmission lines on printed circuit boards causes a path difference, which leads to mode conversion due to the phase difference. We previously proposed a tightly coupled asymmetrically tapered bend to suppress forward differential-to-common mode conversion. In this paper, we propose a design methodology of our tightly coupled asymmetrically tapered bend that limits the bend structure within the area of the original classic bend for high-density mounting. We also evaluated the 45-degree-angle bend formed based on our design methodology and found that the methodology helps improve or maintain its transmission characteristics compared to those of the classic bend.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

To overcome the intra EMC problems in wireless communications, electromagnetic bandgap (EBG) structures can be used to effectively reduce power-bus noise. We previously proposed a vialess open-stub EBG structure. However, it still has the intrinsic disadvantage of a narrow stopband because it uses the open-stub's resonance. Thus, this paper aims to optimize the structural parameters of the vialess open-stub EBG structure to sufficiently suppress power-bus noise in a wider stopband. The structural parameters to determine the noise-reduction performance of the vialess open-stub EBG structure are the branch width rob, the stub width w(s), and the unit-cell length alpha. Rectangular power buses were designed as test vehicles through the analytical approach and used to evaluate the stopband expansion and the noise suppression in the stopband in a full wave simulation. The transmission characteristics showed that, after w(b), W-s, and a are optimized, the stopband is expanded from 0.61 GHz (2.23-2.84 GHz) to 1.56 GHz (2.20-3.76 GHz). In addition, an optimized structure was made that reduced the amount of noise by approximately 10 dB.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

DOI： 10.1109/ISEMC.2015.7256163

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記述言語：日本語   出版者・発行元：The Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.18.279

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記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.18.344

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掲載種別：研究論文（国際会議プロシーディングス）  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

DOI： 10.1109/EMCEurope.2014.6931007

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

DOI： 10.1109/ISEMC.2014.6899067

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Power-bus resonance of printed circuit boards causes electromagnetic interference and detraction of power integrity. To suppress the power-bus resonance, we propose the application of lossy resonators in the power bus. Here, we first explain the concepts of the proposed resonators, focusing especially on the application based on the impedance characteristics. Then, we explain the full-wave simulation conducted to demonstrate that the proposed resonator effectively suppressed power-bus resonance.

DOI： 10.1109/MEMC.2014.6798799

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

バルク電流やバーストといった外乱注入により発生した暗号FPGAの誤動作に関して考察した。特に発生した誤動作の直接原因がクロックグリッチの場合について、まず、外乱によりFPGAのクロック配線にグリッチが重畳することを実験により検証した。次に、発生した誤動作をグリッチ付クロックをFPGAに直接与える構成において再現し、回路動作とグリッチの関係を検証した。以上の実験結果に基づき、外乱によりクロックグリッチが発生した場合の誤動作発生機構、および評価環境における誤動作発生確率を示した。

DOI： 10.11486/ejisso.28.0_63

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation. © 2013 IEEE.

DOI： 10.1109/ISEMC.2013.6670526

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Delta h). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Delta h becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：SOC INSTRUMENT CONTROL ENGINEERS JAPAN  

Side-channel attacks are a kind of cryptanalytic attacks by means of the electric current in the range of radio frequency (RF) leaking out from a cryptographic integrated circuit (IC) and/or the electromagnetic radiation generated by the RF power current. The RF power current is caused by simultaneous switching activities of logic gates during an encryption process operated in the cryptographic IC. The RF power current is a major cause of the electromagnetic interference (EMI). To decrease the RF power current at PCB level can lead to decrease designing costs. As a preparation of applying LECCS models to a cryptographic IC for estimating the RF power current occurred during an encryption process, the model parameters were identified from measurements in this paper. The LECCS models were composed of a current source that expressed the RF power current occurred in the cryptographic circuit and a passive network. The current source identified grown in amplitude 200 ns after the beginning of the encryption process. This agreed to the beginning of the target round. In frequency domain, current spectra were seen at 24 MHz and its harmonics. The authors obtained waveforms of the RF power current from analog circuit simulations with the LECCS model identified, and validated the cryptographic device in security against the side-channel attacks by means of the correlation power analysis (CPA) method. Results of CPA with the simulated waveforms were consistent to CPA results with measured waveforms. These results means that model parameters were identified correctly, and suggests that the LECCS model is effective for validation of cryptographic devices with respect to side-channel attacks.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

We have developed a modal-equivalent-circuit model with mode-conversion sources for clarifying the mode-conversion mechanism and considering countermeasures against common-mode noise by means of circuit analysis based on the proposed model. The modal equivalent circuit is divided into separate normal-mode and common-mode circuits obtained by applying the mode-decomposition technique to an actual circuit. The separate circuits are connected with the mode-conversion sources at the interface where two transmission lines with different current division factors (h) are connected. This model suggests that the mode conversion that occurs is likely related to the common-mode current and the normal-mode voltage at the interface and the difference in the current division factors (Δh). This paper validates the model experimentally. First, it is validated by changing the grounding conditions of a simple cable interconnection system. Next, the mode-conversion mechanism suggested by the mode-conversion sources is experimentally examined by matching on common mode and replacing a two-wire cable with a coaxial cable so that Δh becomes almost 0. Circuit simulation results obtained using the modal equivalent circuit with the mode-conversion sources agree well with measured results and this also demonstrates the model's validity. © 2012 IEEE.

DOI： 10.1109/ISEMC.2012.6351682

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In grounding an STP cable, mode conversion occurs depending on how to ground it. For investigating the mode conversion in a four-conductor transmission-line system that consists of three conductors and the system ground such as the STP cable above the system ground, as shown in Fig. I. we have developed modal equivalent circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in a three-conductor transmission-line system. The modal equivalent circuit consists of three modal equivalent circuits of normal mode (Fig. 2), primary common mode (Fig. 3), and secondary common mode(Fig. 4). In this paper, mode conversion between normal mode and primary common mode was evaluated using mixed-mode S parameters and the measured data validated the modal equivalent circuit. As a result, it was found that mode conversion depends on the imbalance factor and it was examined how to ground for suppressing mode conversion.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In a differential transmission line, a large common-mode current is excited due to its asymmetry. In this paper, the authors demonstrate experimentally the common-mode current and verify the imbalance difference model that was proposed for prediction of the common-mode current reduction. Experimental results show that the reduction of common-mode current of about 20 dB is achieved by changing the position of the transmission line. In addition, the differences that are calculated using the imbalance difference model are in agreement with the measured ones within 2 dB.

DOI： 10.1109/APEMC.2012.6237956

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Side-channel attack is a cryptanalytic attack based on information gained from the physical implementation of a cryptographic IC. The simultaneous switching noise (SSN) current is generated as logic gates in cryptographic IC switch simultaneously in encryption processes. SSN current is a cause of electromagnetic interference (EMI). In this study, linear equivalent circuit modeling was examined for the sake of a developing method to evaluate cryptographic systems before fabrication. A linear equivalent circuit model of a cryptographic FPGA, in which an AES algorithm had been implemented, was determined from experimental measurements. The model was implemented into a commercial analog circuit simulator, and the SSN current was estimated under three configurations among which a decoupling circuit, used as a countermeasure, was changed. Estimated current traces were analyzed statistically by using the correlation power analysis (CPA) method to obtain correlation values, a major index security against side-channel attacks. Variation of the correlation values with a decoupling configuration agreed with the corresponding experimental results also obtained in this study. This means that the security of cryptographic devices against side-channel attacks based on analysis of the SSN current can be estimated by using the equivalent circuit model before fabrication. © 2012 IEEE.

DOI： 10.1109/ISEMC.2012.6351661

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs). We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer. The measured data was evaluated for noise-suppression and PI characteristics. Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit. Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

One of PI/EMC design techniques, on-board decoupling, was proved its possibility to be used as a countermeasure against cryptographic side-channel analysis attack. The on-board decoupling was applied to a side-channel attack standard evaluation board (SASEBO-G) involving a cryptographic FPGA that operated an AES-128 encryption process. Two decoupling conditions were examined. Radio frequency (RF) power current was detected with a current probe that was placed on a power cable connected to SASEBO-G for the cryptographic FPGA. Traces of the RF power current were recorded repeatedly with a digital oscilloscope until 30,000 traces were acquired in each decoupling condition. The traces were analyzed statistically by using the correlation power analysis (CPA). Results of CPA show that necessary number of traces to reveal the secret key significantly increased when the RF power current was attenuated by decoupling over the dominant frequency range in spectra of the RF power current. The decoupling technique can be useful as a countermeasure of side-channel analysis attacks to cryptographic modules. © 2011 IEEE.

DOI： 10.1109/ISEMC.2011.6038441

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator. ©2010 IEEE.

DOI： 10.1109/ISEMC.2010.5711287

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記述言語：日本語   出版者・発行元：一般社団法人 映像情報メディア学会  

多層プリント回路基板の電源系共振は,グリーン関数のモード展開を適用したポート間インピーダンス解析に高速化手法を適用することで,短時間でその特性を計算することができる.この手法では,電源層にスリットを含む場合も,スリット間の電磁結合を表現するモデルを用いて共振特性が求められる.しかし,このスリットモデルの表現ではスリットが幅を持たないため,複数のスリットがある場合など,スリットの幅が電源層の大きさに影響を与える場合には計算結果が正しくなくなる可能性がある.そこで本論文では,スリット間の電磁結合を表現するため,結合マイクロストリップ線路から求めた等価回路モデルを用いて単一のスリットのみを含むスリットセグメントを構成し,これを電源系共振解析に適用することを検討した.結果として,従来モデルと同等かそれ以上の精度で電源系共振解析が可能であることが分かった.

DOI： 10.11485/itetr.33.15.0_25

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Electromagnetic bandgap (EBG) structures that prevent propagation of electromagnetic waves within a given frequency range are quite effective in suppressing simultaneous switching noise on parallel power planes. However, it is quite time consuming to compute the stopband frequencies of interest using full-wave electromagnetic simulation of the entire structure. In contrast, using dispersion-diagram analysis based on a unit-cell network of EBG structures is more efficient and less time consuming. This paper presents an approach for two-dimensional EBG structures by extending a well-known dispersion-diagram analysis of one-dimensional infinite periodic structures. The stopbands predicted with the proposed analysis were compared with good agreement to measured and simulated results. In addition, the concept was applied to test the stopband range of EBG structures formed on an actual printed circuit board with a test coupon of an EBG unit cell placed on the same board.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Is proposed an approach to know magnitudes of parasitic electromagnetic modes excited by the micro-strip line passing over a slit in the return plane. A part of the power having been carried along, the microstrip-line is transferred to the coplanar-line modes along the slot, and the cylindrical. mode in between the pair of re. turn and ground planes. Magnitudes of those modes are expressed by the ratio of powers of the excited electromagnetic mode to the original microstrip line mode, discarding information of phase. Calculation was done with FDTD in the limited domain., around the cross-point in a moderate time of calculation. This approach contributes to the efficient designing of PCB of commercial electronic devices.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Electromagnetics Academy  

Printed circuit boards (PCBs) sometimes have a separated power or ground plane. Differential mode having been propagated along the microstrip line is divided into multiple modes when the differential mode arrives at the intersection of the signal line and the slit. They are differential mode that reflects backward and runs through, slot line mode and parallel plane mode. In order to evaluate excitation of undesirable electromagnetic modes, "transmission factor" is defined as a power ratio of excited mode to incident mode and is expressed in a matrix form like S matrix. The transmission factor is obtained by the electromagnetic calculation near the slit, since it is determined only by the structure of the intersection between the signal line and the slit.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

Power/ground planes in electronic packaging can be a major factor for noise coupling. There can be noise coupling not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. Due to the large size of the power/ground planes, it is difficult to analyze them using full-wave simulators. It is known that the finite difference solution of the Helmholtz equation provides a faster approach with a comparable accuracy. This paper presents new circuit models for a single plane pair based on the finite difference method: T- and X-Models. It also presents a modeling approach for multiple plane pairs that are coupled through apertures.

DOI： 10.1109/emczur.2006.214993

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

Simultaneous switching noise (SSN) is one of the major bottlenecks for successful design of high-performance systems. Especially mixed-signal designs are very sensitive to SSN due to the low voltage levels applied in analog circuits. One way of isolation is by placing the digital and analog domains far from each other. Even then, the power planes can transfer noise voltages both vertically and horizontally through out the board and total board area is a major concern in microminiaturized convergent systems. Electromagnetic bandgap structures (EBG) have been successfully applied for such isolation. Although any periodical shape can be used for isolation, only a few shapes have been reported, with various analysis methods. We present a new EBG with narrow slits, which shows a higher attenuation constant compared with existing structures. We also present a new analysis methodology for 2D EBG structures. Finally, a method to scale such EBG structures for different stopband requirements is introduced. ©2006 IEEE.

DOI： 10.1109/SPI.2006.289196

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Resonance characteristics of gapped power bus structures with a slit or a gap were studied, using a fast algorithm based on a full cavity-mode resonator model and the segmentation method. Inductance and capacitance models were used to account for a field coupling along the slit and across the gap, respectively. The effectiveness of the segmentation method and the inductance model for the slit has been demonstrated by good agreement between the calculated and measured results, while the capacitance model for the gap is shown to be useful when the coupling between the segments is relatively weak.

DOI： 10.1109/TEMC.2005.847414

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In this paper, we describe how we modeled EMI noise from the power-pin current of an LSI that has two ports: a power-ground port and a driver output port. We named this modeling the "Linear Equivalent Circuit and Current Source for I/O (LECCS-I/O)" model and with it measured power current and power-ground impedance for various combinations of loading capacitances and decoupling inductances using a small scale IC (74LVC04). Results showed that up to 500 MHz, the LECCS-I/O model could predict peak and valley frequencies of the power current where the error was within 2.5 MHz, and where the peak current error was less than 5 dB. The application range of the LECCS-I/O model is valid where the non-overlap duration of the dumping oscillation wave between cycles is longer than twice the time constant of the waveform.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：PUBLISHING HOUSE BEIJING UNIV POSTS & TELECOMMUNICATIONS  

One of the major source of radiated EMI is attributed to power bus resonance in a printed circuit board(PCB). A fast algorithm, combined with the segmentation method, is applied for calculating resonance characteristics of a power bus whose pattern consisting of several segments of rectangles and/or right-angled triangles. Good agreements between the calculated and measured results demonstrate the usefulness and accuracy of the fast algorithm and the segmentation method.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Evaluation of common-mode excitation is important to efficiently reduce the EMI radiated from printed circuit boards (PCBs). We have focused on the excitation mechanisms of the common-mode current flowing on a PCB. In a previous paper, we explained a mechanism of common-mode excitation in terms of the current division factor, which expresses the degree of imbalance of a transmission line. The calculation is two-dimensional so the evaluation time is much shorter than that of FDTD or other 3D fullwave simulations. The calculated reduction of common-mode radiation from simple PCBs agreed well with the measured value. In this paper, to demonstrate the effectiveness of this approach, we apply it to various PCBs, such as one that has a signal trace close to a board edge or one with guard bands, and evaluate the effectiveness of the common-mode reduction. Our calculated and experimental results are in good agreement.

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

A new inversion inhomogeneous atmosphere (IA) method that is more stable than Fernald’s method for two-component (molecule and aerosol) scattering analysis of polarized Mie lidar signals is proposed and examined. The backscattering coefficient and the extinction-to-backscattering ratio (EBR) can be calculated for specified regions at which the depolarization ratio is less than that of molecule without further assumptions. The inversion procedure can be extended to both inward stepwise and outward stepwise integration algorithms. Simulation results indicate that a higher precision was achieved with the IA method than with Fernald’s method in terms of error and random noise in estimating boundary value and EBR. Experimental results were also better with the IA method than with Fernald’s method. © 2001 Optical Society of America.

DOI： 10.1364/JOSAA.18.000392

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記述言語：日本語   出版者・発行元：The Vacuum Society of Japan  

DOI： 10.3131/jvsj.38.228

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その他リンク： https://jlc.jst.go.jp/DN/JALC/00032679687?from=CiNii

記述言語：日本語   出版者・発行元：The Vacuum Society of Japan  

DOI： 10.3131/jvsj.38.218

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その他リンク： https://jlc.jst.go.jp/DN/JALC/00032679656?from=CiNii

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担当区分：筆頭著者,　最終著者   記述言語：日本語  

DOI： 10.5104/jiep.25.535

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担当区分：最終著者   記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.5104/jiep.25.439

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記述言語：日本語   出版者・発行元：電気学会  

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：日本語   出版者・発行元：電子情報通信学会  

電磁波による情報通信や電力伝送などの普及により，正確な電磁環境計測の需要が高まっている．我々は，アルカリ金属蒸気の電子スピン偏極を利用した光学式磁界センサの電磁環境計測を目指している．本センサは，コイルを用いた従来のセンサと比較して高い感度や空間分解能を有しており，金属ケーブルなどを用いないため，正確な計測が期待できる．センサの高感度動作には，測定対象周波数に応じた静磁界の印加が必要であり，従来の研究では測定部よりも大きなコイルを用いて空間的に均一な磁界を印加していた．本研究では，20 kHzの交流磁界に対して市販の磁界テスタを用いた感度較正を行い，構築したセンサの線形な出力特性と0.4 nTのノイズレベルを確認した．次に，センサ部分の非金属化と小型化を目的として，静磁界の印加に小型の永久磁石を用いて交流磁界検出を行った．永久磁石を用いて静磁界を印加させることで，理想的な場合と比較すると，信号強度は約81％となり，感度帯域は約126％となった．この原因について，印加される静磁界強度の空間的な不均一によると考察した．

DOI： 10.14923/transcomj.2016pep0010

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：英語  

© 2017 The Japan Society of Applied Physics. We demonstrated optical imagings of AC magnetic fields. A digital micro-mirror device and a lock-in detection allowed obtaining sub-millimeter resolution images without using magnetic shields. Images of gradient field from a wire suggested its potential to apply for signal-source estimations.

DOI： 10.23919/MOC.2017.8244562

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記述言語：日本語   出版者・発行元：[科学情報出版]  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A connector model expressed as an inductance is proposed for use in a previously reported common-mode antenna model. The common-mode antenna model is an equivalent model for estimating only common-mode radiation from a printed circuit board (PCB) more quickly and with less computational resources than a calculation method that fully divides the entire structure of the PCB into elemental cells, such as narrow signal traces and thin dielectric layers. Although the common-mode antenna model can estimate the amount of radiation on the basis of the pin configuration of the connector between two PCBs, the calculation results do not show the peak frequency shift in the radiation spectrum when there is a change in the pin configuration. A previous study suggested that the frequency shift depends on the total inductance of the connector, which led to the development of the connector model reported here, which takes into account the effective inductance of the connector. The common-mode antenna model with the developed connector model accurately simulates the peak frequency shift caused by a change in the connector pin configuration. The results agree well with measured spectra (error of 3 dB).

DOI： 10.1587/transcom.2015EBP3269

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記述言語：日本語   出版者・発行元：Institute of Electrical Engineers of Japan  

In the modal-equivalent circuit derived from the view of the mode-decomposition technique, mode-conversion sources are placed at the interface where the imbalance factor of the transmission lines changes. In addition, the amount of the mode-conversion sources is proportional to not only the difference in the imbalance factor but also the magnitudes of the normal-mode voltage and the common-mode current at the same position. In this paper, therefore, the suppression of mode conversion from normal mode to common mode is experimentally examined by installing a bypass capacitor to power distribution network. The bypass capacitor helps reduce the normal-mode voltage in the vicinity of a connector on a test board where mode conversion occurs so that the common-mode current flowing a power-line cable and the electric field far from the test board are decreased. In fact, the mode conversion was most suppressed when the bypass capacitor is placed closest to the connector on the test board. Also, it was found that the mode conversion was suppressed by the capacitor installed to the power-line cable in the vicinity of the connector.

DOI： 10.1541/ieejfms.136.25

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記述言語：日本語   出版者・発行元：Institute of Electrical Engineers of Japan  

Cryptographic circuits were analyzed regarding their side-channel information leaking behavior based on internal current source. Cryptographic circuits were implemented in an FPGA with registers arranged to demonstrate three known side-channel information leaking behaviors
(1) leakage is reduced by making Hamming distance (HD) at registers constant, (2)leakage increases with signal-to-noise ratio of side-channel traces, and (3) unbalance of routing path from registers to load circuits produces leakage. The implemented circuits were measured in terms of voltage fluctuation in the power distribution network for FPGA core circuit where the circuits were implemented. The measured voltage fluctuations were converted into internal current sources that were exploited to analyze the information leaking behavior by applying a side-channel analysis, correlation power analysis (CPA). The analysis confirmed that internal current source clearly demonstrated the side-channel information leaking behaviors. This results suggests that internal current source would allow to understand what parts of encryption circuits largely contribute to leak information and how to develop an efficient and low-cost countermeasure against side-channel attacks.

DOI： 10.1541/ieejfms.136.365

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a tightly coupled asymmetrically tapered bend to suppress differential-to-common mode conversion caused by bend discontinuity in a pair of differential lines. Tightly coupled symmetrically tapered bends have been so far proposed to suppress the mode conversion by decreasing the path difference in the bend. This approach makes the path difference shorter so that the differential lines are coupled more tightly but the path difference of twice the sum of the line width and the line separation still remains. To suppress the remaining path difference, this paper introduces the use of asymmetric tapers. In addition, two-section tapers are applied to reduce differential-mode reflection increased by the tapers and hence improve differential-mode propagation. A full-wave simulation of a right-angled bend demonstrates that the forward differential-to-common mode conversion is decreased by almost 30 dB compared to the symmetrically tapered bend and that the differential-mode reflection coefficient is reduced to the same amount as that of the classic bend. Also, the generality of the proposed bend structure is discussed.

DOI： 10.1587/transcom.E98.B.1188

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記述言語：英語   出版者・発行元：電子情報通信学会  

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

周期構造による電磁バンドギャップ(Electromagnetic Bandgap: EBG)形成(EBG構造)により,プリント回路基板の電源-グラウンド層間の高周波ノイズを低減する検討が行われている.EBG構造はその抑制量が非常に大きいため,デジアナ混載基板において微弱な信号を扱う高周波回路部に対してディジタル回路部で発生する同時スイッチングノイズの伝搬抑制に有効である.EBG構造には様々な形状があるが,大まかにはビアの有無で分類できる.我々は,ビアの無いプレーナ型EBG構造に着目して高周波ノイズの抑制を検討してきた.これは2層で構成でき,ビアが不要であることからコスト面からも有利と考えられるためである.一方,ビア有りのEBGで提案されているオープンスタブEBGは抑制周波数に依存せず小型化が可能である.オープンスタブEBG構造はビア有りに特有の構造と考えていたが,本報告では,構造を工夫することでビア無しのプレーナ型オープンスタブEBG構造を提案する.そして,電磁界シミュレーションによりその抑制効果を調べ,2.4GHz帯においてそれを確認した.

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記述言語：英語   出版者・発行元：IOP PUBLISHING LTD  

The effect of Mg loading on the high-frequency tunable properties and dielectric loss of Ba0.8Sr0.2Ti1-xMgxO3 (BSTM) ceramics was investigated. Variation in the lattice parameters and the 90 degrees domain configuration with Mg loading indicated a decrease in the tetragonal distortion. Additionally, the 90 degrees domain size decreased slightly with a low Mg loading, up to 0.1 mol %, resulting in a higher domain-wall density compared with the non-doped specimen. The 0.075 mol% Mg-loaded BSTM ceramic exhibited the highest tunability; this was attributed to the domain-size effect. The loss tangent (tan delta) roughly decreased with Mg loading, due to loaded oxygen vacancies. The maximum figure of merit value (FOM = tunability/tan delta) at 10 MHz was achieved for the 0.075 mol% Mg specimen, twice that of the non-doped specimen, due to an increase in the tunability and a decrease in the loss tangent with Mg loading. (C) 2015 The Japan Society of Applied Physics

DOI： 10.7567/JJAP.54.011502

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記述言語：日本語   出版者・発行元：[科学情報出版]  

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記述言語：英語   出版者・発行元：IEEE  

This paper describes a proposed planar electromagnetic bandgap (EBG) structure whose unit cell size is miniaturized through the use of interdigital electrodes (IDEs). For planar EBG structures in general, it is difficult to miniaturize the cell size independently of stopband frequency because the stopband frequency depends on the cell size. For the proposed structure, however, the cell size can be miniaturized because the IDEs help enlarge the capacitance between adjacent unit cells and utilize a resonator formed in the unit cells. Because the resonator's resonant frequency determines the stopband frequency of an EBG structure with IDEs, the cell size can be miniaturized independently of the stopband frequency. In the work described in this paper, the proposed EBG structure's efficacy in reducing power bus noise was examined and evaluated through full-wave simulation and measurement in the wireless communication band. It was found that an IDE-EBG structure with a small (25 mm(2)) unit cell is a valid means for achieving power bus noise reduction.

DOI： 10.1109/EDAPS.2015.7383703

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記述言語：英語   出版者・発行元：IEEE  

This paper formulates mode conversions of transmission and reflection from differential mode to common mode in differential transmission lines with bend discontinuity using a very simple model. The formulae tell us that the mode conversion is caused by not only the path difference in the bend but also the difference between the characteristic impedance and port impedance. The formulae were validated by full-wave simulation under the assumption that effect of the bend region is small and results showed that path difference reduction and impedance matching at the input and output ports are significant in suppressing mode conversion. This suggests that the tightly coupled asymmetrically tapered bend proposed by the authors should be effective for suppressing mode conversion.

DOI： 10.1109/EDAPS.2015.7383689

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記述言語：英語   出版者・発行元：IEEE  

Electromagnetic immunity analysis as well as electromagnetic emission analysis is significant for EMC design. In this paper, we apply a modal equivalent-circuit model with mode-conversion sources to electromagnetic immunity analysis in a simple cable interconnection system. The analysis can treat mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis and has been validated in electromagnetic emission analysis. The approach takes an advantage in less calculation sources and helps get design considerations compared with full-wave simulation. In this paper, common-mode excitation by a current probe in a simple cable interconnection system is investigated for model validation. As a result, it is demonstrated that the circuit analysis with the modal-equivalent circuit model agrees well with the measurement results.

DOI： 10.1109/APEMC.2015.7175388

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記述言語：英語   出版者・発行元：IEEE  

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

DOI： 10.1109/ISEMC.2015.7256163

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

ディジタルICの電源供給回路(PDN)で発生する共振を抑制する手法としてRLスナバが提案されている。本報告ではプリント基板上のPNDに挿入するRLスナバの実装位置について検討した。実装位置として部品や配線の実装密度が高いIC近傍と、密度が小さい遠方について、PDN共振周波数における電源系高周波電流の抑制効果を比較した。2つの実装位置について抵抗値とインダクタンスの最適値を決定し、それらで構成するRLスナバをインバータICのPDNに実装した。さらに電源系高周波電流を測定し、2つの実装位置による共振電流低減効果を比較した。その結果、異なる実装位置でも同レベルの低減効果を実現できることを確認した。この結果は回路シミュレーションの結果とも一致した。よって、オンボードRLスナバはボード上の部品や配線の実装状況に応じて実装位置を柔軟に設定でき、かつ、実装位置に関係なく一定の共振抑制効果を得られる。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

多線条線路の不連続,すなわち,配線の断面構造変化によりモード変換が生じる.これは,ノーマルモードノイズが伝搬すると,この不連続位置でのモード変換によりコモンモードノイズが発生して不要電磁放射(Electromagnetic Interference: EMI)につながる.電源系配線に着目した場合,DC-DCコンバータのスイッチングによる高周波ノイズが最近では問題となっており,EMI低減のための効果的な抑制法の検討は重要である.線路の不連続位置におけるモード変換では,その位置のノーマルモード電圧に比例してコモンモードが励振される.信号配線と異なり,電源系配線ではコンデンサを挿入することで高周波のノーマルモード電圧が効果的に低減できる.本稿では,線路の不連続が生じるコネクタと実装するコンデンサとの間の距離を変えて不連続位置近傍のノーマルモード電圧の低減量,ならびに,系を流れるコモンモード電流,系から放射される電界の低減量の関係を調べた.結果として,ノイズ源であるDC-DCコンバータ近傍より,コネクタ近傍にコンデンサを配置する方がよりモード変換を抑制し,コモンモード電流,および,放射電界を低減できることを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電子機器の多層プリント回路基板における電源/グラウンド層の高周波ノイズ伝搬を抑制する目的で,損失を有する共振器型フィルタをこれまでに提案している.この共振器型フィルタは周波数選択性を有し,内包する共振器の共振周波数を変えることでノイズ伝搬を抑制する周波数域を任意に設定できる.さらに,共振器に与えた損失により除去したノイズの再放出を生じさせない.本稿では,この損失を有する共振器型フィルタを,フェライト薄膜とオープンスタブによりプリント回路基板上に実現した.そして,電磁界シミュレーションと実測で得られた透過特性を調べることで,電源/グラウンド層間を伝搬するGHz帯の高周波ノイズの抑制効果を評価した.その結果,所望のノイズ抑制効果を確認した.さらに,電源/グラウンド層が多層プリント回路基板内部に形成された場合も内層のグラウンド層と共振器型フィルタのグラウンド層をビアで接続してノイズをフィルタに伝えることで,電源/グラウンド層間のノイズを抑制することができた.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

本報告では,電子機器のイミュニティ試験における外来妨害波の伝達過程解明を目的とし,妨害波の注入環境を変化させたときにボード上で観測されるノイズの変化を観測した.実験系は電気的ファストトランジェント/バースト(EFT/B)試験器,結合回路,プリント回路基板(Printed Circuit Board: PCB)で構成した.結合回路には結合・減結合回路網(Coupling Decoupling Network: CDN),またはカレントプローブを使用し,バーストパルスを電源ケーブルより注入した.その結果,正パルスを注入するとPCBに実装されたICの電源電圧が変動した.バーストパルスによりPCB上に発生するノイズ波形は結合回路によって変化した.この原因として,EFT/B試験器から見た入力インピーダンスの変化に言及した.さらに,PCBグラウンドのシステムグラウンドへの接地による特定周波数で変動するノイズの現象を観測した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

我々は暗号IC内部で発生するスイッチング電流を等価電流源として同定している,内部等価電流源を調べることにより暗号ICのサイドチャネル攻撃に対する安全性を評価でき,効果的な安全設計実現を期待できる.本稿ではサイドチャネル攻撃対策を付加したAES回路と未付加の回路をFPGA実装し,暗号処理に伴って発生するスイッチング電流の情報漏洩源としての挙動を,内部等価電流源に基づき調べた.結果,レジスタ遷移より前に電流値の分散が小さくなる時間が存在し,その時刻において電流値と中間値HDとの相関が高くなり,情報漏洩が発生していることを確認した.内部等価電流源を利用することにより,暗号IC内部の情報漏洩源としての挙動をより詳細に分析できる可能性を示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板上のノーマル・コモン両モード間のモード変換が原因となって生じる不要電磁放射(コモンモード放射)に注目し,コモンモードアンテナモデルを用いた放射量シミュレーションを検討している.コモンモードアンテナモデルは,線路の電流配分率とノーマルモード電圧から求めたモード変換励振源を起電力とする等価アンテナモデルである.このときノーマルモード電圧にモード等価回路モデルより求めた伝送線路解析結果を用いることで両モード間のモード変換を考慮する.これまでの手法ではモード等価回路を繰り返し解析する必要があり,繰り返し回数が少ないと十分な計算精度が得られず,また計算時間が増大する問題もあった.本報告では伝送線路解析上でモード等価回路を同時解析するようにシミュレーション手法の改良を行った.これによって計算時間は短縮された.改良した手法では繰り返し解析の場合に比べて放射量シミュレーション精度も向上し,特に放射のピーク周波数付近では実構造モデルと比較して誤差1dB以下の精度まで改善することができた.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板上の差動線路の屈曲部では,線路間に経路差が生じ,この経路差により生じる各線路の信号伝搬に伴う位相差がモード変換を生じさせる.そこで,本稿では,モード変換を抑制した屈曲構造を提案する.それは,これまでに提案されている対称テーパ付密結合屈曲構造のテーパを非対称にし,密結合屈曲部に残された経路差を打ち消すもので,モード変換量は対称テーパの場合に比べて約23dB低減した.さらに,非対称テーパを2分割にすることでディファレンシャルモードの特性インピーダンスをテーパの途中で変わらず一定値なるようにして,反射は約10dB減少した.

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記述言語：英語   出版者・発行元：IEEE  

For suppressing the power-bus resonance at higher frequencies, which causes propagation of electromagnetic noise and detraction of power integrity, we proposed a lossy resonator filter with frequency selectivity and low loss. To suppress noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), a ferrite-covered open stub was formed on a PCB as a lossy resonator filter. Its characteristics were verified by not only full-wave simulation but also measurement using a vector network analyzer. The simulation and measurement results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Through a series of investigations focusing on the input impedance characteristics, this paper clarified that low impedance of the open stub around resonant frequency helps prevent the impedance of the power-ground plane pair from increasing due to parallel plate resonances to achieve power-bus noise reduction.

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記述言語：英語   出版者・発行元：Journal of the Japan Society of Powder and Powder Metallurgy  

To confirm the feasibility of suppressing electromagnetic interference (EMI) in the inner layers of multilayered printed wiring boards (PWBs) and sustaining power integrity characteristics, influence of inserting a ferrite-plated thin film between the power and ground planes on the transmission characteristics were evaluated using four types of test boards with the following two conditions: one is the solid test board with a plane copper foil or the EBG (Electromagnetic bandgap) test boards with a one-dimensional lattice-shaped EBG structure consisting of large and small squares 15 mm x 15 mm and 1.5 mm x 1.5 mm in size
the other is whether the 3 or 6 μm-thick ferrite film was deposited or not. The multiple peaks of the transmission coefficient S21 due to parallel plate resonances were observed in the solid test board without ferrite film but the peaks were suppressed over the wide frequency range up to 6 GHz by applying the ferrite film. The EBG test board with the ferrite film provided not only wideband attenuation owing to the ferrite film but also large attenuation in the EBG stopband. The multiple peaks of in the driving point impedance Z11 due to the parallel plate resonances were also successfully suppressed by applying the ferrite film exhibiting favorable power integrity characteristics.

DOI： 10.2497/jjspm.61.S299

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記述言語：英語   出版者・発行元：IEEE  

A tightly coupled asymmetrically tapered bend to suppress differential-to-common-mode conversion (caused by bend discontinuity in a pair of differential transmission lines) is proposed. A tightly coupled tapered bend has been proposed to suppress the mode conversion by decreasing the path difference in the bend. The tightly coupled bend with symmetric tapers makes the path difference shorter so that the differential transmission lines are coupled more tightly, but a path difference of twice the line separation still remains. To decrease the remaining path difference, a pair of asymmetric tapers is proposed. A full-wave simulation demonstrated that the amount of differential-to-common-mode conversion was decreased by 29 dB compared to that of the symmetrically tapered bend. To suppress differential-mode reflection, furthermore, a tightly coupled bend with sectionally divided asymmetric tapers is suggested.

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記述言語：英語   出版者・発行元：IEEE  

We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter diagrams of the Hamming Distance (HD) of AES intermediate values and the current magnitudes. The obtained leakage functions were confirmed a well-known assumption on the HD power model that magnitude of switching current due to transition of register states is proportional to HD of the register. The internal current was also investigated in terms of correlation with the HD model. Correlation coefficients increased as transforming the external power trace in the internal current because two types of noise were reduced by the transform; constant noise and overlap effect of successive rounds. The noise reduction inferred that the use of the internal current source would provide more precise verification of countermeasures.

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記述言語：英語   出版者・発行元：IEEE  

The equivalent-circuit expression of bend discontinuity in differential transmission lines, which is derived from the view of the mode-decomposition technique, is proposed in this paper. We investigated the relationship between the amount of mode conversion in the bend region and two components in the modal equivalent circuit: the mode-conversion sources and the modal reactances (modal inductances and capacitances). As a result, it was found that not only the difference in the imbalance factor but also the magnitude of the modal reactances can have a lot of effect on the mode conversion.

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記述言語：英語   出版者・発行元：IEEE  

A lossy resonator filter with frequency selectivity and low loss, which suppresses noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), was fabricated and evaluated. A ferrite-covered open stub was formed on a PCB as a lossy resonator filter, and its characteristics were verified by measurement using a vector network analyzer as well as full-wave simulation. The measurement and simulation results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Even in the case that the power bus is inside the board, noise propagation in the power bus was suppressed by connecting the inside ground plane and the ground plane of the lossy resonator filter by vias in order to conduct the noise to the filter.

DOI： 10.1109/EMCEurope.2014.6931007

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記述言語：英語   出版者・発行元：IEEE  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace close to the return edge on a printed circuit board. Our previous studies on the guard trace focused only on a design methodology for reducing common-mode radiation, but the placing guard trace close to the signal line increases crosstalk to deteriorate signal integrity. A guard trace with a periodic structure is therefore proposed for simultaneously reducing common-mode radiation and maintaining signal integrity. Several test boards with different period patterns were evaluated by measurement and full-wave simulation from the viewpoint of transmission coefficient as well as common-mode radiation. As a result, it was found that the guard trace with the periodic structure helps reduce common-mode radiation and maintain signal integrity except for a couple of conditions.

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記述言語：英語   出版者・発行元：Journal of the Japan Society of Powder and Powder Metallurgy  

To confirm the feasibility of suppressing electromagnetic interference (EMI) in the inner layers of multilayered printed wiring boards (PWBs) and sustaining power integrity characteristics, influence of inserting a ferrite-plated thin film between the power and ground planes on the transmission characteristics were evaluated using four types of test boards with the following two conditions: one is the solid test board with a plane copper foil or the EBG (Electromagnetic bandgap) test boards with a one-dimensional lattice-shaped EBG structure consisting of large and small squares 15 mm x 15 mm and 1.5 mm x 1.5 mm in size
the other is whether the 3 or 6 μm-thick ferrite film was deposited or not. The multiple peaks of the transmission coefficient S21 due to parallel plate resonances were observed in the solid test board without ferrite film but the peaks were suppressed over the wide frequency range up to 6 GHz by applying the ferrite film. The EBG test board with the ferrite film provided not only wideband attenuation owing to the ferrite film but also large attenuation in the EBG stopband. The multiple peaks of in the driving point impedance Z11 due to the parallel plate resonances were also successfully suppressed by applying the ferrite film exhibiting favorable power integrity characteristics.

DOI： 10.2497/jjspm.61.S299

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記述言語：英語   出版者・発行元：IEEE  

The guard trace is effective for suppressing common-mode generation caused by placing a signal trace too close to the return edge on a printed circuit board. In our previous study, a guard trace with a periodic structure was proposed not only to reduce common-mode radiation but also to maintain signal integrity and was found to be effective. In the current work, the shape of the periodic structure and the termination at both edges to improve the features was investigated through full-wave simulation and measurement from the viewpoint of transmission coefficient as well as far-field radiation. Results show that the smaller the widths of the narrow portion, the further the periodic structure helps reduce common-mode radiation and maintain signal integrity. Also shown is that the periodic guard trace with both ends connected to the return plane is an appropriate structure.

DOI： 10.1109/EDAPS.2014.7030811

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板上の差動線路の屈曲部をインダクタとキャパシタというリアクタンス素子からなるT型の構造で表現した後,これらが縦続接続されていることに注目し,モード等価回路として表現した.そして,屈曲部に含まれるモード変換励振源やその周囲に配置されたリアクタンス素子とモード変換量の関係を調べた.その結果,平衡度差だけでなくリアクタンス素子の大きさもモード変換量に影響を与えることが分かった.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板に搭載されているFPGAのECCSモデルを同定し,IC/五SIの高周波電流に起因する電源電圧変動を予測した.まず,FPGAのECCSモデルと電源供給回路の線形等価回路をオンボード測定より同定した.同定したECCSモデルは,FPGAで発生する高周波電流を等価電流源で表現している.次に,ECCSモデルとPDNの等価回路とを組み合わせ,回路シミュレーションにより電源電圧変動を予測した.今回は,入カデータ1,000通りに対して電源電圧変動の予測が可能か確認を行った.その結果,シミュレーションと測定した電源電圧変動の相互相関は1,000通りの入力データ全てに対して0.8以上の高い値を示した.これより,ECCSモデルは電源電圧変動予測に適用可能であり,かつ入力データ依存も予測できる可能性を示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

ICの電源供給回路に寄生するインピーダンスの共振により,直流電源側に漏れ出す高周波電流や電源バウンスの発生原因となる入力インピーダンスが増加する.この問題の解決を目的として,デカップリングインダクタと並列に抵抗を挿入する共振抑制手法,RLスナバ回路を検討している.本報告では,ボード配線の寄生容量による共振に対するRLスナバの設計法を示した.まず,オンボード共振周波数における等価回路を簡略化することによって,回路の次数を3次から2次にし,デカップリングインダクタンスの範囲を限定した.次に,2次回路の臨界減衰条件より最適抵抗値を決定した.オンボード等価回路を2次の等価回路に簡略化する方法を述べた.最後に,決定したインダクタンスと抵抗値を電流伝達特性と入力インピーダンスの回路シミュレーションで評価し,等価回路を簡略化するために与えた条件が妥当かどうか検証した.その結果,与えた条件により簡略化前と同等な電流低減およびPI向上を維持できることを示した.また,実用的には条件をさらに緩和できることを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電子機器の多層プリント回路基板における平行平板構造の電源/グラウンド層において生じる平行平板共振は,種々の問題を引き起こす.この共振抑制には,「特定の周波数で生じる各々の平行平板共振に限定して効果的に共振が抑制できること」,また,「わずかな損失を与え,不要電磁波のパワーを効率よく消費すること」の2点が重要である.これに基づき,今回,このコンセプトの実施例としてオープンスタブと磁性膜から構成される損失を有する共振器型フィルタを提案する.本稿ではまず,提案した共振器型フィルタのコンセプトを,特にインピーダンス特性の観点から説明する.次に,電磁界シミュレーションにより3つの事例を対象に本提案フィルタの共振抑制効果を評価し,上述の所望の特性を得たことを述べる.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

空間中に存在する2導体線路に流れる電流はノーマルモードとコモンモードの成分に分離できることが知られている。我々はこれまでにプリント基板上の配線において線路の平衡度に着目してノーマルモード電圧から変換されるコモンモード電流・コモンモード放射の予測を行うアンテナモデルを構築してきた。実際のプリント基板構造からの放射はノーマルモード及びコモンモードの電流によつて生じているため、ノーマルモードによる放射も加味して、全放射量の予測が可能であるか検討した。対象として、3種類の単純な基板構造に対して、ノーマルモードおよびコモンモードのアンテナモデルを構築し、数値解析によって求めた各モードの放射電界のベクトル和と元々の基板構造から生じる放射電界を比較し、これがほぼ一致することを確認した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板の帰路面端に信号線が近づくことで生じるコモンモードの抑制手法として,ガードトレースは有効である.これまでの研究ではコモンモード放射の抑制にのみ着目していたが,ガードトレースが信号線に近づくことでクロストークが大きくなり信号品質の劣化を引き起こす.そこで,放射抑制効果を維持しつつ信号品質の劣化を抑えるため,本報告ではガードトレースへの周期構造導入を提案する.周期パターンを変化させた複数のテスト基板を作製し,透過特性とアイパターン,そして,コモンモード放射量を実測とシミュレーションにより評価した.その結果,周期構造導入により信号品質維持の効果が見られ,パターン周期を小さくすることで高周波まで効果の及ぶことを確認した.さらに,周期構造導入によるコモンモード放射抑制効果の低下の小さいことを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

暗号回路のサイドチャネル攻撃に対する安全性を評価する上で、サイドチャネル解析におけるノイズ成分の予測は重要な課題である。特に暗号IC内部で発生するノイズは、回路動作から推察すると暗号処理の進行に伴って変化する。そのため、測定によりノイズだけを同定するのは容易ではない。本報告では、筆者らが提案している暗号ICの等価電流源モデルに基づき、暗号IC内部で発生するノイズの変動を調査した。暗号回路への入力データ(平文)を一定とした時の電流源の標準偏差を計算し、その暗号処理中の変動を確認した。その結果、定性的な傾向として電流源振幅と標準偏差との間に正の相関があることを確認した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：英語  

In this study, equivalent circuit modeling was examined to develop a method to evaluate cryptographic systems before fabrication. An equivalent circuit model of a cryptographic FPGA in which an advanced encryption standard (AES) algorithm had been implemented was determined from experimental measurements under the initial configuration of a power distribution network (PDN) of the FPGA. The model was implemented into a commercial analog circuit simulator, and power traces due to the simultaneous switching noise current were estimated under three different PDN configurations in which a decoupling circuit was inserted into the PDN as an on-board countermeasure. Estimated power traces were analyzed statistically by the correlation power analysis method to obtain correlation values, a major security index of AES. Variation of the correlation values with changes in decoupling configuration agreed with the corresponding experimental results. This means that the security of cryptographic devices against side-channel attacks can be evaluated by using the equivalent circuit model before fabrication. © 1964-2012 IEEE.

DOI： 10.1109/TEMC.2013.2250505

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記述言語：英語   出版者・発行元：IEEE  

For investigating mode conversion in four-conductor transmission systems we have developed a modal-equivalent-circuit expressed by an imbalance factor of transmission line, a current division factor, in the same way as we developed the one in three-conductor transmission systems. The modal equivalent circuit consists of three modal equivalent circuits of normal mode, primary-common mode, and secondary-common mode. In this paper, the influence of mode conversion by the pigtail termination of a shielded-twisted-pair (STP) cable was analyzed using the modal equivalent circuit and mixed-mode S parameters with respect to normal mode and primary- common mode. As a result, it was found that mode conversion depends on the imbalance factor and that the modal equivalent circuit helps to explain mode conversion that occurs in terminating STP cables with pigtail.

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記述言語：英語  

Noise suppression and power integrity are two requirements for power/ground layers of printed circuit boards. To accomplish the requirements, we proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers. To evaluate the proposed EBG structure, we have so far measured the electric characteristics of both driving-point impedance and transmission coefficient. Although these evaluation indices are helpful, the evaluation using an actual device is also indispensable. In this paper, we evaluated the suppression of noise propagation through power bus by the proposed EBG structure in wireless communication module. The proposed structure provided sufficient result of the effective maintenance of communication quality by suppressing the propagation of electromagnetic noise. © 2013 IEEE.

DOI： 10.1109/EDAPS.2013.6724428

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記述言語：英語   出版者・発行元：IEEE  

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

DOI： 10.1109/ISEMC.2013.6670526

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記述言語：英語   出版者・発行元：IEEE  

The authors previously proposed a method based on a linear equivalent circuit model to predict vulnerability of cryptographic devices before fabrication. The method was verified to demonstrate the correlation power analysis attack, a major side-channel attack method, to a cryptographic device with outstanding accuracy. However, no obvious correlation was seen between the equivalent current source modeling the generation of the simultaneous switching noise (SSN) current in the circuit model and the encryption operation used in the previous study. Therefore, in this study, we improved the topology of the linear equivalent circuit model matched with the physical construction of the power distribution network (PDN) and re-identified the equivalent current source. By comparing the improved current source with the encryption operation, obvious correlations between them were found with respect to the period of the round operation and the dependency of the SSN current on the Hamming distance between successive intermediates. The improved equivalent current source was applied on a Field-Programmable Gate Array (FPGA) in which an Advance Encryption Standard (AES) circuit was implemented to simulate power traces that were confirmed to coincide with measured ones. Correlation between the simulated power traces and the power model was investigated using a set of 1000 plaintexts. As a result, the correlation coefficients agreed well with those for measured power traces. Improving the equivalent circuit model topology, thus, helped to identify the SSN current generated in the FPGA during the AES operation.

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記述言語：日本語   出版者・発行元：科学技術出版  

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記述言語：英語   出版者・発行元：IEEE  

For treating mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis, we have proposed a modal equivalent-circuit model with mode-conversion sources. The approach takes an advantage in less calculation sources and countermeasure consideration compared with full-wave simulation. A mode-decomposition technique was applied with an imbalance factor, that is, the current division factor in our study, of the transmission line. In the modal circuit analysis we proposed, mode conversion is expressed by the controlled sources of which magnitude is proportional to the difference between the current division factors of the adjacent transmission lines. In this paper, we focused on the modal transfer power and derived the mathematical expressions of the mode conversion using the modal characteristic impedance as well as the current division factor. For validating the derived equations, in addition, the comparison with full-wave simulation was carried out and a good agreement was confirmed.

DOI： 10.1109/EDAPS.2013.6724455

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記述言語：英語   出版者・発行元：IEEE  

An equivalent circuit model was evaluated in simulating data-dependent power voltage variations of a field-programmable gate array (FPGA). The equivalent circuit model was Linear Equivalent Circuit and Current Source (LECCS) model representing dynamic switching current inside the FPGA with an equivalent current source. The current source was supposed to depend on input data for the FPGA on which a cryptographic circuit was implemented. Model identification was based on the procedure of LECCS model identification from on-board measurements and the current source was identified for all values of input data used in this work. The identified current source was investigated in accordance with the operation process of the cryptographic circuit and found an excellent correlation to the operation process. The identified LECCS model was combined with an equivalent circuit of the power distribution network for the FPGA core circuit to simulate power voltage variations for the 1,000 input texts. The simulated variation waveforms were compared to the corresponding measured ones to evaluate the LECCS model. Results indicated that the simulated and measured power variations matched excellently for all input data with high cross-correlation coefficients from 0.7 to 0.9. LECCS model is, therefore, able to predict the data-dependent power voltage variation by combining a PDN equivalent circuit.

DOI： 10.1109/EMCCompo.2013.6735196

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

IC/LSIの同時スイッチングノイズに起因するEMI予測を目的として開発されたEMCマクロモデルを使用し、暗号モジュールのサイドチャネル攻撃に対する安全性を予測した。暗号モジュールとして市販のサイドチャネル攻撃標準評価プリント基板SASEBO-Gを使用し、AES暗号に対して相関電力解析によるサイドチャネル攻撃を仕掛けた時の安全性を、EMCマクロモデルと電源供給回路の線形等価回路を用いた回路シミュレーションによって予測した。EMCマクロモデルのインピーダンスおよび等価電流源はLECSSモデルの同定法を参考に実測により同定した。同定したEMCマクロモデルとPDNの線形等価回路を使い、ボード上の電源供給回路にローパスフィルタを挿入した場合について、相関電力解析で得られる相関係数を予測した。予測された相関係数は、同じフィルタ条件において実測したサイドチャネル信号を相関電力解析した時の相関係数とよく一致した。この結果は、暗号モジュールのサイドチャネル攻撃に対する安全性予測において、EMCマクロモデルを用いた等価回路解析が有効であることを示している。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

これまでに提案している平衡度の不整合に起因して生じるモード変換を考慮した等価モデルについて,統一したモデルとして取り扱えるようにするための初期検討を行った.今回は,試験基板とシステムグラウンドの距離を変え,等価モデルの結果と実構造モデルの3次元電磁界シミュレーションの結果と比較し,両者の結果が異なる場合について評価した.その結果,モデルの前提条件を満足しない条件下ではモデルの計算精度が低下することを確認した.コモンモードアンテナモデルではシステムグラウンドに近づけすぎると放射量を過大に算出した.これはコモンモードからノーマルモードへのモード変換を考慮できないためである.一方,モード変換励振源を有するモード等価回路では,放射による損失が考慮できないため,この影響が大きい場合に精度が悪くなった.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電子機器の省エネ化か進むなかで電力変換回路から発生する伝導妨害波の低減設計が重要となっている。伝導妨害波は規制値内に収めらければならない。本報告では、IC/LSIのEMCマクロモデルであるLECCSモデルをベースに構築した伝導妨害波を予測するための線形等価回路モデルについて述べる。またモデル構築のために作製したDual Port LISN(DP-LISN)についても報告する。今回はEUTに卓上IHを使用した。線形等価回路モデルの定数はDP-LISNの負荷抵抗を切り替えることで10組の負荷条件で伝導妨害波電圧を測定し、それらの最小二乗近似により決定した。構築した線形等価回路モデルを用いて伝導妨害波電圧シミュレーションを行い、その結果、シミュレーションによる伝導妨害波強度の周波数変化は実測結果と一致した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

PDNの寄生インピーダンスの共振により,直流電源側に漏れ出す高周波電流が増加する.本報告では,この問題の解決を目的として,デカップリングインダクタと並列に抵抗を挿入する共振抑制手法(RLダンパ回路)オン・ボード共振とチップ・パッケージ・ボード共振に適用した.二つの共振について,回路シミュレーションと実測を行い,RLダンパ回路を評価した.その結果,二つの共振を抑制でき,EMI低減とPI性能向上効果が確認された.また,無線通信モジュールの電源にノイズを注入したときの通信成功率の変化を計測し,イミュニティ改善効果についても検証した.その結果,注入されるノイズ周波数が共振周波数と一致する場合を除き,イミュニティ改善効果を確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

IC/LSIの電源品質(PI)および電磁環境適合(EMC)設計においてパッケージ部のインダクタンスを把握しておくことは重要である。本稿では、既に提案したボード実装状態におけるパッケージインダクタンス測定法について、測定精度を3次元電磁界シミュレーションに基づき検証した。提案法では半導体チップの代わりに伝送線路(LINE)をパッケージ内に埋め込み、測定したいパッケージ構造をLINEの両側に縦続接続した特性を2ポートSパラメータ測定する。取得したSパラメータと先に測定しておいたLINEの特性よりパッケージ部のインダクタンスを算出する。市販の電磁界シミュレータHFSSにおいて提案法を4種類の評価パッケージに適用し、パッケージインダクタンスを測定した。またパッケージ部のみを電磁界解析し別途パッケージインダクタンスを求め、提案法による結果と比較した。その結果、最大0.9nHの誤差で一致した。さらに誤差の原因として電磁界解析用のポートを設置する時に使用するダミーオブジェクトの影響を評価した。その結果、ダミーオブジェクトの使用に起因する誤差は最大0.06nHと十分小さいことを確認した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

我々は,モード等価回路による表現に着目し,モード変換に伴い生じる問題の発生メカニズムを明確にし,さらに,効果的な対策を施しやすくすることを目標として検討を行っている.提案法では,別々に構築したノーマルモード,コモンモード等価回路を,モード変換励振源により結び付けることで回路シミュレータにより解くことができる.本稿では,モード等価回路を用いた解析の有効性を調べるため,送受信器間に中継器が存在する場合と電流プローブによりコモンモード励振を行う場合を対象として検討した.ノーマルモード電圧スペクトル,コモンモード電流スペクトルを用いて評価したところ,モード等価回路による解析結果は現象を精度よく再現できることが分かった.

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記述言語：日本語  

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記述言語：日本語  

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記述言語：日本語   出版者・発行元：エレクトロニクス実装学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

ICパッケージ電気特性のモデリングにおいて,電磁界シミュレーションに基づき構築したモデルを実測結果と比較することは,一つの重要なモデル精度検証方法である.しかし,過去の報告では,パッケージを開封した状態での測定例が報告されているのみであり,パッケージを封止した状態での測定例は見られない.筆者らは,封止かつボード実装された状態におけるパッケージ特性の測定法を検討しており,本報告では、自己インダクタンスの測定法を検討した.提案法では,特性が既知のTHRUラインを用いて,そのTHRUラインをチップ部にマウントしたパッケージをPCB上に実装し,PCB上の測定結果からパッケージ部の自己インダクタンスを抽出する.そして,実測および3次元電磁界解析により抽出精度を検証した.その結果,500 MHz以下で実測では-0.8〜-0.2 nH,電磁界解析では-0.9〜-0.6nHの絶対誤差で自己インダクタンスを測定できた.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板の電源/グラウンド層間における高周波ノイズ伝搬阻止のため,電磁的バンドギャップ(Electromagnetic Bandgap : EBG)構造の層間への適用が検討されている.2本のスタブを用いたオープンスタブ型EBG構造では,セルサイズの小型化,阻止域の拡大およびマルチバンド化が期待できる.本稿では,等価回路モデルを用いたマッシュルーム型EBG構造やスタブ1本のオープンスタブ型EBG構造との比較を行い,その特性を明らかにする.さらに,オープンスタブ型EBG構造において,無線LAN使用周波数である2.4GHz, 5.2GHzの周波数帯域に阻止域を得るための設計手法を検討した.最終的に,2本の異なる長さのスタブをもつオープンスタブ型EBG構造により,2.4GHz, 5.2GHz帯のそれぞれに2つの阻止域が形成できることを確認した.最後に,特性量を利用した等価回路解析と物理的なサイズまでを考慮した電磁界シミュレータによる解析を比較し,等価回路モデルにおけるスパイラル状スタブの等価長について考察を行った.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電流配分率の異なる線路が接続された3導体で構成される伝送系では,線路の接続点においてモード変換が生じる.モード変換を回路上で表現するモ-ド変換励振源を用いて,送受信機器が平行2本線路で接続された系を対象としてモード等価回路を構築した.このモード等価回路の実測における有効性を,コモンモード電流とノーマルモード電圧を用いて評価した.実測と回路シミュレーションのスペクトルは概ね良く一致し,モード変換の影響によって,コモンモードの共振時にコモンモードからノーマルモードヘの変換によりノーマルモード電圧が影響を受けることを確認した.そこでモード変換励振源のパラメータである2つの線路の電流配分率の差とコモンモード電流に着目して,モード変換の抑制を試みた.対策を行ったその結果,回路シミュレーションで予測されたように,モード変換の影響を低減することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板(Printed Circuit Board : PCB)の電源層が具備すべき条件は,高周波ノイズの伝搬阻止と電源バウンスの生じない電源供給である.我々は,PCBの電源-グラウンド層に対して,電磁バンドギャップ(Electromagnetic Bandgap : EBG)構造の導入に加え,磁気損失効果のあるフェライト膜を電源-グラウンド層間へ挿入した電源層が有効であると考えている.本論文では,この提案構造のテスト基板と,これと比較するための3種類のテスト基板を作製し,ネットワークアナライザを用いたSパラメータの2ポート測定により,不要電磁波(Electromagnetic Interference : EMI)抑制と電源品質(Power Integrity : PI)の両特性を評価した.さらに,PI特性については実際の回路への導入を想定し,模擬電源回路と組み合わせた場合の評価を回路シミュレータを用いて検討した.提案構造はEMI抑制,PI特性とも良好な結果を得た.同様にEBG構造ではないベタ層とフェライト膜を組み合わせたテスト基板も提案構造と同等の結果が得られることが分かった.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

暗号ICから漏れ出す高周波電源電流などの副次的な情報から暗号を解読するサイドチャネル攻撃が問題になっている.本報告では,この問題のハードウェア的な対策技術として電源系デカップリングの有効性を実験により確認した.デカップリング回路はキャパシタとインダクタで構成し,デカップリングしない場合も含め3つの条件を試行した.実験にはサイドチャネル標準評価基板SASEBO-Gを用い,AES (Advanced Encryption Standard)暗号処理中に電源線を流れる高周波電源電流をカレントプローブで観測した.取得した30,000波形に対し相関電力解析(Correlation Power Analysis: CPA)を行った.その結果,2つのデカップリング条件のうち1つでサイドチャネル攻撃耐性が向上した.もうひとつの条件では変化がなかった.取得波形のスペクトルを調査した結果,耐性が向上した条件ではFPGA (Field-Programmable Gate Array)のクロック周波数より低周波の全域で高周波電源電流が低減されていた.また,この電源電流低減がデカップリングの結果であることを回路シミュレーションにより確認した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

送受信器が平行ケーブルで接続された3導体系の伝送線路が,システムグラウンドからある一定の距離を隔てて設置されている場合を対象として,モード等価回路を構築した.実電圧・電流の直交モード分解に基づき導出された直交モードの変換行列は,モード電圧間,モード電流間のみのモード変換を表現する.電流配分率の異なる線路を接続した場合では,線路の接続位置にモード変換電圧源やモード変換電流源を挿入することに相当する.モデル評価では,誘電体を含まない導体のみからなる簡単な系を対象とした.提案法では,ノーマルモード等価回路,コモンモード等価回路を別々に構築し,モード変換電圧源やモード変換電流源に両者を結び付けることで回路シミュレータを用いて解くことができる.解析対象を結合伝送線路と考えて回路シミュレーションで解いた場合とは非常によく一致した.さらに,フルウェーブ計算で得られたモード電流のスペクトルとも概ねよく一致した.フルウェーブ計算ではTEMモードが前提ではないため,TEMモードからのずれが計算結果に影響することを確認した.

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記述言語：日本語   出版者・発行元：山陽放送学術文化財団  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

デカップリングキャパシタを実装することで,デカップリングキャパシタが持つESLと電源系パターンの寄生容量が共振を起こし,IC/LSIのスイッチングに起因する高周波電流が増加する場合がある.本報告では,この問題について述べ,対策法としてデカップリングインダクタの配置について検討し,電源端子電流の低減効果をシミュレーションにより確認した.DUTとして,汎用ロジックICを実装した25mm角のプリント基板を用い,シミュレーションにはLECCSモデルを使用した.その結果,寄生のキャパシタよりIC側にデカップリングインダクタを挿入した場合には,低周波において鋭いピークがみられるものの,高周波電流を大きく低減できることを示した.さらに,寄生のキャパシタより外部にデカップリングインダクタを挿入した場合には,電源端子電流を全周波数において低減できることを示した.また,チップ部の電源端子間の電位差をシミュレーションし,PIへの影響は十分小さいことを確認した.

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記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In a differential transmission line, a large common-mode radiation is excited due to its asymmetry. In this paper, the imbalance difference model, which was proposed by the authors for estimation of common-mode radiation, is extended to apply to the differential signaling systems. The authors focus on a differential transmission line with asymmetric property, which consists of an adjacent return plane and two signal lines which are placed close to an edge of the return plane. Three orthogonal transmission modes, a normal mode, a primary common mode and a secondary common mode, are defined. Among these transmission modes, the secondary common mode is dominant in radiation, and a mechanism of the secondary common-mode generation is explained. The radiated emission which was calculated using the imbalance difference model was in good agreement with that obtained by full wave calculation.

DOI： 10.1587/transcom.E93.B.1739

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記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

We propose a novel technique of matching at both ends of the guard trace to suppress resonance. This approach is derived from the viewpoint that the guard trace acts as a transmission line. We examined that matched termination suppresses guard-trace resonance through simulating a circuit and measuring radiation. We found from these results that the proposed method enables guard-trace voltages to remain low and hence avoids increases in radiation. In addition, we demonstrated that "matched termination at the far end of the guard trace" could suppress guard-trace resonance sufficiently at all frequencies. We eventually found that at least two vias at both ends of the guard trace and only one matching resistor at the far end could suppress guard-trace resonance. With respect to fewer vias, the method we propose has the advantage of reducing restrictions in the printed circuit board layout at the design stage.

DOI： 10.1587/transcom.E93.B.1746

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

インバータやコンバータのようにスイッチング電源を内蔵した家電製品の電源ポート伝導妨害波を低減する電源フィルタ設計への適用を目的として、インバータの線形等価回路モデルを構築した。まず、市販電子レンジを被試験体として疑似電源回路網(LISN)を用いて伝導妨害波電圧を測定した。その結果にディファレンシャルモードおよびコモンモードどちらのノイズも確認されたため、両モードを表現する等価回路構造を決定し、モデル定数を決定する手法を述べた。さらに実際に伝導妨害波電流測定よりモデル定数を決定した。最後に構築したモデルを使い回路シミュレーションにより電磁妨害波電圧を予測し測定結果と比較した。その結果、決定したモデル定数が有意であった周波数においてはEMIフィルタによるノイズ低減効果を実用的な精度で予測した。これにより測定による構築可能なマクロモデルのEMIフィルタ設計への適用可能性を示した。

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

本文データは学協会の許諾に基づきCiNiiから複製したものである

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板上の伝送系の帰路面にスリットパターンを導入することにより,それ自体が何らかの受動素子のような振る舞いをする.DGS(Defected Ground Structure)もその1つである.DGSは,導入するスリットパターンによりその伝搬特性が大きく変化するため,フィルタなど様々な用途への応用が期待される.しかし,導入するスリットパターンの設計手法が確立されていないため,明確な設計手法モデルが必要である.3次元電磁界シミュレータによる解析ではコストが大きいうえ,最終的な特性と構造の相関関係が不明確である.これまでにいくつかの等価回路モデルが利用されているが,それらは集中定数モデルで,さらに3次元解析を必要とする.また,集中定数素子の値は物理構造とは対応しておらず設計に用いるのは困難である.本報告では,フィルタとして機能するDGSに着目し,伝送線路モデルを用いた等価回路モデルの構築を行った.3次元解析の結果と等価回路モデルを回路解析した結果の透過特性を比較すると,フィルタとして一般的に利用される第一伝搬阻止域は概ね一致した.

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記述言語：英語  

DOI： 10.1109/ISEMC.2010.5711310

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記述言語：英語   出版者・発行元：IEEE  

The noise suppression effect after interposing a ferrite film of several microns in thickness between the power and ground planes is discussed in this paper. In particular, we focused on the combination of a planar electromagnetic bandgap structure with a ferrite film deposited by using spin spray ferrite plating at a low temperature. In this paper, the stopband characteristics are discussed through the use of both simulation and measurement results. First, a full-wave electromagnetic simulation revealed that a test board with a dielectric as thin as a few hundreds of microns has the stopband characteristics of the frequency shift towards the lower frequencies (miniaturization effect) and stopband expansion with the removal of the passband, which was not observed in the case of a thick-dielectric test board. The simulation results also demonstrated that these improvements mainly resulted from the complex permeability of the ferrite film. Next, we found that the measurements are very similar to the simulation results.

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記述言語：英語   出版者・発行元：IEEE  

The noise suppression effect after interposing a ferrite film of several microns in thickness between the power and ground planes is discussed in this paper. In particular, we focused on the combination of a planar electromagnetic bandgap structure with a ferrite film deposited by using spin spray ferrite plating at a low temperature. In this paper, the stopband characteristics are discussed through the use of both simulation and measurement results. First, a full-wave electromagnetic simulation revealed that a test board with a dielectric as thin as a few hundreds of microns has the stopband characteristics of the frequency shift towards the lower frequencies (miniaturization effect) and stopband expansion with the removal of the passband, which was not observed in the case of a thick-dielectric test board. The simulation results also demonstrated that these improvements mainly resulted from the complex permeability of the ferrite film. Next, we found that the measurements are very similar to the simulation results.

DOI： 10.1109/APEMC.2010.5475608

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記述言語：英語   出版者・発行元：IEEE  

The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator.

DOI： 10.1109/ISEMC.2010.5711287

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電源系解析用ICマクロモデルLECCS(Linear Equivalent Circuit and Current Source)を,バイパス回路設計に適用する.EMI(Electromagnetic Interference:不要電磁輻射)低減とPI(Power Integrity:電源安定性)確保を設計要件とし,LECCSモデルを用いて各性能を向上するための方策について検討した.LECCSモデルは線形等価回路と等価内部電流源より構成されるが,EMI性能と線形等価回路,PI性能と等価内部電流源が密接に関連し,各方策が異なることを述べる.方策に基づいたバイパス回路の設計例を示し,SPICEモデルを用いてその効果を検証した結果,機能することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電源系解析用ICマクロモデルLECCS(Linear Equivalent Circuit and Current Source)を,バイパス回路設計に適用する.EMI(Electromagnetic Interference:不要電磁輻射)低減とPI(Power Integrity:電源安定性)確保を設計要件とし,LECCSモデルを用いて各性能を向上するための方策について検討した.LECCSモデルは線形等価回路と等価内部電流源より構成されるが,EMI性能と線形等価回路,PI性能と等価内部電流源が密接に関連し,各方策が異なることを述べる.方策に基づいたバイパス回路の設計例を示し,SPICEモデルを用いてその効果を検証した結果,機能することを確認した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板のEMC設計において,IC/LSIのEMCマクロモデルの優位性はますます高まっている.EMI放射は電源だけでなく出力系の高周波電流も原因となるため,出力端子電流モデル化も重要である.本報告では,従来電源系解析だけでなく出力系解析を考慮したLECCS-I/Oモデルを構築する.測定より二つ電流源をもつLECCS-I/Oモデル構築し,電源および出力端子電流のシミュレーション精度を検証した.また電流源が一つのLECCS-I/Oモデルとの比較も行った.その結果,電源電流シミュレーションでは,両モデルとも500MHz以下の周波数で精度よく一致していた.一方,出力電流シミュレーションでは,電流源が一つの場合に大きな誤差が生じているのに対して,電流源が二つの場合では500MHz以下の周波数で精度よく一致した.

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記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Placing a guard trace next to a signal line is the conventional technique for reducing the common-mode radiation from a printed circuit board. In this paper, the suppression of common-mode radiation from printed circuit boards having guard traces is estimated and evaluated using the imbalance difference model, which was proposed by the authors. To reduce common-mode radiation further, a procedure for designing a transmission line with guard traces is proposed. Guard traces connected to a return plane through vias are placed near a signal line and they decrease a current division factor (CDF). The CDF represents the degree of imbalance of a transmission line, and a common-mode electromotive force depends on the CDF Thus, by calculating the CDF, we can estimate the reduction in common-mode radiation. It is reduced not only by placing guard traces, but also by narrowing the signal line to compensate for the variation in characteristic impedance due to the guard traces. Experimental results showed that the maximum reduction in common-mode radiation was about 14 dB achieved by placing guard traces on both sides of the signal line, and the calculated reduction agreed with the measured one within 1 dB. According to the CDF and characteristic impedance calculations, common-mode radiation can be reduced by about 25 dB while keeping the characteristic impedance constant by changing the gap between the signal line and the guard trace and by narrowing the width of the signal line.

DOI： 10.1587/transcom.E92.B.2193

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記述言語：英語   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A guard trace placed near a signal line reduces common-mode radiation front a printed circuit board. The reduction effect is evaluated by the imbalance difference model, which was proposed by the authors, when the guard trace has exactly the same potential as the return plane. However, depending on interval of ground connection of the guard trace, the radiation can increase when the guard trace resonates. In this paper, the authors show that the increase of radiation is caused by the common mode, and extend the imbalance difference model to explain a mechanism of increase of common-mode radiation. Additionally, the effective via location of the guard trace is proposed to reduce the number of vias. The guard trace voltage due to the resonance excites the common mode at the interface where the cross-sectional structure of the transmission line changes since the common-mode excitation is expressed by the product of the voltage and the difference of current division factors. To suppress the common-mode excitation, the guard trace should be grounded at the point where the cross-sectional structure changes. As a result, the common-mode radiation decreases even when the guard trace resonates.

DOI： 10.1587/transcom.E92.B.1929

Web of Science

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

プリント回路基板の電源/グランドプレーンに形成した電磁バンドギャップ(Electromagnetic Bandgap:EBG)構造は,帯域阻止フィルタとして動作し,不要電磁波伝搬の抑制に有効である.我々はこれまでに,ノイズ抑制シートを電源/グランド層間へ挿入することがEBG構造の小型化及び高周波側への阻止域の拡大を実現することに有効であることを実験的に示している.しかし,実験で使用したノイズ抑制シートの透磁率が小さくなる高周波数域で小型化の効果が見られた.本報告ではノイズ抑制シートの誘電率に着目し,飽和磁界を印加した状態でSパラメータ測定を行うことで誘電率と透磁率の効果を切り分けて評価した.EBG構造にノイズ抑制シートを適用した場合の阻止域の低周波側へのシフトは,ノイズ抑制シートの異方性誘電率の効果によることが判明した.これは特にスリットにおける面内方向の電界成分に作用したためである.これは,市販の電磁界シミュレータMicrowave Studioを用いた計算でも再現できた.この結果を踏まえて,EBGパターンへの効果的なノイズ抑制シートの適用法を実験的に示した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

1GHzを超えるEMIは自由空間で測定するように規定されている。この測定に使用するサイトの評価を行なう方法として、CISPR 16-1-4にサイトVSRW法が規定されている。このサイトVSWR法では、400mmの範囲に6点の測定ポイントを設けて、その点からの伝達特性の最大・最小によって自由空間条件の評価を行なう。この測定法では、測定ポイント数が少ないために測定結果に大きな不確かさを生じている。この測定は周波数間隔が50MHz以下で測定を行なうことが規定されている。一般的には、上限の50MHz間隔で測定を行なうが、我々は、測定周波数ステップを小さくすることによって不確かさを低減させる手法を提案し、実際の測定によってその効果を確認した。また、この手法では測定点の設定誤差に対する不確かさも低減できることを示した。

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記述言語：日本語   出版者・発行元：社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

IC/LSIの高周波電流による電磁妨害波(EMI, Electromagnetic Interference)のシミュレーションヘの適用を目的として,ドライバ回路のマクロモデルを構築する.従来は,ドライバ回路の動作モデルとしてIBIS (Input/output Buffer Information Specification)モデルが幅広く使われてきた.しかし,IBISモデルは信号系解析用モデルであり,EMIシミュレーションに用いると誤差が大きいという問題がある.そこで,EMIシミュレーションにも適用可能な新しいマクロモデルを提案する.トランジスタの静特性に着目し,IBISモデルより静特性のモデリング精度を向上させた.実際にドライバ回路について提案するマクロモデルを構築し,IBISモデルとの比較シミュレーションを実施した.その結果,IBISモデルに比べて高精度な結果が得られた.

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